1 /* 2 * QEMU model of the IPI Inter Processor Interrupt block 3 * 4 * Copyright (c) 2014 Xilinx Inc. 5 * 6 * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> 7 * Written by Alistair Francis <alistair.francis@xilinx.com> 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/sysbus.h" 30 #include "migration/vmstate.h" 31 #include "hw/register.h" 32 #include "qemu/bitops.h" 33 #include "qemu/log.h" 34 #include "qemu/module.h" 35 #include "hw/intc/xlnx-zynqmp-ipi.h" 36 #include "hw/irq.h" 37 38 #ifndef XLNX_ZYNQMP_IPI_ERR_DEBUG 39 #define XLNX_ZYNQMP_IPI_ERR_DEBUG 0 40 #endif 41 42 #define DB_PRINT_L(lvl, fmt, args...) do {\ 43 if (XLNX_ZYNQMP_IPI_ERR_DEBUG >= lvl) {\ 44 qemu_log(TYPE_XLNX_ZYNQMP_IPI ": %s:" fmt, __func__, ## args);\ 45 } \ 46 } while (0) 47 48 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 49 50 REG32(IPI_TRIG, 0x0) 51 FIELD(IPI_TRIG, PL_3, 27, 1) 52 FIELD(IPI_TRIG, PL_2, 26, 1) 53 FIELD(IPI_TRIG, PL_1, 25, 1) 54 FIELD(IPI_TRIG, PL_0, 24, 1) 55 FIELD(IPI_TRIG, PMU_3, 19, 1) 56 FIELD(IPI_TRIG, PMU_2, 18, 1) 57 FIELD(IPI_TRIG, PMU_1, 17, 1) 58 FIELD(IPI_TRIG, PMU_0, 16, 1) 59 FIELD(IPI_TRIG, RPU_1, 9, 1) 60 FIELD(IPI_TRIG, RPU_0, 8, 1) 61 FIELD(IPI_TRIG, APU, 0, 1) 62 REG32(IPI_OBS, 0x4) 63 FIELD(IPI_OBS, PL_3, 27, 1) 64 FIELD(IPI_OBS, PL_2, 26, 1) 65 FIELD(IPI_OBS, PL_1, 25, 1) 66 FIELD(IPI_OBS, PL_0, 24, 1) 67 FIELD(IPI_OBS, PMU_3, 19, 1) 68 FIELD(IPI_OBS, PMU_2, 18, 1) 69 FIELD(IPI_OBS, PMU_1, 17, 1) 70 FIELD(IPI_OBS, PMU_0, 16, 1) 71 FIELD(IPI_OBS, RPU_1, 9, 1) 72 FIELD(IPI_OBS, RPU_0, 8, 1) 73 FIELD(IPI_OBS, APU, 0, 1) 74 REG32(IPI_ISR, 0x10) 75 FIELD(IPI_ISR, PL_3, 27, 1) 76 FIELD(IPI_ISR, PL_2, 26, 1) 77 FIELD(IPI_ISR, PL_1, 25, 1) 78 FIELD(IPI_ISR, PL_0, 24, 1) 79 FIELD(IPI_ISR, PMU_3, 19, 1) 80 FIELD(IPI_ISR, PMU_2, 18, 1) 81 FIELD(IPI_ISR, PMU_1, 17, 1) 82 FIELD(IPI_ISR, PMU_0, 16, 1) 83 FIELD(IPI_ISR, RPU_1, 9, 1) 84 FIELD(IPI_ISR, RPU_0, 8, 1) 85 FIELD(IPI_ISR, APU, 0, 1) 86 REG32(IPI_IMR, 0x14) 87 FIELD(IPI_IMR, PL_3, 27, 1) 88 FIELD(IPI_IMR, PL_2, 26, 1) 89 FIELD(IPI_IMR, PL_1, 25, 1) 90 FIELD(IPI_IMR, PL_0, 24, 1) 91 FIELD(IPI_IMR, PMU_3, 19, 1) 92 FIELD(IPI_IMR, PMU_2, 18, 1) 93 FIELD(IPI_IMR, PMU_1, 17, 1) 94 FIELD(IPI_IMR, PMU_0, 16, 1) 95 FIELD(IPI_IMR, RPU_1, 9, 1) 96 FIELD(IPI_IMR, RPU_0, 8, 1) 97 FIELD(IPI_IMR, APU, 0, 1) 98 REG32(IPI_IER, 0x18) 99 FIELD(IPI_IER, PL_3, 27, 1) 100 FIELD(IPI_IER, PL_2, 26, 1) 101 FIELD(IPI_IER, PL_1, 25, 1) 102 FIELD(IPI_IER, PL_0, 24, 1) 103 FIELD(IPI_IER, PMU_3, 19, 1) 104 FIELD(IPI_IER, PMU_2, 18, 1) 105 FIELD(IPI_IER, PMU_1, 17, 1) 106 FIELD(IPI_IER, PMU_0, 16, 1) 107 FIELD(IPI_IER, RPU_1, 9, 1) 108 FIELD(IPI_IER, RPU_0, 8, 1) 109 FIELD(IPI_IER, APU, 0, 1) 110 REG32(IPI_IDR, 0x1c) 111 FIELD(IPI_IDR, PL_3, 27, 1) 112 FIELD(IPI_IDR, PL_2, 26, 1) 113 FIELD(IPI_IDR, PL_1, 25, 1) 114 FIELD(IPI_IDR, PL_0, 24, 1) 115 FIELD(IPI_IDR, PMU_3, 19, 1) 116 FIELD(IPI_IDR, PMU_2, 18, 1) 117 FIELD(IPI_IDR, PMU_1, 17, 1) 118 FIELD(IPI_IDR, PMU_0, 16, 1) 119 FIELD(IPI_IDR, RPU_1, 9, 1) 120 FIELD(IPI_IDR, RPU_0, 8, 1) 121 FIELD(IPI_IDR, APU, 0, 1) 122 123 /* APU 124 * RPU_0 125 * RPU_1 126 * PMU_0 127 * PMU_1 128 * PMU_2 129 * PMU_3 130 * PL_0 131 * PL_1 132 * PL_2 133 * PL_3 134 */ 135 int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27}; 136 static const char *index_array_names[NUM_IPIS] = {"APU", "RPU_0", "RPU_1", 137 "PMU_0", "PMU_1", "PMU_2", 138 "PMU_3", "PL_0", "PL_1", 139 "PL_2", "PL_3"}; 140 141 static void xlnx_zynqmp_ipi_set_trig(XlnxZynqMPIPI *s, uint32_t val) 142 { 143 int i, ipi_index, ipi_mask; 144 145 for (i = 0; i < NUM_IPIS; i++) { 146 ipi_index = index_array[i]; 147 ipi_mask = (1 << ipi_index); 148 DB_PRINT("Setting %s=%d\n", index_array_names[i], 149 !!(val & ipi_mask)); 150 qemu_set_irq(s->irq_trig_out[i], !!(val & ipi_mask)); 151 } 152 } 153 154 static void xlnx_zynqmp_ipi_set_obs(XlnxZynqMPIPI *s, uint32_t val) 155 { 156 int i, ipi_index, ipi_mask; 157 158 for (i = 0; i < NUM_IPIS; i++) { 159 ipi_index = index_array[i]; 160 ipi_mask = (1 << ipi_index); 161 DB_PRINT("Setting %s=%d\n", index_array_names[i], 162 !!(val & ipi_mask)); 163 qemu_set_irq(s->irq_obs_out[i], !!(val & ipi_mask)); 164 } 165 } 166 167 static void xlnx_zynqmp_ipi_update_irq(XlnxZynqMPIPI *s) 168 { 169 bool pending = s->regs[R_IPI_ISR] & ~s->regs[R_IPI_IMR]; 170 171 DB_PRINT("irq=%d isr=%x mask=%x\n", 172 pending, s->regs[R_IPI_ISR], s->regs[R_IPI_IMR]); 173 qemu_set_irq(s->irq, pending); 174 } 175 176 static uint64_t xlnx_zynqmp_ipi_trig_prew(RegisterInfo *reg, uint64_t val64) 177 { 178 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); 179 180 xlnx_zynqmp_ipi_set_trig(s, val64); 181 182 return val64; 183 } 184 185 static void xlnx_zynqmp_ipi_trig_postw(RegisterInfo *reg, uint64_t val64) 186 { 187 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); 188 189 /* TRIG generates a pulse on the outbound signals. We use the 190 * post-write callback to bring the signal back-down. 191 */ 192 s->regs[R_IPI_TRIG] = 0; 193 194 xlnx_zynqmp_ipi_set_trig(s, 0); 195 } 196 197 static uint64_t xlnx_zynqmp_ipi_isr_prew(RegisterInfo *reg, uint64_t val64) 198 { 199 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); 200 201 xlnx_zynqmp_ipi_set_obs(s, val64); 202 203 return val64; 204 } 205 206 static void xlnx_zynqmp_ipi_isr_postw(RegisterInfo *reg, uint64_t val64) 207 { 208 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); 209 210 xlnx_zynqmp_ipi_update_irq(s); 211 } 212 213 static uint64_t xlnx_zynqmp_ipi_ier_prew(RegisterInfo *reg, uint64_t val64) 214 { 215 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); 216 uint32_t val = val64; 217 218 s->regs[R_IPI_IMR] &= ~val; 219 xlnx_zynqmp_ipi_update_irq(s); 220 return 0; 221 } 222 223 static uint64_t xlnx_zynqmp_ipi_idr_prew(RegisterInfo *reg, uint64_t val64) 224 { 225 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); 226 uint32_t val = val64; 227 228 s->regs[R_IPI_IMR] |= val; 229 xlnx_zynqmp_ipi_update_irq(s); 230 return 0; 231 } 232 233 static const RegisterAccessInfo xlnx_zynqmp_ipi_regs_info[] = { 234 { .name = "IPI_TRIG", .addr = A_IPI_TRIG, 235 .rsvd = 0xf0f0fcfe, 236 .ro = 0xf0f0fcfe, 237 .pre_write = xlnx_zynqmp_ipi_trig_prew, 238 .post_write = xlnx_zynqmp_ipi_trig_postw, 239 },{ .name = "IPI_OBS", .addr = A_IPI_OBS, 240 .rsvd = 0xf0f0fcfe, 241 .ro = 0xffffffff, 242 },{ .name = "IPI_ISR", .addr = A_IPI_ISR, 243 .rsvd = 0xf0f0fcfe, 244 .ro = 0xf0f0fcfe, 245 .w1c = 0xf0f0301, 246 .pre_write = xlnx_zynqmp_ipi_isr_prew, 247 .post_write = xlnx_zynqmp_ipi_isr_postw, 248 },{ .name = "IPI_IMR", .addr = A_IPI_IMR, 249 .reset = 0xf0f0301, 250 .rsvd = 0xf0f0fcfe, 251 .ro = 0xffffffff, 252 },{ .name = "IPI_IER", .addr = A_IPI_IER, 253 .rsvd = 0xf0f0fcfe, 254 .ro = 0xf0f0fcfe, 255 .pre_write = xlnx_zynqmp_ipi_ier_prew, 256 },{ .name = "IPI_IDR", .addr = A_IPI_IDR, 257 .rsvd = 0xf0f0fcfe, 258 .ro = 0xf0f0fcfe, 259 .pre_write = xlnx_zynqmp_ipi_idr_prew, 260 } 261 }; 262 263 static void xlnx_zynqmp_ipi_reset(DeviceState *dev) 264 { 265 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(dev); 266 int i; 267 268 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { 269 register_reset(&s->regs_info[i]); 270 } 271 272 xlnx_zynqmp_ipi_update_irq(s); 273 } 274 275 static void xlnx_zynqmp_ipi_handler(void *opaque, int n, int level) 276 { 277 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque); 278 uint32_t val = (!!level) << n; 279 280 DB_PRINT("IPI input irq[%d]=%d\n", n, level); 281 282 s->regs[R_IPI_ISR] |= val; 283 xlnx_zynqmp_ipi_set_obs(s, s->regs[R_IPI_ISR]); 284 xlnx_zynqmp_ipi_update_irq(s); 285 } 286 287 static void xlnx_zynqmp_obs_handler(void *opaque, int n, int level) 288 { 289 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque); 290 291 DB_PRINT("OBS input irq[%d]=%d\n", n, level); 292 293 s->regs[R_IPI_OBS] &= ~(1ULL << n); 294 s->regs[R_IPI_OBS] |= (level << n); 295 } 296 297 static const MemoryRegionOps xlnx_zynqmp_ipi_ops = { 298 .read = register_read_memory, 299 .write = register_write_memory, 300 .endianness = DEVICE_LITTLE_ENDIAN, 301 .valid = { 302 .min_access_size = 4, 303 .max_access_size = 4, 304 }, 305 }; 306 307 static void xlnx_zynqmp_ipi_realize(DeviceState *dev, Error **errp) 308 { 309 qdev_init_gpio_in_named(dev, xlnx_zynqmp_ipi_handler, "IPI_INPUTS", 32); 310 qdev_init_gpio_in_named(dev, xlnx_zynqmp_obs_handler, "OBS_INPUTS", 32); 311 } 312 313 static void xlnx_zynqmp_ipi_init(Object *obj) 314 { 315 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(obj); 316 DeviceState *dev = DEVICE(obj); 317 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 318 RegisterInfoArray *reg_array; 319 char *irq_name; 320 int i; 321 322 memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IPI, 323 R_XLNX_ZYNQMP_IPI_MAX * 4); 324 reg_array = 325 register_init_block32(DEVICE(obj), xlnx_zynqmp_ipi_regs_info, 326 ARRAY_SIZE(xlnx_zynqmp_ipi_regs_info), 327 s->regs_info, s->regs, 328 &xlnx_zynqmp_ipi_ops, 329 XLNX_ZYNQMP_IPI_ERR_DEBUG, 330 R_XLNX_ZYNQMP_IPI_MAX * 4); 331 memory_region_add_subregion(&s->iomem, 332 0x0, 333 ®_array->mem); 334 sysbus_init_mmio(sbd, &s->iomem); 335 sysbus_init_irq(sbd, &s->irq); 336 337 for (i = 0; i < NUM_IPIS; i++) { 338 qdev_init_gpio_out_named(dev, &s->irq_trig_out[i], 339 index_array_names[i], 1); 340 341 irq_name = g_strdup_printf("OBS_%s", index_array_names[i]); 342 qdev_init_gpio_out_named(dev, &s->irq_obs_out[i], 343 irq_name, 1); 344 g_free(irq_name); 345 } 346 } 347 348 static const VMStateDescription vmstate_zynqmp_pmu_ipi = { 349 .name = TYPE_XLNX_ZYNQMP_IPI, 350 .version_id = 1, 351 .minimum_version_id = 1, 352 .fields = (const VMStateField[]) { 353 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIPI, R_XLNX_ZYNQMP_IPI_MAX), 354 VMSTATE_END_OF_LIST(), 355 } 356 }; 357 358 static void xlnx_zynqmp_ipi_class_init(ObjectClass *klass, void *data) 359 { 360 DeviceClass *dc = DEVICE_CLASS(klass); 361 362 dc->reset = xlnx_zynqmp_ipi_reset; 363 dc->realize = xlnx_zynqmp_ipi_realize; 364 dc->vmsd = &vmstate_zynqmp_pmu_ipi; 365 } 366 367 static const TypeInfo xlnx_zynqmp_ipi_info = { 368 .name = TYPE_XLNX_ZYNQMP_IPI, 369 .parent = TYPE_SYS_BUS_DEVICE, 370 .instance_size = sizeof(XlnxZynqMPIPI), 371 .class_init = xlnx_zynqmp_ipi_class_init, 372 .instance_init = xlnx_zynqmp_ipi_init, 373 }; 374 375 static void xlnx_zynqmp_ipi_register_types(void) 376 { 377 type_register_static(&xlnx_zynqmp_ipi_info); 378 } 379 380 type_init(xlnx_zynqmp_ipi_register_types) 381