1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "cpu.h" 33 #include "qapi/visitor.h" 34 #include "qemu/range.h" 35 #include "hw/isa/isa.h" 36 #include "hw/sysbus.h" 37 #include "migration/vmstate.h" 38 #include "hw/i386/pc.h" 39 #include "hw/irq.h" 40 #include "hw/isa/apm.h" 41 #include "hw/i386/ioapic.h" 42 #include "hw/pci/pci.h" 43 #include "hw/pci/pci_bridge.h" 44 #include "hw/i386/ich9.h" 45 #include "hw/acpi/acpi.h" 46 #include "hw/acpi/ich9.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/qdev-properties.h" 49 #include "exec/address-spaces.h" 50 #include "sysemu/sysemu.h" 51 #include "qom/cpu.h" 52 #include "hw/nvram/fw_cfg.h" 53 #include "qemu/cutils.h" 54 55 /*****************************************************************************/ 56 /* ICH9 LPC PCI to ISA bridge */ 57 58 static void ich9_lpc_reset(DeviceState *qdev); 59 60 /* chipset configuration register 61 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 62 * are used. 63 * Although it's not pci configuration space, it's little endian as Intel. 64 */ 65 66 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 67 { 68 int intx; 69 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 70 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 71 } 72 } 73 74 static void ich9_cc_update(ICH9LPCState *lpc) 75 { 76 int slot; 77 int pci_intx; 78 79 const int reg_offsets[] = { 80 ICH9_CC_D25IR, 81 ICH9_CC_D26IR, 82 ICH9_CC_D27IR, 83 ICH9_CC_D28IR, 84 ICH9_CC_D29IR, 85 ICH9_CC_D30IR, 86 ICH9_CC_D31IR, 87 }; 88 const int *offset; 89 90 /* D{25 - 31}IR, but D30IR is read only to 0. */ 91 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 92 if (slot == 30) { 93 continue; 94 } 95 ich9_cc_update_ir(lpc->irr[slot], 96 pci_get_word(lpc->chip_config + *offset)); 97 } 98 99 /* 100 * D30: DMI2PCI bridge 101 * It is arbitrarily decided how INTx lines of PCI devices behind 102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 103 * INT[A-D] are connected to PIRQ[E-H] 104 */ 105 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 106 lpc->irr[30][pci_intx] = pci_intx + 4; 107 } 108 } 109 110 static void ich9_cc_init(ICH9LPCState *lpc) 111 { 112 int slot; 113 int intx; 114 115 /* the default irq routing is arbitrary as long as it matches with 116 * acpi irq routing table. 117 * The one that is incompatible with piix_pci(= bochs) one is 118 * intentionally chosen to let the users know that the different 119 * board is used. 120 * 121 * int[A-D] -> pirq[E-F] 122 * avoid pirq A-D because they are used for pci express port 123 */ 124 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 125 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 126 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 127 } 128 } 129 ich9_cc_update(lpc); 130 } 131 132 static void ich9_cc_reset(ICH9LPCState *lpc) 133 { 134 uint8_t *c = lpc->chip_config; 135 136 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 137 138 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 143 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 144 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 145 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 146 147 ich9_cc_update(lpc); 148 } 149 150 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 151 { 152 *addr &= ICH9_CC_ADDR_MASK; 153 if (*addr + *len >= ICH9_CC_SIZE) { 154 *len = ICH9_CC_SIZE - *addr; 155 } 156 } 157 158 /* val: little endian */ 159 static void ich9_cc_write(void *opaque, hwaddr addr, 160 uint64_t val, unsigned len) 161 { 162 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 163 164 ich9_cc_addr_len(&addr, &len); 165 memcpy(lpc->chip_config + addr, &val, len); 166 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 167 ich9_cc_update(lpc); 168 } 169 170 /* return value: little endian */ 171 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 172 unsigned len) 173 { 174 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 175 176 uint32_t val = 0; 177 ich9_cc_addr_len(&addr, &len); 178 memcpy(&val, lpc->chip_config + addr, len); 179 return val; 180 } 181 182 /* IRQ routing */ 183 /* */ 184 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 185 { 186 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 187 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 188 } 189 190 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 191 int *pic_irq, int *pic_dis) 192 { 193 switch (pirq_num) { 194 case 0 ... 3: /* A-D */ 195 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 196 pic_irq, pic_dis); 197 return; 198 case 4 ... 7: /* E-H */ 199 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 200 pic_irq, pic_dis); 201 return; 202 default: 203 break; 204 } 205 abort(); 206 } 207 208 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 209 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 210 { 211 int i, pic_level; 212 213 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 214 215 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 216 pic_level = 0; 217 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 218 int tmp_irq; 219 int tmp_dis; 220 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 221 if (!tmp_dis && tmp_irq == gsi) { 222 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); 223 } 224 } 225 if (gsi == lpc->sci_gsi) { 226 pic_level |= lpc->sci_level; 227 } 228 229 qemu_set_irq(lpc->gsi[gsi], pic_level); 230 } 231 232 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 233 static int ich9_pirq_to_gsi(int pirq) 234 { 235 return pirq + ICH9_LPC_PIC_NUM_PINS; 236 } 237 238 static int ich9_gsi_to_pirq(int gsi) 239 { 240 return gsi - ICH9_LPC_PIC_NUM_PINS; 241 } 242 243 /* gsi: ioapic irq 16-23, otherwise assert */ 244 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 245 { 246 int level = 0; 247 248 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 249 250 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); 251 if (gsi == lpc->sci_gsi) { 252 level |= lpc->sci_level; 253 } 254 255 qemu_set_irq(lpc->gsi[gsi], level); 256 } 257 258 void ich9_lpc_set_irq(void *opaque, int pirq, int level) 259 { 260 ICH9LPCState *lpc = opaque; 261 int pic_irq, pic_dis; 262 263 assert(0 <= pirq); 264 assert(pirq < ICH9_LPC_NB_PIRQS); 265 266 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 267 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 268 ich9_lpc_update_pic(lpc, pic_irq); 269 } 270 271 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 272 * a given device irq pin. 273 */ 274 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 275 { 276 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 277 PCIBus *pci_bus = PCI_BUS(bus); 278 PCIDevice *lpc_pdev = 279 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 280 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 281 282 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 283 } 284 285 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 286 { 287 ICH9LPCState *lpc = opaque; 288 PCIINTxRoute route; 289 int pic_irq; 290 int pic_dis; 291 292 assert(0 <= pirq_pin); 293 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 294 295 route.mode = PCI_INTX_ENABLED; 296 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 297 if (!pic_dis) { 298 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 299 route.irq = pic_irq; 300 } else { 301 route.mode = PCI_INTX_DISABLED; 302 route.irq = -1; 303 } 304 } else { 305 route.irq = ich9_pirq_to_gsi(pirq_pin); 306 } 307 308 return route; 309 } 310 311 void ich9_generate_smi(void) 312 { 313 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 314 } 315 316 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 317 { 318 switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & 319 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { 320 case ICH9_LPC_ACPI_CTRL_9: 321 return 9; 322 case ICH9_LPC_ACPI_CTRL_10: 323 return 10; 324 case ICH9_LPC_ACPI_CTRL_11: 325 return 11; 326 case ICH9_LPC_ACPI_CTRL_20: 327 return 20; 328 case ICH9_LPC_ACPI_CTRL_21: 329 return 21; 330 default: 331 /* reserved */ 332 break; 333 } 334 return -1; 335 } 336 337 static void ich9_set_sci(void *opaque, int irq_num, int level) 338 { 339 ICH9LPCState *lpc = opaque; 340 int irq; 341 342 assert(irq_num == 0); 343 level = !!level; 344 if (level == lpc->sci_level) { 345 return; 346 } 347 lpc->sci_level = level; 348 349 irq = lpc->sci_gsi; 350 if (irq < 0) { 351 return; 352 } 353 354 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 355 ich9_lpc_update_apic(lpc, irq); 356 } else { 357 ich9_lpc_update_pic(lpc, irq); 358 } 359 } 360 361 static void smi_features_ok_callback(void *opaque) 362 { 363 ICH9LPCState *lpc = opaque; 364 uint64_t guest_features; 365 366 if (lpc->smi_features_ok) { 367 /* negotiation already complete, features locked */ 368 return; 369 } 370 371 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 372 le64_to_cpus(&guest_features); 373 if (guest_features & ~lpc->smi_host_features) { 374 /* guest requests invalid features, leave @features_ok at zero */ 375 return; 376 } 377 378 /* valid feature subset requested, lock it down, report success */ 379 lpc->smi_negotiated_features = guest_features; 380 lpc->smi_features_ok = 1; 381 } 382 383 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) 384 { 385 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); 386 qemu_irq sci_irq; 387 FWCfgState *fw_cfg = fw_cfg_find(); 388 389 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 390 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); 391 392 if (lpc->smi_host_features && fw_cfg) { 393 uint64_t host_features_le; 394 395 host_features_le = cpu_to_le64(lpc->smi_host_features); 396 memcpy(lpc->smi_host_features_le, &host_features_le, 397 sizeof host_features_le); 398 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 399 lpc->smi_host_features_le, 400 sizeof lpc->smi_host_features_le); 401 402 /* The other two guest-visible fields are cleared on device reset, we 403 * just link them into fw_cfg here. 404 */ 405 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 406 NULL, NULL, NULL, 407 lpc->smi_guest_features_le, 408 sizeof lpc->smi_guest_features_le, 409 false); 410 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 411 smi_features_ok_callback, NULL, lpc, 412 &lpc->smi_features_ok, 413 sizeof lpc->smi_features_ok, 414 true); 415 } 416 417 ich9_lpc_reset(DEVICE(lpc)); 418 } 419 420 /* APM */ 421 422 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 423 { 424 ICH9LPCState *lpc = arg; 425 426 /* ACPI specs 3.0, 4.7.2.5 */ 427 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 428 val == ICH9_APM_ACPI_ENABLE, 429 val == ICH9_APM_ACPI_DISABLE); 430 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 431 return; 432 } 433 434 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 435 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 436 if (lpc->smi_negotiated_features & 437 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 438 CPUState *cs; 439 CPU_FOREACH(cs) { 440 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 441 } 442 } else { 443 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 444 } 445 } 446 } 447 448 /* config:PMBASE */ 449 static void 450 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 451 { 452 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 453 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 454 uint8_t new_gsi; 455 456 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 457 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 458 } else { 459 pm_io_base = 0; 460 } 461 462 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 463 464 new_gsi = ich9_lpc_sci_irq(lpc); 465 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 466 qemu_set_irq(lpc->pm.irq, 0); 467 lpc->sci_gsi = new_gsi; 468 qemu_set_irq(lpc->pm.irq, 1); 469 } 470 lpc->sci_gsi = new_gsi; 471 } 472 473 /* config:RCBA */ 474 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 475 { 476 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 477 478 if (rcba_old & ICH9_LPC_RCBA_EN) { 479 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 480 } 481 if (rcba & ICH9_LPC_RCBA_EN) { 482 memory_region_add_subregion_overlap(get_system_memory(), 483 rcba & ICH9_LPC_RCBA_BA_MASK, 484 &lpc->rcrb_mem, 1); 485 } 486 } 487 488 /* config:GEN_PMCON* */ 489 static void 490 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 491 { 492 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 493 uint16_t wmask; 494 495 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 496 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 497 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 498 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 499 lpc->pm.smi_en_wmask &= ~1; 500 } 501 } 502 503 static int ich9_lpc_post_load(void *opaque, int version_id) 504 { 505 ICH9LPCState *lpc = opaque; 506 507 ich9_lpc_pmbase_sci_update(lpc); 508 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 509 ich9_lpc_pmcon_update(lpc); 510 return 0; 511 } 512 513 static void ich9_lpc_config_write(PCIDevice *d, 514 uint32_t addr, uint32_t val, int len) 515 { 516 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 517 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 518 519 pci_default_write_config(d, addr, val, len); 520 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 521 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 522 ich9_lpc_pmbase_sci_update(lpc); 523 } 524 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 525 ich9_lpc_rcba_update(lpc, rcba_old); 526 } 527 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 528 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 529 } 530 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 531 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 532 } 533 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 534 ich9_lpc_pmcon_update(lpc); 535 } 536 } 537 538 static void ich9_lpc_reset(DeviceState *qdev) 539 { 540 PCIDevice *d = PCI_DEVICE(qdev); 541 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 542 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 543 int i; 544 545 for (i = 0; i < 4; i++) { 546 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 547 ICH9_LPC_PIRQ_ROUT_DEFAULT); 548 } 549 for (i = 0; i < 4; i++) { 550 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 551 ICH9_LPC_PIRQ_ROUT_DEFAULT); 552 } 553 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 554 555 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 556 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 557 558 ich9_cc_reset(lpc); 559 560 ich9_lpc_pmbase_sci_update(lpc); 561 ich9_lpc_rcba_update(lpc, rcba_old); 562 563 lpc->sci_level = 0; 564 lpc->rst_cnt = 0; 565 566 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 567 lpc->smi_features_ok = 0; 568 lpc->smi_negotiated_features = 0; 569 } 570 571 /* root complex register block is mapped into memory space */ 572 static const MemoryRegionOps rcrb_mmio_ops = { 573 .read = ich9_cc_read, 574 .write = ich9_cc_write, 575 .endianness = DEVICE_LITTLE_ENDIAN, 576 }; 577 578 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 579 { 580 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 581 MemoryRegion *io_as = pci_address_space_io(&s->d); 582 uint8_t *pci_conf; 583 584 pci_conf = s->d.config; 585 if (memory_region_present(io_as, 0x3f8)) { 586 /* com1 */ 587 pci_conf[0x82] |= 0x01; 588 } 589 if (memory_region_present(io_as, 0x2f8)) { 590 /* com2 */ 591 pci_conf[0x82] |= 0x02; 592 } 593 if (memory_region_present(io_as, 0x378)) { 594 /* lpt */ 595 pci_conf[0x82] |= 0x04; 596 } 597 if (memory_region_present(io_as, 0x3f2)) { 598 /* floppy */ 599 pci_conf[0x82] |= 0x08; 600 } 601 } 602 603 /* reset control */ 604 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 605 unsigned len) 606 { 607 ICH9LPCState *lpc = opaque; 608 609 if (val & 4) { 610 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 611 return; 612 } 613 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 614 } 615 616 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 617 { 618 ICH9LPCState *lpc = opaque; 619 620 return lpc->rst_cnt; 621 } 622 623 static const MemoryRegionOps ich9_rst_cnt_ops = { 624 .read = ich9_rst_cnt_read, 625 .write = ich9_rst_cnt_write, 626 .endianness = DEVICE_LITTLE_ENDIAN 627 }; 628 629 static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name, 630 void *opaque, Error **errp) 631 { 632 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 633 uint32_t value = lpc->sci_gsi; 634 635 visit_type_uint32(v, name, &value, errp); 636 } 637 638 static void ich9_lpc_add_properties(ICH9LPCState *lpc) 639 { 640 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 641 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 642 643 object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32", 644 ich9_lpc_get_sci_int, 645 NULL, NULL, NULL, NULL); 646 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 647 &acpi_enable_cmd, NULL); 648 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 649 &acpi_disable_cmd, NULL); 650 651 ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL); 652 } 653 654 static void ich9_lpc_initfn(Object *obj) 655 { 656 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 657 658 ich9_lpc_add_properties(lpc); 659 } 660 661 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 662 { 663 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 664 DeviceState *dev = DEVICE(d); 665 ISABus *isa_bus; 666 667 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 668 errp); 669 if (!isa_bus) { 670 return; 671 } 672 673 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 674 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 675 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 676 ICH9_LPC_ACPI_CTRL_ACPI_EN | 677 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 678 679 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 680 "lpc-rcrb-mmio", ICH9_CC_SIZE); 681 682 lpc->isa_bus = isa_bus; 683 684 ich9_cc_init(lpc); 685 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 686 687 lpc->machine_ready.notify = ich9_lpc_machine_ready; 688 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 689 690 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 691 "lpc-reset-control", 1); 692 memory_region_add_subregion_overlap(pci_address_space_io(d), 693 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 694 1); 695 696 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); 697 698 isa_bus_irqs(isa_bus, lpc->gsi); 699 } 700 701 static bool ich9_rst_cnt_needed(void *opaque) 702 { 703 ICH9LPCState *lpc = opaque; 704 705 return (lpc->rst_cnt != 0); 706 } 707 708 static const VMStateDescription vmstate_ich9_rst_cnt = { 709 .name = "ICH9LPC/rst_cnt", 710 .version_id = 1, 711 .minimum_version_id = 1, 712 .needed = ich9_rst_cnt_needed, 713 .fields = (VMStateField[]) { 714 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 715 VMSTATE_END_OF_LIST() 716 } 717 }; 718 719 static bool ich9_smi_feat_needed(void *opaque) 720 { 721 ICH9LPCState *lpc = opaque; 722 723 return !buffer_is_zero(lpc->smi_guest_features_le, 724 sizeof lpc->smi_guest_features_le) || 725 lpc->smi_features_ok; 726 } 727 728 static const VMStateDescription vmstate_ich9_smi_feat = { 729 .name = "ICH9LPC/smi_feat", 730 .version_id = 1, 731 .minimum_version_id = 1, 732 .needed = ich9_smi_feat_needed, 733 .fields = (VMStateField[]) { 734 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 735 sizeof(uint64_t)), 736 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 737 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 738 VMSTATE_END_OF_LIST() 739 } 740 }; 741 742 static const VMStateDescription vmstate_ich9_lpc = { 743 .name = "ICH9LPC", 744 .version_id = 1, 745 .minimum_version_id = 1, 746 .post_load = ich9_lpc_post_load, 747 .fields = (VMStateField[]) { 748 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 749 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 750 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 751 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 752 VMSTATE_UINT32(sci_level, ICH9LPCState), 753 VMSTATE_END_OF_LIST() 754 }, 755 .subsections = (const VMStateDescription*[]) { 756 &vmstate_ich9_rst_cnt, 757 &vmstate_ich9_smi_feat, 758 NULL 759 } 760 }; 761 762 static Property ich9_lpc_properties[] = { 763 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), 764 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 765 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 766 DEFINE_PROP_END_OF_LIST(), 767 }; 768 769 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 770 { 771 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 772 773 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 774 } 775 776 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 777 { 778 DeviceClass *dc = DEVICE_CLASS(klass); 779 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 780 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 781 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 782 783 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 784 dc->reset = ich9_lpc_reset; 785 k->realize = ich9_lpc_realize; 786 dc->vmsd = &vmstate_ich9_lpc; 787 dc->props = ich9_lpc_properties; 788 k->config_write = ich9_lpc_config_write; 789 dc->desc = "ICH9 LPC bridge"; 790 k->vendor_id = PCI_VENDOR_ID_INTEL; 791 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 792 k->revision = ICH9_A2_LPC_REVISION; 793 k->class_id = PCI_CLASS_BRIDGE_ISA; 794 /* 795 * Reason: part of ICH9 southbridge, needs to be wired up by 796 * pc_q35_init() 797 */ 798 dc->user_creatable = false; 799 hc->pre_plug = ich9_pm_device_pre_plug_cb; 800 hc->plug = ich9_pm_device_plug_cb; 801 hc->unplug_request = ich9_pm_device_unplug_request_cb; 802 hc->unplug = ich9_pm_device_unplug_cb; 803 adevc->ospm_status = ich9_pm_ospm_status; 804 adevc->send_event = ich9_send_gpe; 805 adevc->madt_cpu = pc_madt_cpu_entry; 806 } 807 808 static const TypeInfo ich9_lpc_info = { 809 .name = TYPE_ICH9_LPC_DEVICE, 810 .parent = TYPE_PCI_DEVICE, 811 .instance_size = sizeof(struct ICH9LPCState), 812 .instance_init = ich9_lpc_initfn, 813 .class_init = ich9_lpc_class_init, 814 .interfaces = (InterfaceInfo[]) { 815 { TYPE_HOTPLUG_HANDLER }, 816 { TYPE_ACPI_DEVICE_IF }, 817 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 818 { } 819 } 820 }; 821 822 static void ich9_lpc_register(void) 823 { 824 type_register_static(&ich9_lpc_info); 825 } 826 827 type_init(ich9_lpc_register); 828