1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "qemu-common.h" 32 #include "hw/hw.h" 33 #include "qapi/visitor.h" 34 #include "qemu/range.h" 35 #include "hw/isa/isa.h" 36 #include "hw/sysbus.h" 37 #include "hw/i386/pc.h" 38 #include "hw/isa/apm.h" 39 #include "hw/i386/ioapic.h" 40 #include "hw/pci/pci.h" 41 #include "hw/pci/pcie_host.h" 42 #include "hw/pci/pci_bridge.h" 43 #include "hw/i386/ich9.h" 44 #include "hw/acpi/acpi.h" 45 #include "hw/acpi/ich9.h" 46 #include "hw/pci/pci_bus.h" 47 #include "exec/address-spaces.h" 48 #include "sysemu/sysemu.h" 49 50 static int ich9_lpc_sci_irq(ICH9LPCState *lpc); 51 52 /*****************************************************************************/ 53 /* ICH9 LPC PCI to ISA bridge */ 54 55 static void ich9_lpc_reset(DeviceState *qdev); 56 57 /* chipset configuration register 58 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 59 * are used. 60 * Although it's not pci configuration space, it's little endian as Intel. 61 */ 62 63 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 64 { 65 int intx; 66 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 67 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 68 } 69 } 70 71 static void ich9_cc_update(ICH9LPCState *lpc) 72 { 73 int slot; 74 int pci_intx; 75 76 const int reg_offsets[] = { 77 ICH9_CC_D25IR, 78 ICH9_CC_D26IR, 79 ICH9_CC_D27IR, 80 ICH9_CC_D28IR, 81 ICH9_CC_D29IR, 82 ICH9_CC_D30IR, 83 ICH9_CC_D31IR, 84 }; 85 const int *offset; 86 87 /* D{25 - 31}IR, but D30IR is read only to 0. */ 88 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 89 if (slot == 30) { 90 continue; 91 } 92 ich9_cc_update_ir(lpc->irr[slot], 93 pci_get_word(lpc->chip_config + *offset)); 94 } 95 96 /* 97 * D30: DMI2PCI bridge 98 * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge 99 * are connected to pirq lines. Our choice is PIRQ[E-H]. 100 * INT[A-D] are connected to PIRQ[E-H] 101 */ 102 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 103 lpc->irr[30][pci_intx] = pci_intx + 4; 104 } 105 } 106 107 static void ich9_cc_init(ICH9LPCState *lpc) 108 { 109 int slot; 110 int intx; 111 112 /* the default irq routing is arbitrary as long as it matches with 113 * acpi irq routing table. 114 * The one that is incompatible with piix_pci(= bochs) one is 115 * intentionally chosen to let the users know that the different 116 * board is used. 117 * 118 * int[A-D] -> pirq[E-F] 119 * avoid pirq A-D because they are used for pci express port 120 */ 121 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 122 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 123 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 124 } 125 } 126 ich9_cc_update(lpc); 127 } 128 129 static void ich9_cc_reset(ICH9LPCState *lpc) 130 { 131 uint8_t *c = lpc->chip_config; 132 133 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 134 135 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 136 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 137 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 138 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 143 144 ich9_cc_update(lpc); 145 } 146 147 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 148 { 149 *addr &= ICH9_CC_ADDR_MASK; 150 if (*addr + *len >= ICH9_CC_SIZE) { 151 *len = ICH9_CC_SIZE - *addr; 152 } 153 } 154 155 /* val: little endian */ 156 static void ich9_cc_write(void *opaque, hwaddr addr, 157 uint64_t val, unsigned len) 158 { 159 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 160 161 ich9_cc_addr_len(&addr, &len); 162 memcpy(lpc->chip_config + addr, &val, len); 163 pci_bus_fire_intx_routing_notifier(lpc->d.bus); 164 ich9_cc_update(lpc); 165 } 166 167 /* return value: little endian */ 168 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 169 unsigned len) 170 { 171 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 172 173 uint32_t val = 0; 174 ich9_cc_addr_len(&addr, &len); 175 memcpy(&val, lpc->chip_config + addr, len); 176 return val; 177 } 178 179 /* IRQ routing */ 180 /* */ 181 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 182 { 183 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 184 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 185 } 186 187 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 188 int *pic_irq, int *pic_dis) 189 { 190 switch (pirq_num) { 191 case 0 ... 3: /* A-D */ 192 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 193 pic_irq, pic_dis); 194 return; 195 case 4 ... 7: /* E-H */ 196 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 197 pic_irq, pic_dis); 198 return; 199 default: 200 break; 201 } 202 abort(); 203 } 204 205 /* pic_irq: i8254 irq 0-15 */ 206 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int pic_irq) 207 { 208 int i, pic_level; 209 210 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 211 pic_level = 0; 212 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 213 int tmp_irq; 214 int tmp_dis; 215 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 216 if (!tmp_dis && pic_irq == tmp_irq) { 217 pic_level |= pci_bus_get_irq_level(lpc->d.bus, i); 218 } 219 } 220 if (pic_irq == ich9_lpc_sci_irq(lpc)) { 221 pic_level |= lpc->sci_level; 222 } 223 224 qemu_set_irq(lpc->pic[pic_irq], pic_level); 225 } 226 227 /* pirq: pirq[A-H] 0-7*/ 228 static void ich9_lpc_update_by_pirq(ICH9LPCState *lpc, int pirq) 229 { 230 int pic_irq; 231 int pic_dis; 232 233 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 234 assert(pic_irq < ICH9_LPC_PIC_NUM_PINS); 235 if (pic_dis) { 236 return; 237 } 238 239 ich9_lpc_update_pic(lpc, pic_irq); 240 } 241 242 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 243 static int ich9_pirq_to_gsi(int pirq) 244 { 245 return pirq + ICH9_LPC_PIC_NUM_PINS; 246 } 247 248 static int ich9_gsi_to_pirq(int gsi) 249 { 250 return gsi - ICH9_LPC_PIC_NUM_PINS; 251 } 252 253 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 254 { 255 int level = 0; 256 257 if (gsi >= ICH9_LPC_PIC_NUM_PINS) { 258 level |= pci_bus_get_irq_level(lpc->d.bus, ich9_gsi_to_pirq(gsi)); 259 } 260 if (gsi == ich9_lpc_sci_irq(lpc)) { 261 level |= lpc->sci_level; 262 } 263 264 qemu_set_irq(lpc->ioapic[gsi], level); 265 } 266 267 void ich9_lpc_set_irq(void *opaque, int pirq, int level) 268 { 269 ICH9LPCState *lpc = opaque; 270 271 assert(0 <= pirq); 272 assert(pirq < ICH9_LPC_NB_PIRQS); 273 274 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 275 ich9_lpc_update_by_pirq(lpc, pirq); 276 } 277 278 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 279 * a given device irq pin. 280 */ 281 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 282 { 283 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 284 PCIBus *pci_bus = PCI_BUS(bus); 285 PCIDevice *lpc_pdev = 286 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 287 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 288 289 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 290 } 291 292 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 293 { 294 ICH9LPCState *lpc = opaque; 295 PCIINTxRoute route; 296 int pic_irq; 297 int pic_dis; 298 299 assert(0 <= pirq_pin); 300 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 301 302 route.mode = PCI_INTX_ENABLED; 303 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 304 if (!pic_dis) { 305 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 306 route.irq = pic_irq; 307 } else { 308 route.mode = PCI_INTX_DISABLED; 309 route.irq = -1; 310 } 311 } else { 312 route.irq = ich9_pirq_to_gsi(pirq_pin); 313 } 314 315 return route; 316 } 317 318 void ich9_generate_smi(void) 319 { 320 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 321 } 322 323 void ich9_generate_nmi(void) 324 { 325 cpu_interrupt(first_cpu, CPU_INTERRUPT_NMI); 326 } 327 328 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 329 { 330 switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & 331 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { 332 case ICH9_LPC_ACPI_CTRL_9: 333 return 9; 334 case ICH9_LPC_ACPI_CTRL_10: 335 return 10; 336 case ICH9_LPC_ACPI_CTRL_11: 337 return 11; 338 case ICH9_LPC_ACPI_CTRL_20: 339 return 20; 340 case ICH9_LPC_ACPI_CTRL_21: 341 return 21; 342 default: 343 /* reserved */ 344 break; 345 } 346 return -1; 347 } 348 349 static void ich9_set_sci(void *opaque, int irq_num, int level) 350 { 351 ICH9LPCState *lpc = opaque; 352 int irq; 353 354 assert(irq_num == 0); 355 level = !!level; 356 if (level == lpc->sci_level) { 357 return; 358 } 359 lpc->sci_level = level; 360 361 irq = ich9_lpc_sci_irq(lpc); 362 if (irq < 0) { 363 return; 364 } 365 366 ich9_lpc_update_apic(lpc, irq); 367 if (irq < ICH9_LPC_PIC_NUM_PINS) { 368 ich9_lpc_update_pic(lpc, irq); 369 } 370 } 371 372 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled, bool enable_tco) 373 { 374 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); 375 qemu_irq sci_irq; 376 377 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 378 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, enable_tco, sci_irq); 379 ich9_lpc_reset(&lpc->d.qdev); 380 } 381 382 /* APM */ 383 384 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 385 { 386 ICH9LPCState *lpc = arg; 387 388 /* ACPI specs 3.0, 4.7.2.5 */ 389 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 390 val == ICH9_APM_ACPI_ENABLE, 391 val == ICH9_APM_ACPI_DISABLE); 392 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 393 return; 394 } 395 396 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 397 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 398 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 399 } 400 } 401 402 /* config:PMBASE */ 403 static void 404 ich9_lpc_pmbase_update(ICH9LPCState *lpc) 405 { 406 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 407 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 408 409 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 410 } 411 412 /* config:RBCA */ 413 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rbca_old) 414 { 415 uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 416 417 if (rbca_old & ICH9_LPC_RCBA_EN) { 418 memory_region_del_subregion(get_system_memory(), &lpc->rbca_mem); 419 } 420 if (rbca & ICH9_LPC_RCBA_EN) { 421 memory_region_add_subregion_overlap(get_system_memory(), 422 rbca & ICH9_LPC_RCBA_BA_MASK, 423 &lpc->rbca_mem, 1); 424 } 425 } 426 427 /* config:GEN_PMCON* */ 428 static void 429 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 430 { 431 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 432 uint16_t wmask; 433 434 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 435 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 436 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 437 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 438 lpc->pm.smi_en_wmask &= ~1; 439 } 440 } 441 442 static int ich9_lpc_post_load(void *opaque, int version_id) 443 { 444 ICH9LPCState *lpc = opaque; 445 446 ich9_lpc_pmbase_update(lpc); 447 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */); 448 ich9_lpc_pmcon_update(lpc); 449 return 0; 450 } 451 452 static void ich9_lpc_config_write(PCIDevice *d, 453 uint32_t addr, uint32_t val, int len) 454 { 455 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 456 uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA); 457 458 pci_default_write_config(d, addr, val, len); 459 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) { 460 ich9_lpc_pmbase_update(lpc); 461 } 462 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 463 ich9_lpc_rcba_update(lpc, rbca_old); 464 } 465 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 466 pci_bus_fire_intx_routing_notifier(lpc->d.bus); 467 } 468 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 469 pci_bus_fire_intx_routing_notifier(lpc->d.bus); 470 } 471 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 472 ich9_lpc_pmcon_update(lpc); 473 } 474 } 475 476 static void ich9_lpc_reset(DeviceState *qdev) 477 { 478 PCIDevice *d = PCI_DEVICE(qdev); 479 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 480 uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA); 481 int i; 482 483 for (i = 0; i < 4; i++) { 484 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 485 ICH9_LPC_PIRQ_ROUT_DEFAULT); 486 } 487 for (i = 0; i < 4; i++) { 488 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 489 ICH9_LPC_PIRQ_ROUT_DEFAULT); 490 } 491 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 492 493 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 494 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 495 496 ich9_cc_reset(lpc); 497 498 ich9_lpc_pmbase_update(lpc); 499 ich9_lpc_rcba_update(lpc, rbca_old); 500 501 lpc->sci_level = 0; 502 lpc->rst_cnt = 0; 503 } 504 505 static const MemoryRegionOps rbca_mmio_ops = { 506 .read = ich9_cc_read, 507 .write = ich9_cc_write, 508 .endianness = DEVICE_LITTLE_ENDIAN, 509 }; 510 511 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 512 { 513 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 514 MemoryRegion *io_as = pci_address_space_io(&s->d); 515 uint8_t *pci_conf; 516 517 pci_conf = s->d.config; 518 if (memory_region_present(io_as, 0x3f8)) { 519 /* com1 */ 520 pci_conf[0x82] |= 0x01; 521 } 522 if (memory_region_present(io_as, 0x2f8)) { 523 /* com2 */ 524 pci_conf[0x82] |= 0x02; 525 } 526 if (memory_region_present(io_as, 0x378)) { 527 /* lpt */ 528 pci_conf[0x82] |= 0x04; 529 } 530 if (memory_region_present(io_as, 0x3f2)) { 531 /* floppy */ 532 pci_conf[0x82] |= 0x08; 533 } 534 } 535 536 /* reset control */ 537 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 538 unsigned len) 539 { 540 ICH9LPCState *lpc = opaque; 541 542 if (val & 4) { 543 qemu_system_reset_request(); 544 return; 545 } 546 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 547 } 548 549 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 550 { 551 ICH9LPCState *lpc = opaque; 552 553 return lpc->rst_cnt; 554 } 555 556 static const MemoryRegionOps ich9_rst_cnt_ops = { 557 .read = ich9_rst_cnt_read, 558 .write = ich9_rst_cnt_write, 559 .endianness = DEVICE_LITTLE_ENDIAN 560 }; 561 562 Object *ich9_lpc_find(void) 563 { 564 bool ambig; 565 Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig); 566 567 if (ambig) { 568 return NULL; 569 } 570 return o; 571 } 572 573 static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name, 574 void *opaque, Error **errp) 575 { 576 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 577 uint32_t value = ich9_lpc_sci_irq(lpc); 578 579 visit_type_uint32(v, name, &value, errp); 580 } 581 582 static void ich9_lpc_add_properties(ICH9LPCState *lpc) 583 { 584 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 585 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 586 587 object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32", 588 ich9_lpc_get_sci_int, 589 NULL, NULL, NULL, NULL); 590 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 591 &acpi_enable_cmd, NULL); 592 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 593 &acpi_disable_cmd, NULL); 594 595 ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL); 596 } 597 598 static void ich9_lpc_initfn(Object *obj) 599 { 600 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 601 602 ich9_lpc_add_properties(lpc); 603 } 604 605 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 606 { 607 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 608 ISABus *isa_bus; 609 610 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 611 errp); 612 if (!isa_bus) { 613 return; 614 } 615 616 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 617 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 618 619 memory_region_init_io(&lpc->rbca_mem, OBJECT(d), &rbca_mmio_ops, lpc, 620 "lpc-rbca-mmio", ICH9_CC_SIZE); 621 622 lpc->isa_bus = isa_bus; 623 624 ich9_cc_init(lpc); 625 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 626 627 lpc->machine_ready.notify = ich9_lpc_machine_ready; 628 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 629 630 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 631 "lpc-reset-control", 1); 632 memory_region_add_subregion_overlap(pci_address_space_io(d), 633 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 634 1); 635 } 636 637 static void ich9_device_plug_cb(HotplugHandler *hotplug_dev, 638 DeviceState *dev, Error **errp) 639 { 640 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); 641 642 ich9_pm_device_plug_cb(&lpc->pm, dev, errp); 643 } 644 645 static void ich9_device_unplug_request_cb(HotplugHandler *hotplug_dev, 646 DeviceState *dev, Error **errp) 647 { 648 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); 649 650 ich9_pm_device_unplug_request_cb(&lpc->pm, dev, errp); 651 } 652 653 static void ich9_device_unplug_cb(HotplugHandler *hotplug_dev, 654 DeviceState *dev, Error **errp) 655 { 656 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); 657 658 ich9_pm_device_unplug_cb(&lpc->pm, dev, errp); 659 } 660 661 static bool ich9_rst_cnt_needed(void *opaque) 662 { 663 ICH9LPCState *lpc = opaque; 664 665 return (lpc->rst_cnt != 0); 666 } 667 668 static const VMStateDescription vmstate_ich9_rst_cnt = { 669 .name = "ICH9LPC/rst_cnt", 670 .version_id = 1, 671 .minimum_version_id = 1, 672 .needed = ich9_rst_cnt_needed, 673 .fields = (VMStateField[]) { 674 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 675 VMSTATE_END_OF_LIST() 676 } 677 }; 678 679 static const VMStateDescription vmstate_ich9_lpc = { 680 .name = "ICH9LPC", 681 .version_id = 1, 682 .minimum_version_id = 1, 683 .post_load = ich9_lpc_post_load, 684 .fields = (VMStateField[]) { 685 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 686 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 687 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 688 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 689 VMSTATE_UINT32(sci_level, ICH9LPCState), 690 VMSTATE_END_OF_LIST() 691 }, 692 .subsections = (const VMStateDescription*[]) { 693 &vmstate_ich9_rst_cnt, 694 NULL 695 } 696 }; 697 698 static Property ich9_lpc_properties[] = { 699 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), 700 DEFINE_PROP_END_OF_LIST(), 701 }; 702 703 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 704 { 705 DeviceClass *dc = DEVICE_CLASS(klass); 706 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 707 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 708 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 709 710 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 711 dc->reset = ich9_lpc_reset; 712 k->realize = ich9_lpc_realize; 713 dc->vmsd = &vmstate_ich9_lpc; 714 dc->props = ich9_lpc_properties; 715 k->config_write = ich9_lpc_config_write; 716 dc->desc = "ICH9 LPC bridge"; 717 k->vendor_id = PCI_VENDOR_ID_INTEL; 718 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 719 k->revision = ICH9_A2_LPC_REVISION; 720 k->class_id = PCI_CLASS_BRIDGE_ISA; 721 /* 722 * Reason: part of ICH9 southbridge, needs to be wired up by 723 * pc_q35_init() 724 */ 725 dc->cannot_instantiate_with_device_add_yet = true; 726 hc->plug = ich9_device_plug_cb; 727 hc->unplug_request = ich9_device_unplug_request_cb; 728 hc->unplug = ich9_device_unplug_cb; 729 adevc->ospm_status = ich9_pm_ospm_status; 730 } 731 732 static const TypeInfo ich9_lpc_info = { 733 .name = TYPE_ICH9_LPC_DEVICE, 734 .parent = TYPE_PCI_DEVICE, 735 .instance_size = sizeof(struct ICH9LPCState), 736 .instance_init = ich9_lpc_initfn, 737 .class_init = ich9_lpc_class_init, 738 .interfaces = (InterfaceInfo[]) { 739 { TYPE_HOTPLUG_HANDLER }, 740 { TYPE_ACPI_DEVICE_IF }, 741 { } 742 } 743 }; 744 745 static void ich9_lpc_register(void) 746 { 747 type_register_static(&ich9_lpc_info); 748 } 749 750 type_init(ich9_lpc_register); 751