1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "cpu.h" 14 #include "exec/hwaddr.h" 15 #include "exec/address-spaces.h" 16 #include "sysemu/sysemu.h" 17 #include "sysemu/qtest.h" 18 #include "hw/irq.h" 19 #include "hw/m68k/next-cube.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "hw/scsi/esp.h" 23 #include "hw/sysbus.h" 24 #include "qom/object.h" 25 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 26 #include "hw/block/fdc.h" 27 #include "hw/qdev-properties.h" 28 #include "qapi/error.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 32 /* #define DEBUG_NEXT */ 33 #ifdef DEBUG_NEXT 34 #define DPRINTF(fmt, ...) \ 35 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 36 #else 37 #define DPRINTF(fmt, ...) do { } while (0) 38 #endif 39 40 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 41 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 42 43 #define ENTRY 0x0100001e 44 #define RAM_SIZE 0x4000000 45 #define ROM_FILE "Rev_2.5_v66.bin" 46 47 typedef struct next_dma { 48 uint32_t csr; 49 50 uint32_t saved_next; 51 uint32_t saved_limit; 52 uint32_t saved_start; 53 uint32_t saved_stop; 54 55 uint32_t next; 56 uint32_t limit; 57 uint32_t start; 58 uint32_t stop; 59 60 uint32_t next_initbuf; 61 uint32_t size; 62 } next_dma; 63 64 typedef struct NextRtc { 65 uint8_t ram[32]; 66 uint8_t command; 67 uint8_t value; 68 uint8_t status; 69 uint8_t control; 70 uint8_t retval; 71 } NextRtc; 72 73 struct NeXTState { 74 MachineState parent; 75 76 uint32_t int_mask; 77 uint32_t int_status; 78 79 next_dma dma[10]; 80 qemu_irq *scsi_irq; 81 qemu_irq scsi_dma; 82 qemu_irq scsi_reset; 83 qemu_irq *fd_irq; 84 85 NextRtc rtc; 86 }; 87 88 #define TYPE_NEXT_PC "next-pc" 89 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 90 91 /* NeXT Peripheral Controller */ 92 struct NeXTPC { 93 SysBusDevice parent_obj; 94 95 /* Temporary until all functionality has been moved into this device */ 96 NeXTState *ns; 97 98 MemoryRegion mmiomem; 99 MemoryRegion scrmem; 100 101 uint32_t scr1; 102 uint32_t scr2; 103 uint8_t scsi_csr_1; 104 uint8_t scsi_csr_2; 105 }; 106 107 /* Thanks to NeXT forums for this */ 108 /* 109 static const uint8_t rtc_ram3[32] = { 110 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 111 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 112 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 113 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 114 }; 115 */ 116 static const uint8_t rtc_ram2[32] = { 117 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 118 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 119 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 120 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 121 }; 122 123 #define SCR2_RTCLK 0x2 124 #define SCR2_RTDATA 0x4 125 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 126 127 static void nextscr2_write(NeXTPC *s, uint32_t val, int size) 128 { 129 static int led; 130 static int phase; 131 static uint8_t old_scr2; 132 uint8_t scr2_2; 133 NextRtc *rtc = &s->ns->rtc; 134 135 if (size == 4) { 136 scr2_2 = (val >> 8) & 0xFF; 137 } else { 138 scr2_2 = val & 0xFF; 139 } 140 141 if (val & 0x1) { 142 DPRINTF("fault!\n"); 143 led++; 144 if (led == 10) { 145 DPRINTF("LED flashing, possible fault!\n"); 146 led = 0; 147 } 148 } 149 150 if (scr2_2 & 0x1) { 151 /* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */ 152 if (phase == -1) { 153 phase = 0; 154 } 155 /* If we are in going down clock... do something */ 156 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 157 ((scr2_2 & SCR2_RTCLK) == 0)) { 158 if (phase < 8) { 159 rtc->command = (rtc->command << 1) | 160 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 161 } 162 if (phase >= 8 && phase < 16) { 163 rtc->value = (rtc->value << 1) | 164 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 165 166 /* if we read RAM register, output RT_DATA bit */ 167 if (rtc->command <= 0x1F) { 168 scr2_2 = scr2_2 & (~SCR2_RTDATA); 169 if (rtc->ram[rtc->command] & (0x80 >> (phase - 8))) { 170 scr2_2 |= SCR2_RTDATA; 171 } 172 173 rtc->retval = (rtc->retval << 1) | 174 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 175 } 176 /* read the status 0x30 */ 177 if (rtc->command == 0x30) { 178 scr2_2 = scr2_2 & (~SCR2_RTDATA); 179 /* for now status = 0x98 (new rtc + FTU) */ 180 if (rtc->status & (0x80 >> (phase - 8))) { 181 scr2_2 |= SCR2_RTDATA; 182 } 183 184 rtc->retval = (rtc->retval << 1) | 185 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 186 } 187 /* read the status 0x31 */ 188 if (rtc->command == 0x31) { 189 scr2_2 = scr2_2 & (~SCR2_RTDATA); 190 if (rtc->control & (0x80 >> (phase - 8))) { 191 scr2_2 |= SCR2_RTDATA; 192 } 193 rtc->retval = (rtc->retval << 1) | 194 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 195 } 196 197 if ((rtc->command >= 0x20) && (rtc->command <= 0x2F)) { 198 scr2_2 = scr2_2 & (~SCR2_RTDATA); 199 /* for now 0x00 */ 200 time_t time_h = time(NULL); 201 struct tm *info = localtime(&time_h); 202 int ret = 0; 203 204 switch (rtc->command) { 205 case 0x20: 206 ret = SCR2_TOBCD(info->tm_sec); 207 break; 208 case 0x21: 209 ret = SCR2_TOBCD(info->tm_min); 210 break; 211 case 0x22: 212 ret = SCR2_TOBCD(info->tm_hour); 213 break; 214 case 0x24: 215 ret = SCR2_TOBCD(info->tm_mday); 216 break; 217 case 0x25: 218 ret = SCR2_TOBCD((info->tm_mon + 1)); 219 break; 220 case 0x26: 221 ret = SCR2_TOBCD((info->tm_year - 100)); 222 break; 223 224 } 225 226 if (ret & (0x80 >> (phase - 8))) { 227 scr2_2 |= SCR2_RTDATA; 228 } 229 rtc->retval = (rtc->retval << 1) | 230 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 231 } 232 233 } 234 235 phase++; 236 if (phase == 16) { 237 if (rtc->command >= 0x80 && rtc->command <= 0x9F) { 238 rtc->ram[rtc->command - 0x80] = rtc->value; 239 } 240 /* write to x30 register */ 241 if (rtc->command == 0xB1) { 242 /* clear FTU */ 243 if (rtc->value & 0x04) { 244 rtc->status = rtc->status & (~0x18); 245 s->ns->int_status = s->ns->int_status & (~0x04); 246 } 247 } 248 } 249 } 250 } else { 251 /* else end or abort */ 252 phase = -1; 253 rtc->command = 0; 254 rtc->value = 0; 255 } 256 s->scr2 = val & 0xFFFF00FF; 257 s->scr2 |= scr2_2 << 8; 258 old_scr2 = scr2_2; 259 } 260 261 static uint32_t mmio_readb(NeXTPC *s, hwaddr addr) 262 { 263 switch (addr) { 264 case 0xc000: 265 return (s->scr1 >> 24) & 0xFF; 266 case 0xc001: 267 return (s->scr1 >> 16) & 0xFF; 268 case 0xc002: 269 return (s->scr1 >> 8) & 0xFF; 270 case 0xc003: 271 return (s->scr1 >> 0) & 0xFF; 272 273 case 0xd000: 274 return (s->scr2 >> 24) & 0xFF; 275 case 0xd001: 276 return (s->scr2 >> 16) & 0xFF; 277 case 0xd002: 278 return (s->scr2 >> 8) & 0xFF; 279 case 0xd003: 280 return (s->scr2 >> 0) & 0xFF; 281 case 0x14020: 282 DPRINTF("MMIO Read 0x4020\n"); 283 return 0x7f; 284 285 default: 286 DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr); 287 return 0x0; 288 } 289 } 290 291 static uint32_t mmio_readw(NeXTPC *s, hwaddr addr) 292 { 293 switch (addr) { 294 default: 295 DPRINTF("MMIO Read W @ %"HWADDR_PRIx"\n", addr); 296 return 0x0; 297 } 298 } 299 300 static uint32_t mmio_readl(NeXTPC *s, hwaddr addr) 301 { 302 switch (addr) { 303 case 0x7000: 304 /* DPRINTF("Read INT status: %x\n", s->ns->int_status); */ 305 return s->ns->int_status; 306 307 case 0x7800: 308 DPRINTF("MMIO Read INT mask: %x\n", s->ns->int_mask); 309 return s->ns->int_mask; 310 311 case 0xc000: 312 return s->scr1; 313 314 case 0xd000: 315 return s->scr2; 316 317 default: 318 DPRINTF("MMIO Read L @ %"HWADDR_PRIx"\n", addr); 319 return 0x0; 320 } 321 } 322 323 static void mmio_writeb(NeXTPC *s, hwaddr addr, uint32_t val) 324 { 325 switch (addr) { 326 case 0xd003: 327 nextscr2_write(s, val, 1); 328 break; 329 default: 330 DPRINTF("MMIO Write B @ %x with %x\n", (unsigned int)addr, val); 331 } 332 333 } 334 335 static void mmio_writew(NeXTPC *s, hwaddr addr, uint32_t val) 336 { 337 DPRINTF("MMIO Write W\n"); 338 } 339 340 static void mmio_writel(NeXTPC *s, hwaddr addr, uint32_t val) 341 { 342 switch (addr) { 343 case 0x7000: 344 DPRINTF("INT Status old: %x new: %x\n", s->ns->int_status, val); 345 s->ns->int_status = val; 346 break; 347 case 0x7800: 348 DPRINTF("INT Mask old: %x new: %x\n", s->ns->int_mask, val); 349 s->ns->int_mask = val; 350 break; 351 case 0xc000: 352 DPRINTF("SCR1 Write: %x\n", val); 353 break; 354 case 0xd000: 355 nextscr2_write(s, val, 4); 356 break; 357 358 default: 359 DPRINTF("MMIO Write l @ %x with %x\n", (unsigned int)addr, val); 360 } 361 } 362 363 static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size) 364 { 365 NeXTPC *s = NEXT_PC(opaque); 366 367 switch (size) { 368 case 1: 369 return mmio_readb(s, addr); 370 case 2: 371 return mmio_readw(s, addr); 372 case 4: 373 return mmio_readl(s, addr); 374 default: 375 g_assert_not_reached(); 376 } 377 } 378 379 static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value, 380 unsigned size) 381 { 382 NeXTPC *s = NEXT_PC(opaque); 383 384 switch (size) { 385 case 1: 386 mmio_writeb(s, addr, value); 387 break; 388 case 2: 389 mmio_writew(s, addr, value); 390 break; 391 case 4: 392 mmio_writel(s, addr, value); 393 break; 394 default: 395 g_assert_not_reached(); 396 } 397 } 398 399 static const MemoryRegionOps mmio_ops = { 400 .read = mmio_readfn, 401 .write = mmio_writefn, 402 .valid.min_access_size = 1, 403 .valid.max_access_size = 4, 404 .endianness = DEVICE_NATIVE_ENDIAN, 405 }; 406 407 static uint32_t scr_readb(NeXTPC *s, hwaddr addr) 408 { 409 switch (addr) { 410 case 0x14108: 411 DPRINTF("FD read @ %x\n", (unsigned int)addr); 412 return 0x40 | 0x04 | 0x2 | 0x1; 413 case 0x14020: 414 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 415 return s->scsi_csr_1; 416 417 case 0x14021: 418 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 419 return 0x40; 420 421 /* 422 * These 4 registers are the hardware timer, not sure which register 423 * is the latch instead of data, but no problems so far 424 */ 425 case 0x1a000: 426 return 0xff & (clock() >> 24); 427 case 0x1a001: 428 return 0xff & (clock() >> 16); 429 case 0x1a002: 430 return 0xff & (clock() >> 8); 431 case 0x1a003: 432 /* Hack: We need to have this change consistently to make it work */ 433 return 0xFF & clock(); 434 435 default: 436 DPRINTF("BMAP Read B @ %x\n", (unsigned int)addr); 437 return 0; 438 } 439 } 440 441 static uint32_t scr_readw(NeXTPC *s, hwaddr addr) 442 { 443 DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr); 444 return 0; 445 } 446 447 static uint32_t scr_readl(NeXTPC *s, hwaddr addr) 448 { 449 DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr); 450 return 0; 451 } 452 453 #define SCSICSR_ENABLE 0x01 454 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 455 #define SCSICSR_FIFOFL 0x04 456 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 457 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 458 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 459 460 static void scr_writeb(NeXTPC *s, hwaddr addr, uint32_t value) 461 { 462 switch (addr) { 463 case 0x14108: 464 DPRINTF("FDCSR Write: %x\n", value); 465 466 if (value == 0x0) { 467 /* qemu_irq_raise(s->fd_irq[0]); */ 468 } 469 break; 470 case 0x14020: /* SCSI Control Register */ 471 if (value & SCSICSR_FIFOFL) { 472 DPRINTF("SCSICSR FIFO Flush\n"); 473 /* will have to add another irq to the esp if this is needed */ 474 /* esp_puflush_fifo(esp_g); */ 475 /* qemu_irq_pulse(s->scsi_dma); */ 476 } 477 478 if (value & SCSICSR_ENABLE) { 479 DPRINTF("SCSICSR Enable\n"); 480 /* 481 * qemu_irq_raise(s->scsi_dma); 482 * s->scsi_csr_1 = 0xc0; 483 * s->scsi_csr_1 |= 0x1; 484 * qemu_irq_pulse(s->scsi_dma); 485 */ 486 } 487 /* 488 * else 489 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 490 */ 491 492 if (value & SCSICSR_RESET) { 493 DPRINTF("SCSICSR Reset\n"); 494 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 495 /* qemu_irq_raise(s->scsi_reset); */ 496 /* s->scsi_csr_1 &= ~(SCSICSR_INTMASK |0x80|0x1); */ 497 498 } 499 if (value & SCSICSR_DMADIR) { 500 DPRINTF("SCSICSR DMAdir\n"); 501 } 502 if (value & SCSICSR_CPUDMA) { 503 DPRINTF("SCSICSR CPUDMA\n"); 504 /* qemu_irq_raise(s->scsi_dma); */ 505 506 s->ns->int_status |= 0x4000000; 507 } else { 508 s->ns->int_status &= ~(0x4000000); 509 } 510 if (value & SCSICSR_INTMASK) { 511 DPRINTF("SCSICSR INTMASK\n"); 512 /* 513 * int_mask &= ~0x1000; 514 * s->scsi_csr_1 |= value; 515 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 516 * if (s->scsi_queued) { 517 * s->scsi_queued = 0; 518 * next_irq(s, NEXT_SCSI_I, level); 519 * } 520 */ 521 } else { 522 /* int_mask |= 0x1000; */ 523 } 524 if (value & 0x80) { 525 /* int_mask |= 0x1000; */ 526 /* s->scsi_csr_1 |= 0x80; */ 527 } 528 DPRINTF("SCSICSR Write: %x\n", value); 529 /* s->scsi_csr_1 = value; */ 530 return; 531 /* Hardware timer latch - not implemented yet */ 532 case 0x1a000: 533 default: 534 DPRINTF("BMAP Write B @ %x with %x\n", (unsigned int)addr, value); 535 } 536 } 537 538 static void scr_writew(NeXTPC *s, hwaddr addr, uint32_t value) 539 { 540 DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value); 541 } 542 543 static void scr_writel(NeXTPC *s, hwaddr addr, uint32_t value) 544 { 545 DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value); 546 } 547 548 static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size) 549 { 550 NeXTPC *s = NEXT_PC(opaque); 551 552 switch (size) { 553 case 1: 554 return scr_readb(s, addr); 555 case 2: 556 return scr_readw(s, addr); 557 case 4: 558 return scr_readl(s, addr); 559 default: 560 g_assert_not_reached(); 561 } 562 } 563 564 static void scr_writefn(void *opaque, hwaddr addr, uint64_t value, 565 unsigned size) 566 { 567 NeXTPC *s = NEXT_PC(opaque); 568 569 switch (size) { 570 case 1: 571 scr_writeb(s, addr, value); 572 break; 573 case 2: 574 scr_writew(s, addr, value); 575 break; 576 case 4: 577 scr_writel(s, addr, value); 578 break; 579 default: 580 g_assert_not_reached(); 581 } 582 } 583 584 static const MemoryRegionOps scr_ops = { 585 .read = scr_readfn, 586 .write = scr_writefn, 587 .valid.min_access_size = 1, 588 .valid.max_access_size = 4, 589 .endianness = DEVICE_NATIVE_ENDIAN, 590 }; 591 592 #define NEXTDMA_SCSI(x) (0x10 + x) 593 #define NEXTDMA_FD(x) (0x10 + x) 594 #define NEXTDMA_ENTX(x) (0x110 + x) 595 #define NEXTDMA_ENRX(x) (0x150 + x) 596 #define NEXTDMA_CSR 0x0 597 #define NEXTDMA_NEXT 0x4000 598 #define NEXTDMA_LIMIT 0x4004 599 #define NEXTDMA_START 0x4008 600 #define NEXTDMA_STOP 0x400c 601 #define NEXTDMA_NEXT_INIT 0x4200 602 #define NEXTDMA_SIZE 0x4204 603 604 static void dma_writel(void *opaque, hwaddr addr, uint64_t value, 605 unsigned int size) 606 { 607 NeXTState *next_state = NEXT_MACHINE(opaque); 608 609 switch (addr) { 610 case NEXTDMA_ENRX(NEXTDMA_CSR): 611 if (value & DMA_DEV2M) { 612 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 613 } 614 615 if (value & DMA_SETENABLE) { 616 /* DPRINTF("SCSI DMA ENABLE\n"); */ 617 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 618 } 619 if (value & DMA_SETSUPDATE) { 620 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 621 } 622 if (value & DMA_CLRCOMPLETE) { 623 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 624 } 625 626 if (value & DMA_RESET) { 627 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 628 DMA_ENABLE | DMA_DEV2M); 629 } 630 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 631 break; 632 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 633 next_state->dma[NEXTDMA_ENRX].next_initbuf = value; 634 break; 635 case NEXTDMA_ENRX(NEXTDMA_NEXT): 636 next_state->dma[NEXTDMA_ENRX].next = value; 637 break; 638 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 639 next_state->dma[NEXTDMA_ENRX].limit = value; 640 break; 641 case NEXTDMA_SCSI(NEXTDMA_CSR): 642 if (value & DMA_DEV2M) { 643 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 644 } 645 if (value & DMA_SETENABLE) { 646 /* DPRINTF("SCSI DMA ENABLE\n"); */ 647 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 648 } 649 if (value & DMA_SETSUPDATE) { 650 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 651 } 652 if (value & DMA_CLRCOMPLETE) { 653 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 654 } 655 656 if (value & DMA_RESET) { 657 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 658 DMA_ENABLE | DMA_DEV2M); 659 /* DPRINTF("SCSI DMA RESET\n"); */ 660 } 661 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 662 break; 663 664 case NEXTDMA_SCSI(NEXTDMA_NEXT): 665 next_state->dma[NEXTDMA_SCSI].next = value; 666 break; 667 668 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 669 next_state->dma[NEXTDMA_SCSI].limit = value; 670 break; 671 672 case NEXTDMA_SCSI(NEXTDMA_START): 673 next_state->dma[NEXTDMA_SCSI].start = value; 674 break; 675 676 case NEXTDMA_SCSI(NEXTDMA_STOP): 677 next_state->dma[NEXTDMA_SCSI].stop = value; 678 break; 679 680 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 681 next_state->dma[NEXTDMA_SCSI].next_initbuf = value; 682 break; 683 684 default: 685 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)value); 686 } 687 } 688 689 static uint64_t dma_readl(void *opaque, hwaddr addr, unsigned int size) 690 { 691 NeXTState *next_state = NEXT_MACHINE(opaque); 692 693 switch (addr) { 694 case NEXTDMA_SCSI(NEXTDMA_CSR): 695 DPRINTF("SCSI DMA CSR READ\n"); 696 return next_state->dma[NEXTDMA_SCSI].csr; 697 case NEXTDMA_ENRX(NEXTDMA_CSR): 698 return next_state->dma[NEXTDMA_ENRX].csr; 699 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 700 return next_state->dma[NEXTDMA_ENRX].next_initbuf; 701 case NEXTDMA_ENRX(NEXTDMA_NEXT): 702 return next_state->dma[NEXTDMA_ENRX].next; 703 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 704 return next_state->dma[NEXTDMA_ENRX].limit; 705 706 case NEXTDMA_SCSI(NEXTDMA_NEXT): 707 return next_state->dma[NEXTDMA_SCSI].next; 708 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 709 return next_state->dma[NEXTDMA_SCSI].next_initbuf; 710 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 711 return next_state->dma[NEXTDMA_SCSI].limit; 712 case NEXTDMA_SCSI(NEXTDMA_START): 713 return next_state->dma[NEXTDMA_SCSI].start; 714 case NEXTDMA_SCSI(NEXTDMA_STOP): 715 return next_state->dma[NEXTDMA_SCSI].stop; 716 717 default: 718 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 719 return 0; 720 } 721 722 /* 723 * once the csr's are done, subtract 0x3FEC from the addr, and that will 724 * normalize the upper registers 725 */ 726 } 727 728 static const MemoryRegionOps dma_ops = { 729 .read = dma_readl, 730 .write = dma_writel, 731 .impl.min_access_size = 4, 732 .valid.min_access_size = 4, 733 .valid.max_access_size = 4, 734 .endianness = DEVICE_NATIVE_ENDIAN, 735 }; 736 737 /* 738 * TODO: set the shift numbers as values in the enum, so the first switch 739 * will not be needed 740 */ 741 static void next_irq(void *opaque, int number, int level) 742 { 743 M68kCPU *cpu = opaque; 744 int shift = 0; 745 NeXTState *ns = NEXT_MACHINE(qdev_get_machine()); 746 747 /* first switch sets interupt status */ 748 /* DPRINTF("IRQ %i\n",number); */ 749 switch (number) { 750 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 751 case NEXT_FD_I: 752 shift = 7; 753 break; 754 case NEXT_KBD_I: 755 shift = 3; 756 break; 757 case NEXT_PWR_I: 758 shift = 2; 759 break; 760 case NEXT_ENRX_I: 761 shift = 9; 762 break; 763 case NEXT_ENTX_I: 764 shift = 10; 765 break; 766 case NEXT_SCSI_I: 767 shift = 12; 768 break; 769 case NEXT_CLK_I: 770 shift = 5; 771 break; 772 773 /* level 5 - scc (serial) */ 774 case NEXT_SCC_I: 775 shift = 17; 776 break; 777 778 /* level 6 - audio etherrx/tx dma */ 779 case NEXT_ENTX_DMA_I: 780 shift = 28; 781 break; 782 case NEXT_ENRX_DMA_I: 783 shift = 27; 784 break; 785 case NEXT_SCSI_DMA_I: 786 shift = 26; 787 break; 788 case NEXT_SND_I: 789 shift = 23; 790 break; 791 case NEXT_SCC_DMA_I: 792 shift = 21; 793 break; 794 795 } 796 /* 797 * this HAS to be wrong, the interrupt handlers in mach and together 798 * int_status and int_mask and return if there is a hit 799 */ 800 if (ns->int_mask & (1 << shift)) { 801 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 802 /* return; */ 803 } 804 805 /* second switch triggers the correct interrupt */ 806 if (level) { 807 ns->int_status |= 1 << shift; 808 809 switch (number) { 810 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 811 case NEXT_FD_I: 812 case NEXT_KBD_I: 813 case NEXT_PWR_I: 814 case NEXT_ENRX_I: 815 case NEXT_ENTX_I: 816 case NEXT_SCSI_I: 817 case NEXT_CLK_I: 818 m68k_set_irq_level(cpu, 3, 27); 819 break; 820 821 /* level 5 - scc (serial) */ 822 case NEXT_SCC_I: 823 m68k_set_irq_level(cpu, 5, 29); 824 break; 825 826 /* level 6 - audio etherrx/tx dma */ 827 case NEXT_ENTX_DMA_I: 828 case NEXT_ENRX_DMA_I: 829 case NEXT_SCSI_DMA_I: 830 case NEXT_SND_I: 831 case NEXT_SCC_DMA_I: 832 m68k_set_irq_level(cpu, 6, 30); 833 break; 834 } 835 } else { 836 ns->int_status &= ~(1 << shift); 837 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 838 } 839 } 840 841 static void next_serial_irq(void *opaque, int n, int level) 842 { 843 /* DPRINTF("SCC IRQ NUM %i\n",n); */ 844 if (n) { 845 next_irq(opaque, NEXT_SCC_DMA_I, level); 846 } else { 847 next_irq(opaque, NEXT_SCC_I, level); 848 } 849 } 850 851 static void next_escc_init(M68kCPU *cpu) 852 { 853 qemu_irq *ser_irq = qemu_allocate_irqs(next_serial_irq, cpu, 2); 854 DeviceState *dev; 855 SysBusDevice *s; 856 857 dev = qdev_new(TYPE_ESCC); 858 qdev_prop_set_uint32(dev, "disabled", 0); 859 qdev_prop_set_uint32(dev, "frequency", 9600 * 384); 860 qdev_prop_set_uint32(dev, "it_shift", 0); 861 qdev_prop_set_bit(dev, "bit_swap", true); 862 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 863 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 864 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 865 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 866 867 s = SYS_BUS_DEVICE(dev); 868 sysbus_realize_and_unref(s, &error_fatal); 869 sysbus_connect_irq(s, 0, ser_irq[0]); 870 sysbus_connect_irq(s, 1, ser_irq[1]); 871 sysbus_mmio_map(s, 0, 0x2118000); 872 } 873 874 static void next_pc_reset(DeviceState *dev) 875 { 876 NeXTPC *s = NEXT_PC(dev); 877 878 /* Set internal registers to initial values */ 879 /* 0x0000XX00 << vital bits */ 880 s->scr1 = 0x00011102; 881 s->scr2 = 0x00ff0c80; 882 } 883 884 static void next_pc_realize(DeviceState *dev, Error **errp) 885 { 886 NeXTPC *s = NEXT_PC(dev); 887 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 888 889 memory_region_init_io(&s->mmiomem, OBJECT(s), &mmio_ops, s, 890 "next.mmio", 0xD0000); 891 memory_region_init_io(&s->scrmem, OBJECT(s), &scr_ops, s, 892 "next.scr", 0x20000); 893 sysbus_init_mmio(sbd, &s->mmiomem); 894 sysbus_init_mmio(sbd, &s->scrmem); 895 } 896 897 static void next_pc_class_init(ObjectClass *klass, void *data) 898 { 899 DeviceClass *dc = DEVICE_CLASS(klass); 900 901 dc->desc = "NeXT Peripheral Controller"; 902 dc->realize = next_pc_realize; 903 dc->reset = next_pc_reset; 904 /* We will add the VMState in a later commit */ 905 } 906 907 static const TypeInfo next_pc_info = { 908 .name = TYPE_NEXT_PC, 909 .parent = TYPE_SYS_BUS_DEVICE, 910 .instance_size = sizeof(NeXTPC), 911 .class_init = next_pc_class_init, 912 }; 913 914 static void next_cube_init(MachineState *machine) 915 { 916 M68kCPU *cpu; 917 CPUM68KState *env; 918 MemoryRegion *rom = g_new(MemoryRegion, 1); 919 MemoryRegion *dmamem = g_new(MemoryRegion, 1); 920 MemoryRegion *bmapm1 = g_new(MemoryRegion, 1); 921 MemoryRegion *bmapm2 = g_new(MemoryRegion, 1); 922 MemoryRegion *sysmem = get_system_memory(); 923 const char *bios_name = machine->firmware ?: ROM_FILE; 924 NeXTState *ns = NEXT_MACHINE(machine); 925 DeviceState *dev; 926 DeviceState *pcdev; 927 928 /* Initialize the cpu core */ 929 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 930 if (!cpu) { 931 error_report("Unable to find m68k CPU definition"); 932 exit(1); 933 } 934 env = &cpu->env; 935 936 /* Initialize CPU registers. */ 937 env->vbr = 0; 938 env->sr = 0x2700; 939 940 /* Peripheral Controller */ 941 pcdev = qdev_new(TYPE_NEXT_PC); 942 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 943 /* Temporary while we refactor this code */ 944 NEXT_PC(pcdev)->ns = ns; 945 946 ns->rtc.status = 0x90; 947 948 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 949 memcpy(ns->rtc.ram, rtc_ram2, 32); 950 951 /* 64MB RAM starting at 0x04000000 */ 952 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 953 954 /* Framebuffer */ 955 dev = qdev_new(TYPE_NEXTFB); 956 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 957 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000); 958 959 /* MMIO */ 960 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000); 961 962 /* BMAP IO - acts as a catch-all for now */ 963 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 964 965 /* BMAP memory */ 966 memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64, 967 true, &error_fatal); 968 memory_region_add_subregion(sysmem, 0x020c0000, bmapm1); 969 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 970 memory_region_init_alias(bmapm2, NULL, "next.bmapmem2", bmapm1, 0x0, 64); 971 memory_region_add_subregion(sysmem, 0x820c0000, bmapm2); 972 973 /* KBD */ 974 dev = qdev_new(TYPE_NEXTKBD); 975 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 976 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000); 977 978 /* Load ROM here */ 979 /* still not sure if the rom should also be mapped at 0x0*/ 980 memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal); 981 memory_region_add_subregion(sysmem, 0x01000000, rom); 982 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 983 if (!qtest_enabled()) { 984 error_report("Failed to load firmware '%s'.", bios_name); 985 } 986 } else { 987 uint8_t *ptr; 988 /* Initial PC is always at offset 4 in firmware binaries */ 989 ptr = rom_ptr(0x01000004, 4); 990 g_assert(ptr != NULL); 991 env->pc = ldl_p(ptr); 992 if (env->pc >= 0x01020000) { 993 error_report("'%s' does not seem to be a valid firmware image.", 994 bios_name); 995 exit(1); 996 } 997 } 998 999 /* Serial */ 1000 next_escc_init(cpu); 1001 1002 /* TODO: */ 1003 /* Network */ 1004 /* SCSI */ 1005 1006 /* DMA */ 1007 memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5000); 1008 memory_region_add_subregion(sysmem, 0x02000000, dmamem); 1009 } 1010 1011 static void next_machine_class_init(ObjectClass *oc, void *data) 1012 { 1013 MachineClass *mc = MACHINE_CLASS(oc); 1014 1015 mc->desc = "NeXT Cube"; 1016 mc->init = next_cube_init; 1017 mc->default_ram_size = RAM_SIZE; 1018 mc->default_ram_id = "next.ram"; 1019 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1020 } 1021 1022 static const TypeInfo next_typeinfo = { 1023 .name = TYPE_NEXT_MACHINE, 1024 .parent = TYPE_MACHINE, 1025 .class_init = next_machine_class_init, 1026 .instance_size = sizeof(NeXTState), 1027 }; 1028 1029 static void next_register_type(void) 1030 { 1031 type_register_static(&next_typeinfo); 1032 type_register_static(&next_pc_info); 1033 } 1034 1035 type_init(next_register_type) 1036