1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "cpu.h" 14 #include "exec/hwaddr.h" 15 #include "exec/address-spaces.h" 16 #include "sysemu/sysemu.h" 17 #include "sysemu/qtest.h" 18 #include "hw/irq.h" 19 #include "hw/m68k/next-cube.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "hw/scsi/esp.h" 23 #include "hw/sysbus.h" 24 #include "qom/object.h" 25 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 26 #include "hw/block/fdc.h" 27 #include "hw/qdev-properties.h" 28 #include "qapi/error.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 32 /* #define DEBUG_NEXT */ 33 #ifdef DEBUG_NEXT 34 #define DPRINTF(fmt, ...) \ 35 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 36 #else 37 #define DPRINTF(fmt, ...) do { } while (0) 38 #endif 39 40 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 41 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 42 43 #define ENTRY 0x0100001e 44 #define RAM_SIZE 0x4000000 45 #define ROM_FILE "Rev_2.5_v66.bin" 46 47 typedef struct next_dma { 48 uint32_t csr; 49 50 uint32_t saved_next; 51 uint32_t saved_limit; 52 uint32_t saved_start; 53 uint32_t saved_stop; 54 55 uint32_t next; 56 uint32_t limit; 57 uint32_t start; 58 uint32_t stop; 59 60 uint32_t next_initbuf; 61 uint32_t size; 62 } next_dma; 63 64 typedef struct NextRtc { 65 uint8_t ram[32]; 66 uint8_t command; 67 uint8_t value; 68 uint8_t status; 69 uint8_t control; 70 uint8_t retval; 71 } NextRtc; 72 73 struct NeXTState { 74 MachineState parent; 75 76 uint32_t int_mask; 77 uint32_t int_status; 78 79 uint8_t scsi_csr_1; 80 uint8_t scsi_csr_2; 81 next_dma dma[10]; 82 qemu_irq *scsi_irq; 83 qemu_irq scsi_dma; 84 qemu_irq scsi_reset; 85 qemu_irq *fd_irq; 86 87 NextRtc rtc; 88 }; 89 90 #define TYPE_NEXT_PC "next-pc" 91 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 92 93 /* NeXT Peripheral Controller */ 94 struct NeXTPC { 95 SysBusDevice parent_obj; 96 97 /* Temporary until all functionality has been moved into this device */ 98 NeXTState *ns; 99 100 MemoryRegion mmiomem; 101 102 uint32_t scr1; 103 uint32_t scr2; 104 }; 105 106 /* Thanks to NeXT forums for this */ 107 /* 108 static const uint8_t rtc_ram3[32] = { 109 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 110 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 111 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 113 }; 114 */ 115 static const uint8_t rtc_ram2[32] = { 116 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 117 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 118 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 120 }; 121 122 #define SCR2_RTCLK 0x2 123 #define SCR2_RTDATA 0x4 124 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 125 126 static void nextscr2_write(NeXTPC *s, uint32_t val, int size) 127 { 128 static int led; 129 static int phase; 130 static uint8_t old_scr2; 131 uint8_t scr2_2; 132 NextRtc *rtc = &s->ns->rtc; 133 134 if (size == 4) { 135 scr2_2 = (val >> 8) & 0xFF; 136 } else { 137 scr2_2 = val & 0xFF; 138 } 139 140 if (val & 0x1) { 141 DPRINTF("fault!\n"); 142 led++; 143 if (led == 10) { 144 DPRINTF("LED flashing, possible fault!\n"); 145 led = 0; 146 } 147 } 148 149 if (scr2_2 & 0x1) { 150 /* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */ 151 if (phase == -1) { 152 phase = 0; 153 } 154 /* If we are in going down clock... do something */ 155 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 156 ((scr2_2 & SCR2_RTCLK) == 0)) { 157 if (phase < 8) { 158 rtc->command = (rtc->command << 1) | 159 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 160 } 161 if (phase >= 8 && phase < 16) { 162 rtc->value = (rtc->value << 1) | 163 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 164 165 /* if we read RAM register, output RT_DATA bit */ 166 if (rtc->command <= 0x1F) { 167 scr2_2 = scr2_2 & (~SCR2_RTDATA); 168 if (rtc->ram[rtc->command] & (0x80 >> (phase - 8))) { 169 scr2_2 |= SCR2_RTDATA; 170 } 171 172 rtc->retval = (rtc->retval << 1) | 173 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 174 } 175 /* read the status 0x30 */ 176 if (rtc->command == 0x30) { 177 scr2_2 = scr2_2 & (~SCR2_RTDATA); 178 /* for now status = 0x98 (new rtc + FTU) */ 179 if (rtc->status & (0x80 >> (phase - 8))) { 180 scr2_2 |= SCR2_RTDATA; 181 } 182 183 rtc->retval = (rtc->retval << 1) | 184 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 185 } 186 /* read the status 0x31 */ 187 if (rtc->command == 0x31) { 188 scr2_2 = scr2_2 & (~SCR2_RTDATA); 189 if (rtc->control & (0x80 >> (phase - 8))) { 190 scr2_2 |= SCR2_RTDATA; 191 } 192 rtc->retval = (rtc->retval << 1) | 193 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 194 } 195 196 if ((rtc->command >= 0x20) && (rtc->command <= 0x2F)) { 197 scr2_2 = scr2_2 & (~SCR2_RTDATA); 198 /* for now 0x00 */ 199 time_t time_h = time(NULL); 200 struct tm *info = localtime(&time_h); 201 int ret = 0; 202 203 switch (rtc->command) { 204 case 0x20: 205 ret = SCR2_TOBCD(info->tm_sec); 206 break; 207 case 0x21: 208 ret = SCR2_TOBCD(info->tm_min); 209 break; 210 case 0x22: 211 ret = SCR2_TOBCD(info->tm_hour); 212 break; 213 case 0x24: 214 ret = SCR2_TOBCD(info->tm_mday); 215 break; 216 case 0x25: 217 ret = SCR2_TOBCD((info->tm_mon + 1)); 218 break; 219 case 0x26: 220 ret = SCR2_TOBCD((info->tm_year - 100)); 221 break; 222 223 } 224 225 if (ret & (0x80 >> (phase - 8))) { 226 scr2_2 |= SCR2_RTDATA; 227 } 228 rtc->retval = (rtc->retval << 1) | 229 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 230 } 231 232 } 233 234 phase++; 235 if (phase == 16) { 236 if (rtc->command >= 0x80 && rtc->command <= 0x9F) { 237 rtc->ram[rtc->command - 0x80] = rtc->value; 238 } 239 /* write to x30 register */ 240 if (rtc->command == 0xB1) { 241 /* clear FTU */ 242 if (rtc->value & 0x04) { 243 rtc->status = rtc->status & (~0x18); 244 s->ns->int_status = s->ns->int_status & (~0x04); 245 } 246 } 247 } 248 } 249 } else { 250 /* else end or abort */ 251 phase = -1; 252 rtc->command = 0; 253 rtc->value = 0; 254 } 255 s->scr2 = val & 0xFFFF00FF; 256 s->scr2 |= scr2_2 << 8; 257 old_scr2 = scr2_2; 258 } 259 260 static uint32_t mmio_readb(NeXTPC *s, hwaddr addr) 261 { 262 switch (addr) { 263 case 0xc000: 264 return (s->scr1 >> 24) & 0xFF; 265 case 0xc001: 266 return (s->scr1 >> 16) & 0xFF; 267 case 0xc002: 268 return (s->scr1 >> 8) & 0xFF; 269 case 0xc003: 270 return (s->scr1 >> 0) & 0xFF; 271 272 case 0xd000: 273 return (s->scr2 >> 24) & 0xFF; 274 case 0xd001: 275 return (s->scr2 >> 16) & 0xFF; 276 case 0xd002: 277 return (s->scr2 >> 8) & 0xFF; 278 case 0xd003: 279 return (s->scr2 >> 0) & 0xFF; 280 case 0x14020: 281 DPRINTF("MMIO Read 0x4020\n"); 282 return 0x7f; 283 284 default: 285 DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr); 286 return 0x0; 287 } 288 } 289 290 static uint32_t mmio_readw(NeXTPC *s, hwaddr addr) 291 { 292 switch (addr) { 293 default: 294 DPRINTF("MMIO Read W @ %"HWADDR_PRIx"\n", addr); 295 return 0x0; 296 } 297 } 298 299 static uint32_t mmio_readl(NeXTPC *s, hwaddr addr) 300 { 301 switch (addr) { 302 case 0x7000: 303 /* DPRINTF("Read INT status: %x\n", s->ns->int_status); */ 304 return s->ns->int_status; 305 306 case 0x7800: 307 DPRINTF("MMIO Read INT mask: %x\n", s->ns->int_mask); 308 return s->ns->int_mask; 309 310 case 0xc000: 311 return s->scr1; 312 313 case 0xd000: 314 return s->scr2; 315 316 default: 317 DPRINTF("MMIO Read L @ %"HWADDR_PRIx"\n", addr); 318 return 0x0; 319 } 320 } 321 322 static void mmio_writeb(NeXTPC *s, hwaddr addr, uint32_t val) 323 { 324 switch (addr) { 325 case 0xd003: 326 nextscr2_write(s, val, 1); 327 break; 328 default: 329 DPRINTF("MMIO Write B @ %x with %x\n", (unsigned int)addr, val); 330 } 331 332 } 333 334 static void mmio_writew(NeXTPC *s, hwaddr addr, uint32_t val) 335 { 336 DPRINTF("MMIO Write W\n"); 337 } 338 339 static void mmio_writel(NeXTPC *s, hwaddr addr, uint32_t val) 340 { 341 switch (addr) { 342 case 0x7000: 343 DPRINTF("INT Status old: %x new: %x\n", s->ns->int_status, val); 344 s->ns->int_status = val; 345 break; 346 case 0x7800: 347 DPRINTF("INT Mask old: %x new: %x\n", s->ns->int_mask, val); 348 s->ns->int_mask = val; 349 break; 350 case 0xc000: 351 DPRINTF("SCR1 Write: %x\n", val); 352 break; 353 case 0xd000: 354 nextscr2_write(s, val, 4); 355 break; 356 357 default: 358 DPRINTF("MMIO Write l @ %x with %x\n", (unsigned int)addr, val); 359 } 360 } 361 362 static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size) 363 { 364 NeXTPC *s = NEXT_PC(opaque); 365 366 switch (size) { 367 case 1: 368 return mmio_readb(s, addr); 369 case 2: 370 return mmio_readw(s, addr); 371 case 4: 372 return mmio_readl(s, addr); 373 default: 374 g_assert_not_reached(); 375 } 376 } 377 378 static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value, 379 unsigned size) 380 { 381 NeXTPC *s = NEXT_PC(opaque); 382 383 switch (size) { 384 case 1: 385 mmio_writeb(s, addr, value); 386 break; 387 case 2: 388 mmio_writew(s, addr, value); 389 break; 390 case 4: 391 mmio_writel(s, addr, value); 392 break; 393 default: 394 g_assert_not_reached(); 395 } 396 } 397 398 static const MemoryRegionOps mmio_ops = { 399 .read = mmio_readfn, 400 .write = mmio_writefn, 401 .valid.min_access_size = 1, 402 .valid.max_access_size = 4, 403 .endianness = DEVICE_NATIVE_ENDIAN, 404 }; 405 406 static uint32_t scr_readb(NeXTState *s, hwaddr addr) 407 { 408 switch (addr) { 409 case 0x14108: 410 DPRINTF("FD read @ %x\n", (unsigned int)addr); 411 return 0x40 | 0x04 | 0x2 | 0x1; 412 case 0x14020: 413 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 414 return s->scsi_csr_1; 415 416 case 0x14021: 417 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 418 return 0x40; 419 420 /* 421 * These 4 registers are the hardware timer, not sure which register 422 * is the latch instead of data, but no problems so far 423 */ 424 case 0x1a000: 425 return 0xff & (clock() >> 24); 426 case 0x1a001: 427 return 0xff & (clock() >> 16); 428 case 0x1a002: 429 return 0xff & (clock() >> 8); 430 case 0x1a003: 431 /* Hack: We need to have this change consistently to make it work */ 432 return 0xFF & clock(); 433 434 default: 435 DPRINTF("BMAP Read B @ %x\n", (unsigned int)addr); 436 return 0; 437 } 438 } 439 440 static uint32_t scr_readw(NeXTState *s, hwaddr addr) 441 { 442 DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr); 443 return 0; 444 } 445 446 static uint32_t scr_readl(NeXTState *s, hwaddr addr) 447 { 448 DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr); 449 return 0; 450 } 451 452 #define SCSICSR_ENABLE 0x01 453 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 454 #define SCSICSR_FIFOFL 0x04 455 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 456 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 457 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 458 459 static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value) 460 { 461 switch (addr) { 462 case 0x14108: 463 DPRINTF("FDCSR Write: %x\n", value); 464 465 if (value == 0x0) { 466 /* qemu_irq_raise(s->fd_irq[0]); */ 467 } 468 break; 469 case 0x14020: /* SCSI Control Register */ 470 if (value & SCSICSR_FIFOFL) { 471 DPRINTF("SCSICSR FIFO Flush\n"); 472 /* will have to add another irq to the esp if this is needed */ 473 /* esp_puflush_fifo(esp_g); */ 474 /* qemu_irq_pulse(s->scsi_dma); */ 475 } 476 477 if (value & SCSICSR_ENABLE) { 478 DPRINTF("SCSICSR Enable\n"); 479 /* 480 * qemu_irq_raise(s->scsi_dma); 481 * s->scsi_csr_1 = 0xc0; 482 * s->scsi_csr_1 |= 0x1; 483 * qemu_irq_pulse(s->scsi_dma); 484 */ 485 } 486 /* 487 * else 488 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 489 */ 490 491 if (value & SCSICSR_RESET) { 492 DPRINTF("SCSICSR Reset\n"); 493 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 494 /* qemu_irq_raise(s->scsi_reset); */ 495 /* s->scsi_csr_1 &= ~(SCSICSR_INTMASK |0x80|0x1); */ 496 497 } 498 if (value & SCSICSR_DMADIR) { 499 DPRINTF("SCSICSR DMAdir\n"); 500 } 501 if (value & SCSICSR_CPUDMA) { 502 DPRINTF("SCSICSR CPUDMA\n"); 503 /* qemu_irq_raise(s->scsi_dma); */ 504 505 s->int_status |= 0x4000000; 506 } else { 507 s->int_status &= ~(0x4000000); 508 } 509 if (value & SCSICSR_INTMASK) { 510 DPRINTF("SCSICSR INTMASK\n"); 511 /* 512 * int_mask &= ~0x1000; 513 * s->scsi_csr_1 |= value; 514 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 515 * if (s->scsi_queued) { 516 * s->scsi_queued = 0; 517 * next_irq(s, NEXT_SCSI_I, level); 518 * } 519 */ 520 } else { 521 /* int_mask |= 0x1000; */ 522 } 523 if (value & 0x80) { 524 /* int_mask |= 0x1000; */ 525 /* s->scsi_csr_1 |= 0x80; */ 526 } 527 DPRINTF("SCSICSR Write: %x\n", value); 528 /* s->scsi_csr_1 = value; */ 529 return; 530 /* Hardware timer latch - not implemented yet */ 531 case 0x1a000: 532 default: 533 DPRINTF("BMAP Write B @ %x with %x\n", (unsigned int)addr, value); 534 } 535 } 536 537 static void scr_writew(NeXTState *s, hwaddr addr, uint32_t value) 538 { 539 DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value); 540 } 541 542 static void scr_writel(NeXTState *s, hwaddr addr, uint32_t value) 543 { 544 DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value); 545 } 546 547 static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size) 548 { 549 NeXTState *ns = NEXT_MACHINE(opaque); 550 551 switch (size) { 552 case 1: 553 return scr_readb(ns, addr); 554 case 2: 555 return scr_readw(ns, addr); 556 case 4: 557 return scr_readl(ns, addr); 558 default: 559 g_assert_not_reached(); 560 } 561 } 562 563 static void scr_writefn(void *opaque, hwaddr addr, uint64_t value, 564 unsigned size) 565 { 566 NeXTState *ns = NEXT_MACHINE(opaque); 567 568 switch (size) { 569 case 1: 570 scr_writeb(ns, addr, value); 571 break; 572 case 2: 573 scr_writew(ns, addr, value); 574 break; 575 case 4: 576 scr_writel(ns, addr, value); 577 break; 578 default: 579 g_assert_not_reached(); 580 } 581 } 582 583 static const MemoryRegionOps scr_ops = { 584 .read = scr_readfn, 585 .write = scr_writefn, 586 .valid.min_access_size = 1, 587 .valid.max_access_size = 4, 588 .endianness = DEVICE_NATIVE_ENDIAN, 589 }; 590 591 #define NEXTDMA_SCSI(x) (0x10 + x) 592 #define NEXTDMA_FD(x) (0x10 + x) 593 #define NEXTDMA_ENTX(x) (0x110 + x) 594 #define NEXTDMA_ENRX(x) (0x150 + x) 595 #define NEXTDMA_CSR 0x0 596 #define NEXTDMA_NEXT 0x4000 597 #define NEXTDMA_LIMIT 0x4004 598 #define NEXTDMA_START 0x4008 599 #define NEXTDMA_STOP 0x400c 600 #define NEXTDMA_NEXT_INIT 0x4200 601 #define NEXTDMA_SIZE 0x4204 602 603 static void dma_writel(void *opaque, hwaddr addr, uint64_t value, 604 unsigned int size) 605 { 606 NeXTState *next_state = NEXT_MACHINE(opaque); 607 608 switch (addr) { 609 case NEXTDMA_ENRX(NEXTDMA_CSR): 610 if (value & DMA_DEV2M) { 611 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 612 } 613 614 if (value & DMA_SETENABLE) { 615 /* DPRINTF("SCSI DMA ENABLE\n"); */ 616 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 617 } 618 if (value & DMA_SETSUPDATE) { 619 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 620 } 621 if (value & DMA_CLRCOMPLETE) { 622 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 623 } 624 625 if (value & DMA_RESET) { 626 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 627 DMA_ENABLE | DMA_DEV2M); 628 } 629 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 630 break; 631 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 632 next_state->dma[NEXTDMA_ENRX].next_initbuf = value; 633 break; 634 case NEXTDMA_ENRX(NEXTDMA_NEXT): 635 next_state->dma[NEXTDMA_ENRX].next = value; 636 break; 637 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 638 next_state->dma[NEXTDMA_ENRX].limit = value; 639 break; 640 case NEXTDMA_SCSI(NEXTDMA_CSR): 641 if (value & DMA_DEV2M) { 642 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 643 } 644 if (value & DMA_SETENABLE) { 645 /* DPRINTF("SCSI DMA ENABLE\n"); */ 646 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 647 } 648 if (value & DMA_SETSUPDATE) { 649 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 650 } 651 if (value & DMA_CLRCOMPLETE) { 652 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 653 } 654 655 if (value & DMA_RESET) { 656 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 657 DMA_ENABLE | DMA_DEV2M); 658 /* DPRINTF("SCSI DMA RESET\n"); */ 659 } 660 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 661 break; 662 663 case NEXTDMA_SCSI(NEXTDMA_NEXT): 664 next_state->dma[NEXTDMA_SCSI].next = value; 665 break; 666 667 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 668 next_state->dma[NEXTDMA_SCSI].limit = value; 669 break; 670 671 case NEXTDMA_SCSI(NEXTDMA_START): 672 next_state->dma[NEXTDMA_SCSI].start = value; 673 break; 674 675 case NEXTDMA_SCSI(NEXTDMA_STOP): 676 next_state->dma[NEXTDMA_SCSI].stop = value; 677 break; 678 679 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 680 next_state->dma[NEXTDMA_SCSI].next_initbuf = value; 681 break; 682 683 default: 684 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)value); 685 } 686 } 687 688 static uint64_t dma_readl(void *opaque, hwaddr addr, unsigned int size) 689 { 690 NeXTState *next_state = NEXT_MACHINE(opaque); 691 692 switch (addr) { 693 case NEXTDMA_SCSI(NEXTDMA_CSR): 694 DPRINTF("SCSI DMA CSR READ\n"); 695 return next_state->dma[NEXTDMA_SCSI].csr; 696 case NEXTDMA_ENRX(NEXTDMA_CSR): 697 return next_state->dma[NEXTDMA_ENRX].csr; 698 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 699 return next_state->dma[NEXTDMA_ENRX].next_initbuf; 700 case NEXTDMA_ENRX(NEXTDMA_NEXT): 701 return next_state->dma[NEXTDMA_ENRX].next; 702 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 703 return next_state->dma[NEXTDMA_ENRX].limit; 704 705 case NEXTDMA_SCSI(NEXTDMA_NEXT): 706 return next_state->dma[NEXTDMA_SCSI].next; 707 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 708 return next_state->dma[NEXTDMA_SCSI].next_initbuf; 709 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 710 return next_state->dma[NEXTDMA_SCSI].limit; 711 case NEXTDMA_SCSI(NEXTDMA_START): 712 return next_state->dma[NEXTDMA_SCSI].start; 713 case NEXTDMA_SCSI(NEXTDMA_STOP): 714 return next_state->dma[NEXTDMA_SCSI].stop; 715 716 default: 717 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 718 return 0; 719 } 720 721 /* 722 * once the csr's are done, subtract 0x3FEC from the addr, and that will 723 * normalize the upper registers 724 */ 725 } 726 727 static const MemoryRegionOps dma_ops = { 728 .read = dma_readl, 729 .write = dma_writel, 730 .impl.min_access_size = 4, 731 .valid.min_access_size = 4, 732 .valid.max_access_size = 4, 733 .endianness = DEVICE_NATIVE_ENDIAN, 734 }; 735 736 /* 737 * TODO: set the shift numbers as values in the enum, so the first switch 738 * will not be needed 739 */ 740 static void next_irq(void *opaque, int number, int level) 741 { 742 M68kCPU *cpu = opaque; 743 int shift = 0; 744 NeXTState *ns = NEXT_MACHINE(qdev_get_machine()); 745 746 /* first switch sets interupt status */ 747 /* DPRINTF("IRQ %i\n",number); */ 748 switch (number) { 749 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 750 case NEXT_FD_I: 751 shift = 7; 752 break; 753 case NEXT_KBD_I: 754 shift = 3; 755 break; 756 case NEXT_PWR_I: 757 shift = 2; 758 break; 759 case NEXT_ENRX_I: 760 shift = 9; 761 break; 762 case NEXT_ENTX_I: 763 shift = 10; 764 break; 765 case NEXT_SCSI_I: 766 shift = 12; 767 break; 768 case NEXT_CLK_I: 769 shift = 5; 770 break; 771 772 /* level 5 - scc (serial) */ 773 case NEXT_SCC_I: 774 shift = 17; 775 break; 776 777 /* level 6 - audio etherrx/tx dma */ 778 case NEXT_ENTX_DMA_I: 779 shift = 28; 780 break; 781 case NEXT_ENRX_DMA_I: 782 shift = 27; 783 break; 784 case NEXT_SCSI_DMA_I: 785 shift = 26; 786 break; 787 case NEXT_SND_I: 788 shift = 23; 789 break; 790 case NEXT_SCC_DMA_I: 791 shift = 21; 792 break; 793 794 } 795 /* 796 * this HAS to be wrong, the interrupt handlers in mach and together 797 * int_status and int_mask and return if there is a hit 798 */ 799 if (ns->int_mask & (1 << shift)) { 800 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 801 /* return; */ 802 } 803 804 /* second switch triggers the correct interrupt */ 805 if (level) { 806 ns->int_status |= 1 << shift; 807 808 switch (number) { 809 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 810 case NEXT_FD_I: 811 case NEXT_KBD_I: 812 case NEXT_PWR_I: 813 case NEXT_ENRX_I: 814 case NEXT_ENTX_I: 815 case NEXT_SCSI_I: 816 case NEXT_CLK_I: 817 m68k_set_irq_level(cpu, 3, 27); 818 break; 819 820 /* level 5 - scc (serial) */ 821 case NEXT_SCC_I: 822 m68k_set_irq_level(cpu, 5, 29); 823 break; 824 825 /* level 6 - audio etherrx/tx dma */ 826 case NEXT_ENTX_DMA_I: 827 case NEXT_ENRX_DMA_I: 828 case NEXT_SCSI_DMA_I: 829 case NEXT_SND_I: 830 case NEXT_SCC_DMA_I: 831 m68k_set_irq_level(cpu, 6, 30); 832 break; 833 } 834 } else { 835 ns->int_status &= ~(1 << shift); 836 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 837 } 838 } 839 840 static void next_serial_irq(void *opaque, int n, int level) 841 { 842 /* DPRINTF("SCC IRQ NUM %i\n",n); */ 843 if (n) { 844 next_irq(opaque, NEXT_SCC_DMA_I, level); 845 } else { 846 next_irq(opaque, NEXT_SCC_I, level); 847 } 848 } 849 850 static void next_escc_init(M68kCPU *cpu) 851 { 852 qemu_irq *ser_irq = qemu_allocate_irqs(next_serial_irq, cpu, 2); 853 DeviceState *dev; 854 SysBusDevice *s; 855 856 dev = qdev_new(TYPE_ESCC); 857 qdev_prop_set_uint32(dev, "disabled", 0); 858 qdev_prop_set_uint32(dev, "frequency", 9600 * 384); 859 qdev_prop_set_uint32(dev, "it_shift", 0); 860 qdev_prop_set_bit(dev, "bit_swap", true); 861 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 862 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 863 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 864 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 865 866 s = SYS_BUS_DEVICE(dev); 867 sysbus_realize_and_unref(s, &error_fatal); 868 sysbus_connect_irq(s, 0, ser_irq[0]); 869 sysbus_connect_irq(s, 1, ser_irq[1]); 870 sysbus_mmio_map(s, 0, 0x2118000); 871 } 872 873 static void next_pc_reset(DeviceState *dev) 874 { 875 NeXTPC *s = NEXT_PC(dev); 876 877 /* Set internal registers to initial values */ 878 /* 0x0000XX00 << vital bits */ 879 s->scr1 = 0x00011102; 880 s->scr2 = 0x00ff0c80; 881 } 882 883 static void next_pc_realize(DeviceState *dev, Error **errp) 884 { 885 NeXTPC *s = NEXT_PC(dev); 886 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 887 888 memory_region_init_io(&s->mmiomem, OBJECT(s), &mmio_ops, s, 889 "next.mmio", 0xD0000); 890 891 sysbus_init_mmio(sbd, &s->mmiomem); 892 } 893 894 static void next_pc_class_init(ObjectClass *klass, void *data) 895 { 896 DeviceClass *dc = DEVICE_CLASS(klass); 897 898 dc->desc = "NeXT Peripheral Controller"; 899 dc->realize = next_pc_realize; 900 dc->reset = next_pc_reset; 901 /* We will add the VMState in a later commit */ 902 } 903 904 static const TypeInfo next_pc_info = { 905 .name = TYPE_NEXT_PC, 906 .parent = TYPE_SYS_BUS_DEVICE, 907 .instance_size = sizeof(NeXTPC), 908 .class_init = next_pc_class_init, 909 }; 910 911 static void next_cube_init(MachineState *machine) 912 { 913 M68kCPU *cpu; 914 CPUM68KState *env; 915 MemoryRegion *rom = g_new(MemoryRegion, 1); 916 MemoryRegion *scrmem = g_new(MemoryRegion, 1); 917 MemoryRegion *dmamem = g_new(MemoryRegion, 1); 918 MemoryRegion *bmapm1 = g_new(MemoryRegion, 1); 919 MemoryRegion *bmapm2 = g_new(MemoryRegion, 1); 920 MemoryRegion *sysmem = get_system_memory(); 921 const char *bios_name = machine->firmware ?: ROM_FILE; 922 NeXTState *ns = NEXT_MACHINE(machine); 923 DeviceState *dev; 924 DeviceState *pcdev; 925 926 /* Initialize the cpu core */ 927 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 928 if (!cpu) { 929 error_report("Unable to find m68k CPU definition"); 930 exit(1); 931 } 932 env = &cpu->env; 933 934 /* Initialize CPU registers. */ 935 env->vbr = 0; 936 env->sr = 0x2700; 937 938 /* Peripheral Controller */ 939 pcdev = qdev_new(TYPE_NEXT_PC); 940 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 941 /* Temporary while we refactor this code */ 942 NEXT_PC(pcdev)->ns = ns; 943 944 ns->rtc.status = 0x90; 945 946 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 947 memcpy(ns->rtc.ram, rtc_ram2, 32); 948 949 /* 64MB RAM starting at 0x04000000 */ 950 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 951 952 /* Framebuffer */ 953 dev = qdev_new(TYPE_NEXTFB); 954 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 955 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000); 956 957 /* MMIO */ 958 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000); 959 960 /* BMAP memory */ 961 memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64, 962 true, &error_fatal); 963 memory_region_add_subregion(sysmem, 0x020c0000, bmapm1); 964 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 965 memory_region_init_alias(bmapm2, NULL, "next.bmapmem2", bmapm1, 0x0, 64); 966 memory_region_add_subregion(sysmem, 0x820c0000, bmapm2); 967 968 /* BMAP IO - acts as a catch-all for now */ 969 memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr", 970 0x20000); 971 memory_region_add_subregion(sysmem, 0x02100000, scrmem); 972 973 /* KBD */ 974 dev = qdev_new(TYPE_NEXTKBD); 975 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 976 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000); 977 978 /* Load ROM here */ 979 /* still not sure if the rom should also be mapped at 0x0*/ 980 memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal); 981 memory_region_add_subregion(sysmem, 0x01000000, rom); 982 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 983 if (!qtest_enabled()) { 984 error_report("Failed to load firmware '%s'.", bios_name); 985 } 986 } else { 987 uint8_t *ptr; 988 /* Initial PC is always at offset 4 in firmware binaries */ 989 ptr = rom_ptr(0x01000004, 4); 990 g_assert(ptr != NULL); 991 env->pc = ldl_p(ptr); 992 if (env->pc >= 0x01020000) { 993 error_report("'%s' does not seem to be a valid firmware image.", 994 bios_name); 995 exit(1); 996 } 997 } 998 999 /* Serial */ 1000 next_escc_init(cpu); 1001 1002 /* TODO: */ 1003 /* Network */ 1004 /* SCSI */ 1005 1006 /* DMA */ 1007 memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5000); 1008 memory_region_add_subregion(sysmem, 0x02000000, dmamem); 1009 } 1010 1011 static void next_machine_class_init(ObjectClass *oc, void *data) 1012 { 1013 MachineClass *mc = MACHINE_CLASS(oc); 1014 1015 mc->desc = "NeXT Cube"; 1016 mc->init = next_cube_init; 1017 mc->default_ram_size = RAM_SIZE; 1018 mc->default_ram_id = "next.ram"; 1019 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1020 } 1021 1022 static const TypeInfo next_typeinfo = { 1023 .name = TYPE_NEXT_MACHINE, 1024 .parent = TYPE_MACHINE, 1025 .class_init = next_machine_class_init, 1026 .instance_size = sizeof(NeXTState), 1027 }; 1028 1029 static void next_register_type(void) 1030 { 1031 type_register_static(&next_typeinfo); 1032 type_register_static(&next_pc_info); 1033 } 1034 1035 type_init(next_register_type) 1036