1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "cpu.h" 14 #include "exec/hwaddr.h" 15 #include "exec/address-spaces.h" 16 #include "sysemu/sysemu.h" 17 #include "sysemu/qtest.h" 18 #include "hw/irq.h" 19 #include "hw/m68k/next-cube.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "hw/scsi/esp.h" 23 #include "hw/sysbus.h" 24 #include "qom/object.h" 25 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 26 #include "hw/block/fdc.h" 27 #include "hw/qdev-properties.h" 28 #include "qapi/error.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 32 /* #define DEBUG_NEXT */ 33 #ifdef DEBUG_NEXT 34 #define DPRINTF(fmt, ...) \ 35 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 36 #else 37 #define DPRINTF(fmt, ...) do { } while (0) 38 #endif 39 40 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 41 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 42 43 #define ENTRY 0x0100001e 44 #define RAM_SIZE 0x4000000 45 #define ROM_FILE "Rev_2.5_v66.bin" 46 47 typedef struct next_dma { 48 uint32_t csr; 49 50 uint32_t saved_next; 51 uint32_t saved_limit; 52 uint32_t saved_start; 53 uint32_t saved_stop; 54 55 uint32_t next; 56 uint32_t limit; 57 uint32_t start; 58 uint32_t stop; 59 60 uint32_t next_initbuf; 61 uint32_t size; 62 } next_dma; 63 64 typedef struct NextRtc { 65 uint8_t ram[32]; 66 uint8_t command; 67 uint8_t value; 68 uint8_t status; 69 uint8_t control; 70 uint8_t retval; 71 } NextRtc; 72 73 struct NeXTState { 74 MachineState parent; 75 76 next_dma dma[10]; 77 qemu_irq *scsi_irq; 78 qemu_irq scsi_dma; 79 qemu_irq scsi_reset; 80 qemu_irq *fd_irq; 81 }; 82 83 #define TYPE_NEXT_PC "next-pc" 84 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 85 86 /* NeXT Peripheral Controller */ 87 struct NeXTPC { 88 SysBusDevice parent_obj; 89 90 M68kCPU *cpu; 91 92 MemoryRegion mmiomem; 93 MemoryRegion scrmem; 94 95 uint32_t scr1; 96 uint32_t scr2; 97 uint8_t scsi_csr_1; 98 uint8_t scsi_csr_2; 99 uint32_t int_mask; 100 uint32_t int_status; 101 102 NextRtc rtc; 103 }; 104 105 /* Thanks to NeXT forums for this */ 106 /* 107 static const uint8_t rtc_ram3[32] = { 108 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 109 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 110 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 111 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 112 }; 113 */ 114 static const uint8_t rtc_ram2[32] = { 115 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 116 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 117 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 119 }; 120 121 #define SCR2_RTCLK 0x2 122 #define SCR2_RTDATA 0x4 123 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 124 125 static void nextscr2_write(NeXTPC *s, uint32_t val, int size) 126 { 127 static int led; 128 static int phase; 129 static uint8_t old_scr2; 130 uint8_t scr2_2; 131 NextRtc *rtc = &s->rtc; 132 133 if (size == 4) { 134 scr2_2 = (val >> 8) & 0xFF; 135 } else { 136 scr2_2 = val & 0xFF; 137 } 138 139 if (val & 0x1) { 140 DPRINTF("fault!\n"); 141 led++; 142 if (led == 10) { 143 DPRINTF("LED flashing, possible fault!\n"); 144 led = 0; 145 } 146 } 147 148 if (scr2_2 & 0x1) { 149 /* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */ 150 if (phase == -1) { 151 phase = 0; 152 } 153 /* If we are in going down clock... do something */ 154 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 155 ((scr2_2 & SCR2_RTCLK) == 0)) { 156 if (phase < 8) { 157 rtc->command = (rtc->command << 1) | 158 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 159 } 160 if (phase >= 8 && phase < 16) { 161 rtc->value = (rtc->value << 1) | 162 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 163 164 /* if we read RAM register, output RT_DATA bit */ 165 if (rtc->command <= 0x1F) { 166 scr2_2 = scr2_2 & (~SCR2_RTDATA); 167 if (rtc->ram[rtc->command] & (0x80 >> (phase - 8))) { 168 scr2_2 |= SCR2_RTDATA; 169 } 170 171 rtc->retval = (rtc->retval << 1) | 172 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 173 } 174 /* read the status 0x30 */ 175 if (rtc->command == 0x30) { 176 scr2_2 = scr2_2 & (~SCR2_RTDATA); 177 /* for now status = 0x98 (new rtc + FTU) */ 178 if (rtc->status & (0x80 >> (phase - 8))) { 179 scr2_2 |= SCR2_RTDATA; 180 } 181 182 rtc->retval = (rtc->retval << 1) | 183 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 184 } 185 /* read the status 0x31 */ 186 if (rtc->command == 0x31) { 187 scr2_2 = scr2_2 & (~SCR2_RTDATA); 188 if (rtc->control & (0x80 >> (phase - 8))) { 189 scr2_2 |= SCR2_RTDATA; 190 } 191 rtc->retval = (rtc->retval << 1) | 192 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 193 } 194 195 if ((rtc->command >= 0x20) && (rtc->command <= 0x2F)) { 196 scr2_2 = scr2_2 & (~SCR2_RTDATA); 197 /* for now 0x00 */ 198 time_t time_h = time(NULL); 199 struct tm *info = localtime(&time_h); 200 int ret = 0; 201 202 switch (rtc->command) { 203 case 0x20: 204 ret = SCR2_TOBCD(info->tm_sec); 205 break; 206 case 0x21: 207 ret = SCR2_TOBCD(info->tm_min); 208 break; 209 case 0x22: 210 ret = SCR2_TOBCD(info->tm_hour); 211 break; 212 case 0x24: 213 ret = SCR2_TOBCD(info->tm_mday); 214 break; 215 case 0x25: 216 ret = SCR2_TOBCD((info->tm_mon + 1)); 217 break; 218 case 0x26: 219 ret = SCR2_TOBCD((info->tm_year - 100)); 220 break; 221 222 } 223 224 if (ret & (0x80 >> (phase - 8))) { 225 scr2_2 |= SCR2_RTDATA; 226 } 227 rtc->retval = (rtc->retval << 1) | 228 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 229 } 230 231 } 232 233 phase++; 234 if (phase == 16) { 235 if (rtc->command >= 0x80 && rtc->command <= 0x9F) { 236 rtc->ram[rtc->command - 0x80] = rtc->value; 237 } 238 /* write to x30 register */ 239 if (rtc->command == 0xB1) { 240 /* clear FTU */ 241 if (rtc->value & 0x04) { 242 rtc->status = rtc->status & (~0x18); 243 s->int_status = s->int_status & (~0x04); 244 } 245 } 246 } 247 } 248 } else { 249 /* else end or abort */ 250 phase = -1; 251 rtc->command = 0; 252 rtc->value = 0; 253 } 254 s->scr2 = val & 0xFFFF00FF; 255 s->scr2 |= scr2_2 << 8; 256 old_scr2 = scr2_2; 257 } 258 259 static uint32_t mmio_readb(NeXTPC *s, hwaddr addr) 260 { 261 switch (addr) { 262 case 0xc000: 263 return (s->scr1 >> 24) & 0xFF; 264 case 0xc001: 265 return (s->scr1 >> 16) & 0xFF; 266 case 0xc002: 267 return (s->scr1 >> 8) & 0xFF; 268 case 0xc003: 269 return (s->scr1 >> 0) & 0xFF; 270 271 case 0xd000: 272 return (s->scr2 >> 24) & 0xFF; 273 case 0xd001: 274 return (s->scr2 >> 16) & 0xFF; 275 case 0xd002: 276 return (s->scr2 >> 8) & 0xFF; 277 case 0xd003: 278 return (s->scr2 >> 0) & 0xFF; 279 case 0x14020: 280 DPRINTF("MMIO Read 0x4020\n"); 281 return 0x7f; 282 283 default: 284 DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr); 285 return 0x0; 286 } 287 } 288 289 static uint32_t mmio_readw(NeXTPC *s, hwaddr addr) 290 { 291 switch (addr) { 292 default: 293 DPRINTF("MMIO Read W @ %"HWADDR_PRIx"\n", addr); 294 return 0x0; 295 } 296 } 297 298 static uint32_t mmio_readl(NeXTPC *s, hwaddr addr) 299 { 300 switch (addr) { 301 case 0x7000: 302 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 303 return s->int_status; 304 305 case 0x7800: 306 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 307 return s->int_mask; 308 309 case 0xc000: 310 return s->scr1; 311 312 case 0xd000: 313 return s->scr2; 314 315 default: 316 DPRINTF("MMIO Read L @ %"HWADDR_PRIx"\n", addr); 317 return 0x0; 318 } 319 } 320 321 static void mmio_writeb(NeXTPC *s, hwaddr addr, uint32_t val) 322 { 323 switch (addr) { 324 case 0xd003: 325 nextscr2_write(s, val, 1); 326 break; 327 default: 328 DPRINTF("MMIO Write B @ %x with %x\n", (unsigned int)addr, val); 329 } 330 331 } 332 333 static void mmio_writew(NeXTPC *s, hwaddr addr, uint32_t val) 334 { 335 DPRINTF("MMIO Write W\n"); 336 } 337 338 static void mmio_writel(NeXTPC *s, hwaddr addr, uint32_t val) 339 { 340 switch (addr) { 341 case 0x7000: 342 DPRINTF("INT Status old: %x new: %x\n", s->int_status, val); 343 s->int_status = val; 344 break; 345 case 0x7800: 346 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val); 347 s->int_mask = val; 348 break; 349 case 0xc000: 350 DPRINTF("SCR1 Write: %x\n", val); 351 break; 352 case 0xd000: 353 nextscr2_write(s, val, 4); 354 break; 355 356 default: 357 DPRINTF("MMIO Write l @ %x with %x\n", (unsigned int)addr, val); 358 } 359 } 360 361 static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size) 362 { 363 NeXTPC *s = NEXT_PC(opaque); 364 365 switch (size) { 366 case 1: 367 return mmio_readb(s, addr); 368 case 2: 369 return mmio_readw(s, addr); 370 case 4: 371 return mmio_readl(s, addr); 372 default: 373 g_assert_not_reached(); 374 } 375 } 376 377 static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value, 378 unsigned size) 379 { 380 NeXTPC *s = NEXT_PC(opaque); 381 382 switch (size) { 383 case 1: 384 mmio_writeb(s, addr, value); 385 break; 386 case 2: 387 mmio_writew(s, addr, value); 388 break; 389 case 4: 390 mmio_writel(s, addr, value); 391 break; 392 default: 393 g_assert_not_reached(); 394 } 395 } 396 397 static const MemoryRegionOps mmio_ops = { 398 .read = mmio_readfn, 399 .write = mmio_writefn, 400 .valid.min_access_size = 1, 401 .valid.max_access_size = 4, 402 .endianness = DEVICE_NATIVE_ENDIAN, 403 }; 404 405 static uint32_t scr_readb(NeXTPC *s, hwaddr addr) 406 { 407 switch (addr) { 408 case 0x14108: 409 DPRINTF("FD read @ %x\n", (unsigned int)addr); 410 return 0x40 | 0x04 | 0x2 | 0x1; 411 case 0x14020: 412 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 413 return s->scsi_csr_1; 414 415 case 0x14021: 416 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 417 return 0x40; 418 419 /* 420 * These 4 registers are the hardware timer, not sure which register 421 * is the latch instead of data, but no problems so far 422 */ 423 case 0x1a000: 424 return 0xff & (clock() >> 24); 425 case 0x1a001: 426 return 0xff & (clock() >> 16); 427 case 0x1a002: 428 return 0xff & (clock() >> 8); 429 case 0x1a003: 430 /* Hack: We need to have this change consistently to make it work */ 431 return 0xFF & clock(); 432 433 default: 434 DPRINTF("BMAP Read B @ %x\n", (unsigned int)addr); 435 return 0; 436 } 437 } 438 439 static uint32_t scr_readw(NeXTPC *s, hwaddr addr) 440 { 441 DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr); 442 return 0; 443 } 444 445 static uint32_t scr_readl(NeXTPC *s, hwaddr addr) 446 { 447 DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr); 448 return 0; 449 } 450 451 #define SCSICSR_ENABLE 0x01 452 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 453 #define SCSICSR_FIFOFL 0x04 454 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 455 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 456 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 457 458 static void scr_writeb(NeXTPC *s, hwaddr addr, uint32_t value) 459 { 460 switch (addr) { 461 case 0x14108: 462 DPRINTF("FDCSR Write: %x\n", value); 463 464 if (value == 0x0) { 465 /* qemu_irq_raise(s->fd_irq[0]); */ 466 } 467 break; 468 case 0x14020: /* SCSI Control Register */ 469 if (value & SCSICSR_FIFOFL) { 470 DPRINTF("SCSICSR FIFO Flush\n"); 471 /* will have to add another irq to the esp if this is needed */ 472 /* esp_puflush_fifo(esp_g); */ 473 /* qemu_irq_pulse(s->scsi_dma); */ 474 } 475 476 if (value & SCSICSR_ENABLE) { 477 DPRINTF("SCSICSR Enable\n"); 478 /* 479 * qemu_irq_raise(s->scsi_dma); 480 * s->scsi_csr_1 = 0xc0; 481 * s->scsi_csr_1 |= 0x1; 482 * qemu_irq_pulse(s->scsi_dma); 483 */ 484 } 485 /* 486 * else 487 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 488 */ 489 490 if (value & SCSICSR_RESET) { 491 DPRINTF("SCSICSR Reset\n"); 492 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 493 /* qemu_irq_raise(s->scsi_reset); */ 494 /* s->scsi_csr_1 &= ~(SCSICSR_INTMASK |0x80|0x1); */ 495 496 } 497 if (value & SCSICSR_DMADIR) { 498 DPRINTF("SCSICSR DMAdir\n"); 499 } 500 if (value & SCSICSR_CPUDMA) { 501 DPRINTF("SCSICSR CPUDMA\n"); 502 /* qemu_irq_raise(s->scsi_dma); */ 503 504 s->int_status |= 0x4000000; 505 } else { 506 s->int_status &= ~(0x4000000); 507 } 508 if (value & SCSICSR_INTMASK) { 509 DPRINTF("SCSICSR INTMASK\n"); 510 /* 511 * int_mask &= ~0x1000; 512 * s->scsi_csr_1 |= value; 513 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 514 * if (s->scsi_queued) { 515 * s->scsi_queued = 0; 516 * next_irq(s, NEXT_SCSI_I, level); 517 * } 518 */ 519 } else { 520 /* int_mask |= 0x1000; */ 521 } 522 if (value & 0x80) { 523 /* int_mask |= 0x1000; */ 524 /* s->scsi_csr_1 |= 0x80; */ 525 } 526 DPRINTF("SCSICSR Write: %x\n", value); 527 /* s->scsi_csr_1 = value; */ 528 return; 529 /* Hardware timer latch - not implemented yet */ 530 case 0x1a000: 531 default: 532 DPRINTF("BMAP Write B @ %x with %x\n", (unsigned int)addr, value); 533 } 534 } 535 536 static void scr_writew(NeXTPC *s, hwaddr addr, uint32_t value) 537 { 538 DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value); 539 } 540 541 static void scr_writel(NeXTPC *s, hwaddr addr, uint32_t value) 542 { 543 DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value); 544 } 545 546 static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size) 547 { 548 NeXTPC *s = NEXT_PC(opaque); 549 550 switch (size) { 551 case 1: 552 return scr_readb(s, addr); 553 case 2: 554 return scr_readw(s, addr); 555 case 4: 556 return scr_readl(s, addr); 557 default: 558 g_assert_not_reached(); 559 } 560 } 561 562 static void scr_writefn(void *opaque, hwaddr addr, uint64_t value, 563 unsigned size) 564 { 565 NeXTPC *s = NEXT_PC(opaque); 566 567 switch (size) { 568 case 1: 569 scr_writeb(s, addr, value); 570 break; 571 case 2: 572 scr_writew(s, addr, value); 573 break; 574 case 4: 575 scr_writel(s, addr, value); 576 break; 577 default: 578 g_assert_not_reached(); 579 } 580 } 581 582 static const MemoryRegionOps scr_ops = { 583 .read = scr_readfn, 584 .write = scr_writefn, 585 .valid.min_access_size = 1, 586 .valid.max_access_size = 4, 587 .endianness = DEVICE_NATIVE_ENDIAN, 588 }; 589 590 #define NEXTDMA_SCSI(x) (0x10 + x) 591 #define NEXTDMA_FD(x) (0x10 + x) 592 #define NEXTDMA_ENTX(x) (0x110 + x) 593 #define NEXTDMA_ENRX(x) (0x150 + x) 594 #define NEXTDMA_CSR 0x0 595 #define NEXTDMA_NEXT 0x4000 596 #define NEXTDMA_LIMIT 0x4004 597 #define NEXTDMA_START 0x4008 598 #define NEXTDMA_STOP 0x400c 599 #define NEXTDMA_NEXT_INIT 0x4200 600 #define NEXTDMA_SIZE 0x4204 601 602 static void dma_writel(void *opaque, hwaddr addr, uint64_t value, 603 unsigned int size) 604 { 605 NeXTState *next_state = NEXT_MACHINE(opaque); 606 607 switch (addr) { 608 case NEXTDMA_ENRX(NEXTDMA_CSR): 609 if (value & DMA_DEV2M) { 610 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 611 } 612 613 if (value & DMA_SETENABLE) { 614 /* DPRINTF("SCSI DMA ENABLE\n"); */ 615 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 616 } 617 if (value & DMA_SETSUPDATE) { 618 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 619 } 620 if (value & DMA_CLRCOMPLETE) { 621 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 622 } 623 624 if (value & DMA_RESET) { 625 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 626 DMA_ENABLE | DMA_DEV2M); 627 } 628 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 629 break; 630 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 631 next_state->dma[NEXTDMA_ENRX].next_initbuf = value; 632 break; 633 case NEXTDMA_ENRX(NEXTDMA_NEXT): 634 next_state->dma[NEXTDMA_ENRX].next = value; 635 break; 636 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 637 next_state->dma[NEXTDMA_ENRX].limit = value; 638 break; 639 case NEXTDMA_SCSI(NEXTDMA_CSR): 640 if (value & DMA_DEV2M) { 641 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 642 } 643 if (value & DMA_SETENABLE) { 644 /* DPRINTF("SCSI DMA ENABLE\n"); */ 645 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 646 } 647 if (value & DMA_SETSUPDATE) { 648 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 649 } 650 if (value & DMA_CLRCOMPLETE) { 651 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 652 } 653 654 if (value & DMA_RESET) { 655 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 656 DMA_ENABLE | DMA_DEV2M); 657 /* DPRINTF("SCSI DMA RESET\n"); */ 658 } 659 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 660 break; 661 662 case NEXTDMA_SCSI(NEXTDMA_NEXT): 663 next_state->dma[NEXTDMA_SCSI].next = value; 664 break; 665 666 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 667 next_state->dma[NEXTDMA_SCSI].limit = value; 668 break; 669 670 case NEXTDMA_SCSI(NEXTDMA_START): 671 next_state->dma[NEXTDMA_SCSI].start = value; 672 break; 673 674 case NEXTDMA_SCSI(NEXTDMA_STOP): 675 next_state->dma[NEXTDMA_SCSI].stop = value; 676 break; 677 678 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 679 next_state->dma[NEXTDMA_SCSI].next_initbuf = value; 680 break; 681 682 default: 683 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)value); 684 } 685 } 686 687 static uint64_t dma_readl(void *opaque, hwaddr addr, unsigned int size) 688 { 689 NeXTState *next_state = NEXT_MACHINE(opaque); 690 691 switch (addr) { 692 case NEXTDMA_SCSI(NEXTDMA_CSR): 693 DPRINTF("SCSI DMA CSR READ\n"); 694 return next_state->dma[NEXTDMA_SCSI].csr; 695 case NEXTDMA_ENRX(NEXTDMA_CSR): 696 return next_state->dma[NEXTDMA_ENRX].csr; 697 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 698 return next_state->dma[NEXTDMA_ENRX].next_initbuf; 699 case NEXTDMA_ENRX(NEXTDMA_NEXT): 700 return next_state->dma[NEXTDMA_ENRX].next; 701 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 702 return next_state->dma[NEXTDMA_ENRX].limit; 703 704 case NEXTDMA_SCSI(NEXTDMA_NEXT): 705 return next_state->dma[NEXTDMA_SCSI].next; 706 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 707 return next_state->dma[NEXTDMA_SCSI].next_initbuf; 708 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 709 return next_state->dma[NEXTDMA_SCSI].limit; 710 case NEXTDMA_SCSI(NEXTDMA_START): 711 return next_state->dma[NEXTDMA_SCSI].start; 712 case NEXTDMA_SCSI(NEXTDMA_STOP): 713 return next_state->dma[NEXTDMA_SCSI].stop; 714 715 default: 716 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 717 return 0; 718 } 719 720 /* 721 * once the csr's are done, subtract 0x3FEC from the addr, and that will 722 * normalize the upper registers 723 */ 724 } 725 726 static const MemoryRegionOps dma_ops = { 727 .read = dma_readl, 728 .write = dma_writel, 729 .impl.min_access_size = 4, 730 .valid.min_access_size = 4, 731 .valid.max_access_size = 4, 732 .endianness = DEVICE_NATIVE_ENDIAN, 733 }; 734 735 static void next_irq(void *opaque, int number, int level) 736 { 737 NeXTPC *s = NEXT_PC(opaque); 738 M68kCPU *cpu = s->cpu; 739 int shift = 0; 740 741 /* first switch sets interupt status */ 742 /* DPRINTF("IRQ %i\n",number); */ 743 switch (number) { 744 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 745 case NEXT_FD_I: 746 shift = 7; 747 break; 748 case NEXT_KBD_I: 749 shift = 3; 750 break; 751 case NEXT_PWR_I: 752 shift = 2; 753 break; 754 case NEXT_ENRX_I: 755 shift = 9; 756 break; 757 case NEXT_ENTX_I: 758 shift = 10; 759 break; 760 case NEXT_SCSI_I: 761 shift = 12; 762 break; 763 case NEXT_CLK_I: 764 shift = 5; 765 break; 766 767 /* level 5 - scc (serial) */ 768 case NEXT_SCC_I: 769 shift = 17; 770 break; 771 772 /* level 6 - audio etherrx/tx dma */ 773 case NEXT_ENTX_DMA_I: 774 shift = 28; 775 break; 776 case NEXT_ENRX_DMA_I: 777 shift = 27; 778 break; 779 case NEXT_SCSI_DMA_I: 780 shift = 26; 781 break; 782 case NEXT_SND_I: 783 shift = 23; 784 break; 785 case NEXT_SCC_DMA_I: 786 shift = 21; 787 break; 788 789 } 790 /* 791 * this HAS to be wrong, the interrupt handlers in mach and together 792 * int_status and int_mask and return if there is a hit 793 */ 794 if (s->int_mask & (1 << shift)) { 795 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 796 /* return; */ 797 } 798 799 /* second switch triggers the correct interrupt */ 800 if (level) { 801 s->int_status |= 1 << shift; 802 803 switch (number) { 804 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 805 case NEXT_FD_I: 806 case NEXT_KBD_I: 807 case NEXT_PWR_I: 808 case NEXT_ENRX_I: 809 case NEXT_ENTX_I: 810 case NEXT_SCSI_I: 811 case NEXT_CLK_I: 812 m68k_set_irq_level(cpu, 3, 27); 813 break; 814 815 /* level 5 - scc (serial) */ 816 case NEXT_SCC_I: 817 m68k_set_irq_level(cpu, 5, 29); 818 break; 819 820 /* level 6 - audio etherrx/tx dma */ 821 case NEXT_ENTX_DMA_I: 822 case NEXT_ENRX_DMA_I: 823 case NEXT_SCSI_DMA_I: 824 case NEXT_SND_I: 825 case NEXT_SCC_DMA_I: 826 m68k_set_irq_level(cpu, 6, 30); 827 break; 828 } 829 } else { 830 s->int_status &= ~(1 << shift); 831 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 832 } 833 } 834 835 static void next_escc_init(DeviceState *pcdev) 836 { 837 DeviceState *dev; 838 SysBusDevice *s; 839 840 dev = qdev_new(TYPE_ESCC); 841 qdev_prop_set_uint32(dev, "disabled", 0); 842 qdev_prop_set_uint32(dev, "frequency", 9600 * 384); 843 qdev_prop_set_uint32(dev, "it_shift", 0); 844 qdev_prop_set_bit(dev, "bit_swap", true); 845 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 846 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 847 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 848 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 849 850 s = SYS_BUS_DEVICE(dev); 851 sysbus_realize_and_unref(s, &error_fatal); 852 sysbus_connect_irq(s, 0, qdev_get_gpio_in(pcdev, NEXT_SCC_I)); 853 sysbus_connect_irq(s, 1, qdev_get_gpio_in(pcdev, NEXT_SCC_DMA_I)); 854 sysbus_mmio_map(s, 0, 0x2118000); 855 } 856 857 static void next_pc_reset(DeviceState *dev) 858 { 859 NeXTPC *s = NEXT_PC(dev); 860 861 /* Set internal registers to initial values */ 862 /* 0x0000XX00 << vital bits */ 863 s->scr1 = 0x00011102; 864 s->scr2 = 0x00ff0c80; 865 866 s->rtc.status = 0x90; 867 868 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 869 memcpy(s->rtc.ram, rtc_ram2, 32); 870 } 871 872 static void next_pc_realize(DeviceState *dev, Error **errp) 873 { 874 NeXTPC *s = NEXT_PC(dev); 875 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 876 877 qdev_init_gpio_in(dev, next_irq, NEXT_NUM_IRQS); 878 879 memory_region_init_io(&s->mmiomem, OBJECT(s), &mmio_ops, s, 880 "next.mmio", 0xD0000); 881 memory_region_init_io(&s->scrmem, OBJECT(s), &scr_ops, s, 882 "next.scr", 0x20000); 883 sysbus_init_mmio(sbd, &s->mmiomem); 884 sysbus_init_mmio(sbd, &s->scrmem); 885 } 886 887 /* 888 * If the m68k CPU implemented its inbound irq lines as GPIO lines 889 * rather than via the m68k_set_irq_level() function we would not need 890 * this cpu link property and could instead provide outbound IRQ lines 891 * that the board could wire up to the CPU. 892 */ 893 static Property next_pc_properties[] = { 894 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 895 DEFINE_PROP_END_OF_LIST(), 896 }; 897 898 static void next_pc_class_init(ObjectClass *klass, void *data) 899 { 900 DeviceClass *dc = DEVICE_CLASS(klass); 901 902 dc->desc = "NeXT Peripheral Controller"; 903 dc->realize = next_pc_realize; 904 dc->reset = next_pc_reset; 905 device_class_set_props(dc, next_pc_properties); 906 /* We will add the VMState in a later commit */ 907 } 908 909 static const TypeInfo next_pc_info = { 910 .name = TYPE_NEXT_PC, 911 .parent = TYPE_SYS_BUS_DEVICE, 912 .instance_size = sizeof(NeXTPC), 913 .class_init = next_pc_class_init, 914 }; 915 916 static void next_cube_init(MachineState *machine) 917 { 918 M68kCPU *cpu; 919 CPUM68KState *env; 920 MemoryRegion *rom = g_new(MemoryRegion, 1); 921 MemoryRegion *dmamem = g_new(MemoryRegion, 1); 922 MemoryRegion *bmapm1 = g_new(MemoryRegion, 1); 923 MemoryRegion *bmapm2 = g_new(MemoryRegion, 1); 924 MemoryRegion *sysmem = get_system_memory(); 925 const char *bios_name = machine->firmware ?: ROM_FILE; 926 DeviceState *dev; 927 DeviceState *pcdev; 928 929 /* Initialize the cpu core */ 930 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 931 if (!cpu) { 932 error_report("Unable to find m68k CPU definition"); 933 exit(1); 934 } 935 env = &cpu->env; 936 937 /* Initialize CPU registers. */ 938 env->vbr = 0; 939 env->sr = 0x2700; 940 941 /* Peripheral Controller */ 942 pcdev = qdev_new(TYPE_NEXT_PC); 943 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 944 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 945 946 /* 64MB RAM starting at 0x04000000 */ 947 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 948 949 /* Framebuffer */ 950 dev = qdev_new(TYPE_NEXTFB); 951 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 952 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000); 953 954 /* MMIO */ 955 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000); 956 957 /* BMAP IO - acts as a catch-all for now */ 958 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 959 960 /* BMAP memory */ 961 memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64, 962 true, &error_fatal); 963 memory_region_add_subregion(sysmem, 0x020c0000, bmapm1); 964 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 965 memory_region_init_alias(bmapm2, NULL, "next.bmapmem2", bmapm1, 0x0, 64); 966 memory_region_add_subregion(sysmem, 0x820c0000, bmapm2); 967 968 /* KBD */ 969 dev = qdev_new(TYPE_NEXTKBD); 970 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 971 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000); 972 973 /* Load ROM here */ 974 /* still not sure if the rom should also be mapped at 0x0*/ 975 memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal); 976 memory_region_add_subregion(sysmem, 0x01000000, rom); 977 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 978 if (!qtest_enabled()) { 979 error_report("Failed to load firmware '%s'.", bios_name); 980 } 981 } else { 982 uint8_t *ptr; 983 /* Initial PC is always at offset 4 in firmware binaries */ 984 ptr = rom_ptr(0x01000004, 4); 985 g_assert(ptr != NULL); 986 env->pc = ldl_p(ptr); 987 if (env->pc >= 0x01020000) { 988 error_report("'%s' does not seem to be a valid firmware image.", 989 bios_name); 990 exit(1); 991 } 992 } 993 994 /* Serial */ 995 next_escc_init(pcdev); 996 997 /* TODO: */ 998 /* Network */ 999 /* SCSI */ 1000 1001 /* DMA */ 1002 memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5000); 1003 memory_region_add_subregion(sysmem, 0x02000000, dmamem); 1004 } 1005 1006 static void next_machine_class_init(ObjectClass *oc, void *data) 1007 { 1008 MachineClass *mc = MACHINE_CLASS(oc); 1009 1010 mc->desc = "NeXT Cube"; 1011 mc->init = next_cube_init; 1012 mc->default_ram_size = RAM_SIZE; 1013 mc->default_ram_id = "next.ram"; 1014 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1015 } 1016 1017 static const TypeInfo next_typeinfo = { 1018 .name = TYPE_NEXT_MACHINE, 1019 .parent = TYPE_MACHINE, 1020 .class_init = next_machine_class_init, 1021 .instance_size = sizeof(NeXTState), 1022 }; 1023 1024 static void next_register_type(void) 1025 { 1026 type_register_static(&next_typeinfo); 1027 type_register_static(&next_pc_info); 1028 } 1029 1030 type_init(next_register_type) 1031