1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "exec/address-spaces.h" 15 #include "sysemu/sysemu.h" 16 #include "sysemu/qtest.h" 17 #include "hw/hw.h" 18 #include "hw/m68k/next-cube.h" 19 #include "hw/boards.h" 20 #include "hw/loader.h" 21 #include "hw/scsi/esp.h" 22 #include "hw/sysbus.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "qapi/error.h" 26 #include "ui/console.h" 27 #include "target/m68k/cpu.h" 28 29 /* #define DEBUG_NEXT */ 30 #ifdef DEBUG_NEXT 31 #define DPRINTF(fmt, ...) \ 32 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 33 #else 34 #define DPRINTF(fmt, ...) do { } while (0) 35 #endif 36 37 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 38 #define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE) 39 40 #define ENTRY 0x0100001e 41 #define RAM_SIZE 0x4000000 42 #define ROM_FILE "Rev_2.5_v66.bin" 43 44 typedef struct next_dma { 45 uint32_t csr; 46 47 uint32_t saved_next; 48 uint32_t saved_limit; 49 uint32_t saved_start; 50 uint32_t saved_stop; 51 52 uint32_t next; 53 uint32_t limit; 54 uint32_t start; 55 uint32_t stop; 56 57 uint32_t next_initbuf; 58 uint32_t size; 59 } next_dma; 60 61 typedef struct { 62 MachineState parent; 63 64 uint32_t int_mask; 65 uint32_t int_status; 66 67 uint8_t scsi_csr_1; 68 uint8_t scsi_csr_2; 69 next_dma dma[10]; 70 qemu_irq *scsi_irq; 71 qemu_irq scsi_dma; 72 qemu_irq scsi_reset; 73 qemu_irq *fd_irq; 74 75 uint32_t scr1; 76 uint32_t scr2; 77 78 uint8_t rtc_ram[32]; 79 } NeXTState; 80 81 /* Thanks to NeXT forums for this */ 82 /* 83 static const uint8_t rtc_ram3[32] = { 84 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 85 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 86 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 87 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 88 }; 89 */ 90 static const uint8_t rtc_ram2[32] = { 91 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 92 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 93 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 94 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 95 }; 96 97 #define SCR2_RTCLK 0x2 98 #define SCR2_RTDATA 0x4 99 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 100 101 static void nextscr2_write(NeXTState *s, uint32_t val, int size) 102 { 103 static int led; 104 static int phase; 105 static uint8_t old_scr2; 106 static uint8_t rtc_command; 107 static uint8_t rtc_value; 108 static uint8_t rtc_status = 0x90; 109 static uint8_t rtc_return; 110 uint8_t scr2_2; 111 112 if (size == 4) { 113 scr2_2 = (val >> 8) & 0xFF; 114 } else { 115 scr2_2 = val & 0xFF; 116 } 117 118 if (val & 0x1) { 119 DPRINTF("fault!\n"); 120 led++; 121 if (led == 10) { 122 DPRINTF("LED flashing, possible fault!\n"); 123 led = 0; 124 } 125 } 126 127 if (scr2_2 & 0x1) { 128 /* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */ 129 if (phase == -1) { 130 phase = 0; 131 } 132 /* If we are in going down clock... do something */ 133 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 134 ((scr2_2 & SCR2_RTCLK) == 0)) { 135 if (phase < 8) { 136 rtc_command = (rtc_command << 1) | 137 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 138 } 139 if (phase >= 8 && phase < 16) { 140 rtc_value = (rtc_value << 1) | ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 141 142 /* if we read RAM register, output RT_DATA bit */ 143 if (rtc_command <= 0x1F) { 144 scr2_2 = scr2_2 & (~SCR2_RTDATA); 145 if (s->rtc_ram[rtc_command] & (0x80 >> (phase - 8))) { 146 scr2_2 |= SCR2_RTDATA; 147 } 148 149 rtc_return = (rtc_return << 1) | 150 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 151 } 152 /* read the status 0x30 */ 153 if (rtc_command == 0x30) { 154 scr2_2 = scr2_2 & (~SCR2_RTDATA); 155 /* for now status = 0x98 (new rtc + FTU) */ 156 if (rtc_status & (0x80 >> (phase - 8))) { 157 scr2_2 |= SCR2_RTDATA; 158 } 159 160 rtc_return = (rtc_return << 1) | 161 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 162 } 163 /* read the status 0x31 */ 164 if (rtc_command == 0x31) { 165 scr2_2 = scr2_2 & (~SCR2_RTDATA); 166 /* for now 0x00 */ 167 if (0x00 & (0x80 >> (phase - 8))) { 168 scr2_2 |= SCR2_RTDATA; 169 } 170 rtc_return = (rtc_return << 1) | 171 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 172 } 173 174 if ((rtc_command >= 0x20) && (rtc_command <= 0x2F)) { 175 scr2_2 = scr2_2 & (~SCR2_RTDATA); 176 /* for now 0x00 */ 177 time_t time_h = time(NULL); 178 struct tm *info = localtime(&time_h); 179 int ret = 0; 180 181 switch (rtc_command) { 182 case 0x20: 183 ret = SCR2_TOBCD(info->tm_sec); 184 break; 185 case 0x21: 186 ret = SCR2_TOBCD(info->tm_min); 187 break; 188 case 0x22: 189 ret = SCR2_TOBCD(info->tm_hour); 190 break; 191 case 0x24: 192 ret = SCR2_TOBCD(info->tm_mday); 193 break; 194 case 0x25: 195 ret = SCR2_TOBCD((info->tm_mon + 1)); 196 break; 197 case 0x26: 198 ret = SCR2_TOBCD((info->tm_year - 100)); 199 break; 200 201 } 202 203 if (ret & (0x80 >> (phase - 8))) { 204 scr2_2 |= SCR2_RTDATA; 205 } 206 rtc_return = (rtc_return << 1) | 207 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 208 } 209 210 } 211 212 phase++; 213 if (phase == 16) { 214 if (rtc_command >= 0x80 && rtc_command <= 0x9F) { 215 s->rtc_ram[rtc_command - 0x80] = rtc_value; 216 } 217 /* write to x30 register */ 218 if (rtc_command == 0xB1) { 219 /* clear FTU */ 220 if (rtc_value & 0x04) { 221 rtc_status = rtc_status & (~0x18); 222 s->int_status = s->int_status & (~0x04); 223 } 224 } 225 } 226 } 227 } else { 228 /* else end or abort */ 229 phase = -1; 230 rtc_command = 0; 231 rtc_value = 0; 232 } 233 s->scr2 = val & 0xFFFF00FF; 234 s->scr2 |= scr2_2 << 8; 235 old_scr2 = scr2_2; 236 } 237 238 static uint32_t mmio_readb(NeXTState *s, hwaddr addr) 239 { 240 switch (addr) { 241 case 0xc000: 242 return (s->scr1 >> 24) & 0xFF; 243 case 0xc001: 244 return (s->scr1 >> 16) & 0xFF; 245 case 0xc002: 246 return (s->scr1 >> 8) & 0xFF; 247 case 0xc003: 248 return (s->scr1 >> 0) & 0xFF; 249 250 case 0xd000: 251 return (s->scr2 >> 24) & 0xFF; 252 case 0xd001: 253 return (s->scr2 >> 16) & 0xFF; 254 case 0xd002: 255 return (s->scr2 >> 8) & 0xFF; 256 case 0xd003: 257 return (s->scr2 >> 0) & 0xFF; 258 case 0x14020: 259 DPRINTF("MMIO Read 0x4020\n"); 260 return 0x7f; 261 262 default: 263 DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr); 264 return 0x0; 265 } 266 } 267 268 static uint32_t mmio_readw(NeXTState *s, hwaddr addr) 269 { 270 switch (addr) { 271 default: 272 DPRINTF("MMIO Read W @ %"HWADDR_PRIx"\n", addr); 273 return 0x0; 274 } 275 } 276 277 static uint32_t mmio_readl(NeXTState *s, hwaddr addr) 278 { 279 switch (addr) { 280 case 0x7000: 281 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 282 return s->int_status; 283 284 case 0x7800: 285 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 286 return s->int_mask; 287 288 case 0xc000: 289 return s->scr1; 290 291 case 0xd000: 292 return s->scr2; 293 294 default: 295 DPRINTF("MMIO Read L @ %"HWADDR_PRIx"\n", addr); 296 return 0x0; 297 } 298 } 299 300 static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val) 301 { 302 switch (addr) { 303 case 0xd003: 304 nextscr2_write(s, val, 1); 305 break; 306 default: 307 DPRINTF("MMIO Write B @ %x with %x\n", (unsigned int)addr, val); 308 } 309 310 } 311 312 static void mmio_writew(NeXTState *s, hwaddr addr, uint32_t val) 313 { 314 DPRINTF("MMIO Write W\n"); 315 } 316 317 static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val) 318 { 319 switch (addr) { 320 case 0x7000: 321 DPRINTF("INT Status old: %x new: %x\n", s->int_status, val); 322 s->int_status = val; 323 break; 324 case 0x7800: 325 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val); 326 s->int_mask = val; 327 break; 328 case 0xc000: 329 DPRINTF("SCR1 Write: %x\n", val); 330 break; 331 case 0xd000: 332 nextscr2_write(s, val, 4); 333 break; 334 335 default: 336 DPRINTF("MMIO Write l @ %x with %x\n", (unsigned int)addr, val); 337 } 338 } 339 340 static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size) 341 { 342 NeXTState *ns = NEXT_MACHINE(opaque); 343 344 switch (size) { 345 case 1: 346 return mmio_readb(ns, addr); 347 case 2: 348 return mmio_readw(ns, addr); 349 case 4: 350 return mmio_readl(ns, addr); 351 default: 352 g_assert_not_reached(); 353 } 354 } 355 356 static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value, 357 unsigned size) 358 { 359 NeXTState *ns = NEXT_MACHINE(opaque); 360 361 switch (size) { 362 case 1: 363 mmio_writeb(ns, addr, value); 364 break; 365 case 2: 366 mmio_writew(ns, addr, value); 367 break; 368 case 4: 369 mmio_writel(ns, addr, value); 370 break; 371 default: 372 g_assert_not_reached(); 373 } 374 } 375 376 static const MemoryRegionOps mmio_ops = { 377 .read = mmio_readfn, 378 .write = mmio_writefn, 379 .valid.min_access_size = 1, 380 .valid.max_access_size = 4, 381 .endianness = DEVICE_NATIVE_ENDIAN, 382 }; 383 384 static uint32_t scr_readb(NeXTState *s, hwaddr addr) 385 { 386 switch (addr) { 387 case 0x14108: 388 DPRINTF("FD read @ %x\n", (unsigned int)addr); 389 return 0x40 | 0x04 | 0x2 | 0x1; 390 case 0x14020: 391 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 392 return s->scsi_csr_1; 393 394 case 0x14021: 395 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 396 return 0x40; 397 398 /* 399 * These 4 registers are the hardware timer, not sure which register 400 * is the latch instead of data, but no problems so far 401 */ 402 case 0x1a000: 403 return 0xff & (clock() >> 24); 404 case 0x1a001: 405 return 0xff & (clock() >> 16); 406 case 0x1a002: 407 return 0xff & (clock() >> 8); 408 case 0x1a003: 409 /* Hack: We need to have this change consistently to make it work */ 410 return 0xFF & clock(); 411 412 default: 413 DPRINTF("BMAP Read B @ %x\n", (unsigned int)addr); 414 return 0; 415 } 416 } 417 418 static uint32_t scr_readw(NeXTState *s, hwaddr addr) 419 { 420 DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr); 421 return 0; 422 } 423 424 static uint32_t scr_readl(NeXTState *s, hwaddr addr) 425 { 426 DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr); 427 return 0; 428 } 429 430 #define SCSICSR_ENABLE 0x01 431 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 432 #define SCSICSR_FIFOFL 0x04 433 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 434 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 435 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 436 437 static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value) 438 { 439 switch (addr) { 440 case 0x14108: 441 DPRINTF("FDCSR Write: %x\n", value); 442 443 if (value == 0x0) { 444 /* qemu_irq_raise(s->fd_irq[0]); */ 445 } 446 break; 447 case 0x14020: /* SCSI Control Register */ 448 if (value & SCSICSR_FIFOFL) { 449 DPRINTF("SCSICSR FIFO Flush\n"); 450 /* will have to add another irq to the esp if this is needed */ 451 /* esp_puflush_fifo(esp_g); */ 452 /* qemu_irq_pulse(s->scsi_dma); */ 453 } 454 455 if (value & SCSICSR_ENABLE) { 456 DPRINTF("SCSICSR Enable\n"); 457 /* 458 * qemu_irq_raise(s->scsi_dma); 459 * s->scsi_csr_1 = 0xc0; 460 * s->scsi_csr_1 |= 0x1; 461 * qemu_irq_pulse(s->scsi_dma); 462 */ 463 } 464 /* 465 * else 466 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 467 */ 468 469 if (value & SCSICSR_RESET) { 470 DPRINTF("SCSICSR Reset\n"); 471 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 472 /* qemu_irq_raise(s->scsi_reset); */ 473 /* s->scsi_csr_1 &= ~(SCSICSR_INTMASK |0x80|0x1); */ 474 475 } 476 if (value & SCSICSR_DMADIR) { 477 DPRINTF("SCSICSR DMAdir\n"); 478 } 479 if (value & SCSICSR_CPUDMA) { 480 DPRINTF("SCSICSR CPUDMA\n"); 481 /* qemu_irq_raise(s->scsi_dma); */ 482 483 s->int_status |= 0x4000000; 484 } else { 485 s->int_status &= ~(0x4000000); 486 } 487 if (value & SCSICSR_INTMASK) { 488 DPRINTF("SCSICSR INTMASK\n"); 489 /* 490 * int_mask &= ~0x1000; 491 * s->scsi_csr_1 |= value; 492 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 493 * if (s->scsi_queued) { 494 * s->scsi_queued = 0; 495 * next_irq(s, NEXT_SCSI_I, level); 496 * } 497 */ 498 } else { 499 /* int_mask |= 0x1000; */ 500 } 501 if (value & 0x80) { 502 /* int_mask |= 0x1000; */ 503 /* s->scsi_csr_1 |= 0x80; */ 504 } 505 DPRINTF("SCSICSR Write: %x\n", value); 506 /* s->scsi_csr_1 = value; */ 507 return; 508 /* Hardware timer latch - not implemented yet */ 509 case 0x1a000: 510 default: 511 DPRINTF("BMAP Write B @ %x with %x\n", (unsigned int)addr, value); 512 } 513 } 514 515 static void scr_writew(NeXTState *s, hwaddr addr, uint32_t value) 516 { 517 DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value); 518 } 519 520 static void scr_writel(NeXTState *s, hwaddr addr, uint32_t value) 521 { 522 DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value); 523 } 524 525 static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size) 526 { 527 NeXTState *ns = NEXT_MACHINE(opaque); 528 529 switch (size) { 530 case 1: 531 return scr_readb(ns, addr); 532 case 2: 533 return scr_readw(ns, addr); 534 case 4: 535 return scr_readl(ns, addr); 536 default: 537 g_assert_not_reached(); 538 } 539 } 540 541 static void scr_writefn(void *opaque, hwaddr addr, uint64_t value, 542 unsigned size) 543 { 544 NeXTState *ns = NEXT_MACHINE(opaque); 545 546 switch (size) { 547 case 1: 548 scr_writeb(ns, addr, value); 549 break; 550 case 2: 551 scr_writew(ns, addr, value); 552 break; 553 case 4: 554 scr_writel(ns, addr, value); 555 break; 556 default: 557 g_assert_not_reached(); 558 } 559 } 560 561 static const MemoryRegionOps scr_ops = { 562 .read = scr_readfn, 563 .write = scr_writefn, 564 .valid.min_access_size = 1, 565 .valid.max_access_size = 4, 566 .endianness = DEVICE_NATIVE_ENDIAN, 567 }; 568 569 #define NEXTDMA_SCSI(x) (0x10 + x) 570 #define NEXTDMA_FD(x) (0x10 + x) 571 #define NEXTDMA_ENTX(x) (0x110 + x) 572 #define NEXTDMA_ENRX(x) (0x150 + x) 573 #define NEXTDMA_CSR 0x0 574 #define NEXTDMA_NEXT 0x4000 575 #define NEXTDMA_LIMIT 0x4004 576 #define NEXTDMA_START 0x4008 577 #define NEXTDMA_STOP 0x400c 578 #define NEXTDMA_NEXT_INIT 0x4200 579 #define NEXTDMA_SIZE 0x4204 580 581 static void dma_writel(void *opaque, hwaddr addr, uint64_t value, 582 unsigned int size) 583 { 584 NeXTState *next_state = NEXT_MACHINE(opaque); 585 586 switch (addr) { 587 case NEXTDMA_ENRX(NEXTDMA_CSR): 588 if (value & DMA_DEV2M) { 589 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 590 } 591 592 if (value & DMA_SETENABLE) { 593 /* DPRINTF("SCSI DMA ENABLE\n"); */ 594 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 595 } 596 if (value & DMA_SETSUPDATE) { 597 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 598 } 599 if (value & DMA_CLRCOMPLETE) { 600 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 601 } 602 603 if (value & DMA_RESET) { 604 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 605 DMA_ENABLE | DMA_DEV2M); 606 } 607 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 608 break; 609 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 610 next_state->dma[NEXTDMA_ENRX].next_initbuf = value; 611 break; 612 case NEXTDMA_ENRX(NEXTDMA_NEXT): 613 next_state->dma[NEXTDMA_ENRX].next = value; 614 break; 615 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 616 next_state->dma[NEXTDMA_ENRX].limit = value; 617 break; 618 case NEXTDMA_SCSI(NEXTDMA_CSR): 619 if (value & DMA_DEV2M) { 620 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 621 } 622 if (value & DMA_SETENABLE) { 623 /* DPRINTF("SCSI DMA ENABLE\n"); */ 624 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 625 } 626 if (value & DMA_SETSUPDATE) { 627 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 628 } 629 if (value & DMA_CLRCOMPLETE) { 630 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 631 } 632 633 if (value & DMA_RESET) { 634 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 635 DMA_ENABLE | DMA_DEV2M); 636 /* DPRINTF("SCSI DMA RESET\n"); */ 637 } 638 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 639 break; 640 641 case NEXTDMA_SCSI(NEXTDMA_NEXT): 642 next_state->dma[NEXTDMA_SCSI].next = value; 643 break; 644 645 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 646 next_state->dma[NEXTDMA_SCSI].limit = value; 647 break; 648 649 case NEXTDMA_SCSI(NEXTDMA_START): 650 next_state->dma[NEXTDMA_SCSI].start = value; 651 break; 652 653 case NEXTDMA_SCSI(NEXTDMA_STOP): 654 next_state->dma[NEXTDMA_SCSI].stop = value; 655 break; 656 657 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 658 next_state->dma[NEXTDMA_SCSI].next_initbuf = value; 659 break; 660 661 default: 662 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)value); 663 } 664 } 665 666 static uint64_t dma_readl(void *opaque, hwaddr addr, unsigned int size) 667 { 668 NeXTState *next_state = NEXT_MACHINE(opaque); 669 670 switch (addr) { 671 case NEXTDMA_SCSI(NEXTDMA_CSR): 672 DPRINTF("SCSI DMA CSR READ\n"); 673 return next_state->dma[NEXTDMA_SCSI].csr; 674 case NEXTDMA_ENRX(NEXTDMA_CSR): 675 return next_state->dma[NEXTDMA_ENRX].csr; 676 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 677 return next_state->dma[NEXTDMA_ENRX].next_initbuf; 678 case NEXTDMA_ENRX(NEXTDMA_NEXT): 679 return next_state->dma[NEXTDMA_ENRX].next; 680 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 681 return next_state->dma[NEXTDMA_ENRX].limit; 682 683 case NEXTDMA_SCSI(NEXTDMA_NEXT): 684 return next_state->dma[NEXTDMA_SCSI].next; 685 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 686 return next_state->dma[NEXTDMA_SCSI].next_initbuf; 687 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 688 return next_state->dma[NEXTDMA_SCSI].limit; 689 case NEXTDMA_SCSI(NEXTDMA_START): 690 return next_state->dma[NEXTDMA_SCSI].start; 691 case NEXTDMA_SCSI(NEXTDMA_STOP): 692 return next_state->dma[NEXTDMA_SCSI].stop; 693 694 default: 695 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 696 return 0; 697 } 698 699 /* 700 * once the csr's are done, subtract 0x3FEC from the addr, and that will 701 * normalize the upper registers 702 */ 703 } 704 705 static const MemoryRegionOps dma_ops = { 706 .read = dma_readl, 707 .write = dma_writel, 708 .impl.min_access_size = 4, 709 .valid.min_access_size = 4, 710 .valid.max_access_size = 4, 711 .endianness = DEVICE_NATIVE_ENDIAN, 712 }; 713 714 /* 715 * TODO: set the shift numbers as values in the enum, so the first switch 716 * will not be needed 717 */ 718 void next_irq(void *opaque, int number, int level) 719 { 720 M68kCPU *cpu = opaque; 721 int shift = 0; 722 NeXTState *ns = NEXT_MACHINE(qdev_get_machine()); 723 724 /* first switch sets interupt status */ 725 /* DPRINTF("IRQ %i\n",number); */ 726 switch (number) { 727 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 728 case NEXT_FD_I: 729 shift = 7;; 730 break; 731 case NEXT_KBD_I: 732 shift = 3; 733 break; 734 case NEXT_PWR_I: 735 shift = 2; 736 break; 737 case NEXT_ENRX_I: 738 shift = 9; 739 break; 740 case NEXT_ENTX_I: 741 shift = 10; 742 break; 743 case NEXT_SCSI_I: 744 shift = 12; 745 break; 746 case NEXT_CLK_I: 747 shift = 5; 748 break; 749 750 /* level 5 - scc (serial) */ 751 case NEXT_SCC_I: 752 shift = 17; 753 break; 754 755 /* level 6 - audio etherrx/tx dma */ 756 case NEXT_ENTX_DMA_I: 757 shift = 28; 758 break; 759 case NEXT_ENRX_DMA_I: 760 shift = 27; 761 break; 762 case NEXT_SCSI_DMA_I: 763 shift = 26; 764 break; 765 case NEXT_SND_I: 766 shift = 23; 767 break; 768 case NEXT_SCC_DMA_I: 769 shift = 21; 770 break; 771 772 } 773 /* 774 * this HAS to be wrong, the interrupt handlers in mach and together 775 * int_status and int_mask and return if there is a hit 776 */ 777 if (ns->int_mask & (1 << shift)) { 778 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 779 /* return; */ 780 } 781 782 /* second switch triggers the correct interrupt */ 783 if (level) { 784 ns->int_status |= 1 << shift; 785 786 switch (number) { 787 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 788 case NEXT_FD_I: 789 case NEXT_KBD_I: 790 case NEXT_PWR_I: 791 case NEXT_ENRX_I: 792 case NEXT_ENTX_I: 793 case NEXT_SCSI_I: 794 case NEXT_CLK_I: 795 m68k_set_irq_level(cpu, 3, 27); 796 break; 797 798 /* level 5 - scc (serial) */ 799 case NEXT_SCC_I: 800 m68k_set_irq_level(cpu, 5, 29); 801 break; 802 803 /* level 6 - audio etherrx/tx dma */ 804 case NEXT_ENTX_DMA_I: 805 case NEXT_ENRX_DMA_I: 806 case NEXT_SCSI_DMA_I: 807 case NEXT_SND_I: 808 case NEXT_SCC_DMA_I: 809 m68k_set_irq_level(cpu, 6, 30); 810 break; 811 } 812 } else { 813 ns->int_status &= ~(1 << shift); 814 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 815 } 816 } 817 818 static void next_cube_init(MachineState *machine) 819 { 820 M68kCPU *cpu; 821 CPUM68KState *env; 822 MemoryRegion *ram = g_new(MemoryRegion, 1); 823 MemoryRegion *rom = g_new(MemoryRegion, 1); 824 MemoryRegion *mmiomem = g_new(MemoryRegion, 1); 825 MemoryRegion *scrmem = g_new(MemoryRegion, 1); 826 MemoryRegion *dmamem = g_new(MemoryRegion, 1); 827 MemoryRegion *bmapm1 = g_new(MemoryRegion, 1); 828 MemoryRegion *bmapm2 = g_new(MemoryRegion, 1); 829 MemoryRegion *sysmem = get_system_memory(); 830 NeXTState *ns = NEXT_MACHINE(machine); 831 DeviceState *dev; 832 833 /* Initialize the cpu core */ 834 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 835 if (!cpu) { 836 error_report("Unable to find m68k CPU definition"); 837 exit(1); 838 } 839 env = &cpu->env; 840 841 /* Initialize CPU registers. */ 842 env->vbr = 0; 843 env->sr = 0x2700; 844 845 /* Set internal registers to initial values */ 846 /* 0x0000XX00 << vital bits */ 847 ns->scr1 = 0x00011102; 848 ns->scr2 = 0x00ff0c80; 849 850 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 851 memcpy(ns->rtc_ram, rtc_ram2, 32); 852 853 /* 64MB RAM starting at 0x04000000 */ 854 memory_region_allocate_system_memory(ram, NULL, "next.ram", ram_size); 855 memory_region_add_subregion(sysmem, 0x04000000, ram); 856 857 /* Framebuffer */ 858 dev = qdev_create(NULL, TYPE_NEXTFB); 859 qdev_init_nofail(dev); 860 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000); 861 862 /* MMIO */ 863 memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio", 864 0xD0000); 865 memory_region_add_subregion(sysmem, 0x02000000, mmiomem); 866 867 /* BMAP memory */ 868 memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64, 869 true, &error_fatal); 870 memory_region_add_subregion(sysmem, 0x020c0000, bmapm1); 871 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 872 memory_region_init_alias(bmapm2, NULL, "next.bmapmem2", bmapm1, 0x0, 64); 873 memory_region_add_subregion(sysmem, 0x820c0000, bmapm2); 874 875 /* BMAP IO - acts as a catch-all for now */ 876 memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr", 877 0x20000); 878 memory_region_add_subregion(sysmem, 0x02100000, scrmem); 879 880 /* KBD */ 881 dev = qdev_create(NULL, TYPE_NEXTKBD); 882 qdev_init_nofail(dev); 883 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000); 884 885 /* Load ROM here */ 886 if (bios_name == NULL) { 887 bios_name = ROM_FILE; 888 } 889 /* still not sure if the rom should also be mapped at 0x0*/ 890 memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal); 891 memory_region_add_subregion(sysmem, 0x01000000, rom); 892 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 893 if (!qtest_enabled()) { 894 error_report("Failed to load firmware '%s'.", bios_name); 895 } 896 } else { 897 uint8_t *ptr; 898 /* Initial PC is always at offset 4 in firmware binaries */ 899 ptr = rom_ptr(0x01000004, 4); 900 g_assert(ptr != NULL); 901 env->pc = ldl_p(ptr); 902 if (env->pc >= 0x01020000) { 903 error_report("'%s' does not seem to be a valid firmware image.", 904 bios_name); 905 exit(1); 906 } 907 } 908 909 /* TODO: */ 910 /* Serial */ 911 /* Network */ 912 /* SCSI */ 913 914 /* DMA */ 915 memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5000); 916 memory_region_add_subregion(sysmem, 0x02000000, dmamem); 917 } 918 919 static void next_machine_class_init(ObjectClass *oc, void *data) 920 { 921 MachineClass *mc = MACHINE_CLASS(oc); 922 923 mc->desc = "NeXT Cube"; 924 mc->init = next_cube_init; 925 mc->default_ram_size = RAM_SIZE; 926 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 927 } 928 929 static const TypeInfo next_typeinfo = { 930 .name = TYPE_NEXT_MACHINE, 931 .parent = TYPE_MACHINE, 932 .class_init = next_machine_class_init, 933 .instance_size = sizeof(NeXTState), 934 }; 935 936 static void next_register_type(void) 937 { 938 type_register_static(&next_typeinfo); 939 } 940 941 type_init(next_register_type) 942