1 /* 2 * QEMU Motorla 680x0 Macintosh hardware System Emulator 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/units.h" 25 #include "qemu-common.h" 26 #include "sysemu/sysemu.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/boards.h" 30 #include "hw/irq.h" 31 #include "elf.h" 32 #include "hw/loader.h" 33 #include "ui/console.h" 34 #include "exec/address-spaces.h" 35 #include "hw/char/escc.h" 36 #include "hw/sysbus.h" 37 #include "hw/scsi/esp.h" 38 #include "bootinfo.h" 39 #include "hw/misc/mac_via.h" 40 #include "hw/input/adb.h" 41 #include "hw/nubus/mac-nubus-bridge.h" 42 #include "hw/display/macfb.h" 43 #include "hw/block/swim.h" 44 #include "net/net.h" 45 #include "qapi/error.h" 46 #include "sysemu/qtest.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/reset.h" 49 50 #define MACROM_ADDR 0x40000000 51 #define MACROM_SIZE 0x00100000 52 53 #define MACROM_FILENAME "MacROM.bin" 54 55 #define Q800_MACHINE_ID 35 56 #define Q800_CPU_ID (1 << 2) 57 #define Q800_FPU_ID (1 << 2) 58 #define Q800_MMU_ID (1 << 2) 59 60 #define MACH_MAC 3 61 #define Q800_MAC_CPU_ID 2 62 63 #define VIA_BASE 0x50f00000 64 #define SONIC_PROM_BASE 0x50f08000 65 #define SONIC_BASE 0x50f0a000 66 #define SCC_BASE 0x50f0c020 67 #define ESP_BASE 0x50f10000 68 #define ESP_PDMA 0x50f10100 69 #define ASC_BASE 0x50F14000 70 #define SWIM_BASE 0x50F1E000 71 #define NUBUS_SUPER_SLOT_BASE 0x60000000 72 #define NUBUS_SLOT_BASE 0xf0000000 73 74 /* 75 * the video base, whereas it a Nubus address, 76 * is needed by the kernel to have early display and 77 * thus provided by the bootloader 78 */ 79 #define VIDEO_BASE 0xf9001000 80 81 #define MAC_CLOCK 3686418 82 83 /* 84 * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip 85 * that performs a variety of functions (RAM management, clock generation, ...). 86 * The GLUE chip receives interrupt requests from various devices, 87 * assign priority to each, and asserts one or more interrupt line to the 88 * CPU. 89 */ 90 91 typedef struct { 92 M68kCPU *cpu; 93 uint8_t ipr; 94 } GLUEState; 95 96 static void GLUE_set_irq(void *opaque, int irq, int level) 97 { 98 GLUEState *s = opaque; 99 int i; 100 101 if (level) { 102 s->ipr |= 1 << irq; 103 } else { 104 s->ipr &= ~(1 << irq); 105 } 106 107 for (i = 7; i >= 0; i--) { 108 if ((s->ipr >> i) & 1) { 109 m68k_set_irq_level(s->cpu, i + 1, i + 25); 110 return; 111 } 112 } 113 m68k_set_irq_level(s->cpu, 0, 0); 114 } 115 116 static void main_cpu_reset(void *opaque) 117 { 118 M68kCPU *cpu = opaque; 119 CPUState *cs = CPU(cpu); 120 121 cpu_reset(cs); 122 cpu->env.aregs[7] = ldl_phys(cs->as, 0); 123 cpu->env.pc = ldl_phys(cs->as, 4); 124 } 125 126 static void q800_init(MachineState *machine) 127 { 128 M68kCPU *cpu = NULL; 129 int linux_boot; 130 int32_t kernel_size; 131 uint64_t elf_entry; 132 char *filename; 133 int bios_size; 134 ram_addr_t initrd_base; 135 int32_t initrd_size; 136 MemoryRegion *rom; 137 MemoryRegion *ram; 138 ram_addr_t ram_size = machine->ram_size; 139 const char *kernel_filename = machine->kernel_filename; 140 const char *initrd_filename = machine->initrd_filename; 141 const char *kernel_cmdline = machine->kernel_cmdline; 142 hwaddr parameters_base; 143 CPUState *cs; 144 DeviceState *dev; 145 DeviceState *via_dev; 146 SysBusESPState *sysbus_esp; 147 ESPState *esp; 148 SysBusDevice *sysbus; 149 BusState *adb_bus; 150 NubusBus *nubus; 151 GLUEState *irq; 152 qemu_irq *pic; 153 154 linux_boot = (kernel_filename != NULL); 155 156 if (ram_size > 1 * GiB) { 157 error_report("Too much memory for this machine: %" PRId64 " MiB, " 158 "maximum 1024 MiB", ram_size / MiB); 159 exit(1); 160 } 161 162 /* init CPUs */ 163 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 164 qemu_register_reset(main_cpu_reset, cpu); 165 166 ram = g_malloc(sizeof(*ram)); 167 memory_region_init_ram(ram, NULL, "m68k_mac.ram", ram_size, &error_abort); 168 memory_region_add_subregion(get_system_memory(), 0, ram); 169 170 /* IRQ Glue */ 171 172 irq = g_new0(GLUEState, 1); 173 irq->cpu = cpu; 174 pic = qemu_allocate_irqs(GLUE_set_irq, irq, 8); 175 176 /* VIA */ 177 178 via_dev = qdev_create(NULL, TYPE_MAC_VIA); 179 qdev_init_nofail(via_dev); 180 sysbus = SYS_BUS_DEVICE(via_dev); 181 sysbus_mmio_map(sysbus, 0, VIA_BASE); 182 qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]); 183 qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1, pic[1]); 184 185 186 adb_bus = qdev_get_child_bus(via_dev, "adb.0"); 187 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 188 qdev_init_nofail(dev); 189 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 190 qdev_init_nofail(dev); 191 192 /* MACSONIC */ 193 194 if (nb_nics > 1) { 195 error_report("q800 can only have one ethernet interface"); 196 exit(1); 197 } 198 199 qemu_check_nic_model(&nd_table[0], "dp83932"); 200 201 /* 202 * MacSonic driver needs an Apple MAC address 203 * Valid prefix are: 204 * 00:05:02 Apple 205 * 00:80:19 Dayna Communications, Inc. 206 * 00:A0:40 Apple 207 * 08:00:07 Apple 208 * (Q800 use the last one) 209 */ 210 nd_table[0].macaddr.a[0] = 0x08; 211 nd_table[0].macaddr.a[1] = 0x00; 212 nd_table[0].macaddr.a[2] = 0x07; 213 214 dev = qdev_create(NULL, "dp8393x"); 215 qdev_set_nic_properties(dev, &nd_table[0]); 216 qdev_prop_set_uint8(dev, "it_shift", 2); 217 qdev_prop_set_bit(dev, "big_endian", true); 218 qdev_prop_set_ptr(dev, "dma_mr", get_system_memory()); 219 qdev_init_nofail(dev); 220 sysbus = SYS_BUS_DEVICE(dev); 221 sysbus_mmio_map(sysbus, 0, SONIC_BASE); 222 sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE); 223 sysbus_connect_irq(sysbus, 0, pic[2]); 224 225 /* SCC */ 226 227 dev = qdev_create(NULL, TYPE_ESCC); 228 qdev_prop_set_uint32(dev, "disabled", 0); 229 qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); 230 qdev_prop_set_uint32(dev, "it_shift", 1); 231 qdev_prop_set_bit(dev, "bit_swap", true); 232 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 233 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 234 qdev_prop_set_uint32(dev, "chnBtype", 0); 235 qdev_prop_set_uint32(dev, "chnAtype", 0); 236 qdev_init_nofail(dev); 237 sysbus = SYS_BUS_DEVICE(dev); 238 sysbus_connect_irq(sysbus, 0, pic[3]); 239 sysbus_connect_irq(sysbus, 1, pic[3]); 240 sysbus_mmio_map(sysbus, 0, SCC_BASE); 241 242 /* SCSI */ 243 244 dev = qdev_create(NULL, TYPE_ESP); 245 sysbus_esp = ESP_STATE(dev); 246 esp = &sysbus_esp->esp; 247 esp->dma_memory_read = NULL; 248 esp->dma_memory_write = NULL; 249 esp->dma_opaque = NULL; 250 sysbus_esp->it_shift = 4; 251 esp->dma_enabled = 1; 252 qdev_init_nofail(dev); 253 254 sysbus = SYS_BUS_DEVICE(dev); 255 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev, 256 "via2-irq", 257 VIA2_IRQ_SCSI_BIT)); 258 sysbus_connect_irq(sysbus, 1, 259 qdev_get_gpio_in_named(via_dev, "via2-irq", 260 VIA2_IRQ_SCSI_DATA_BIT)); 261 sysbus_mmio_map(sysbus, 0, ESP_BASE); 262 sysbus_mmio_map(sysbus, 1, ESP_PDMA); 263 264 scsi_bus_legacy_handle_cmdline(&esp->bus); 265 266 /* SWIM floppy controller */ 267 268 dev = qdev_create(NULL, TYPE_SWIM); 269 qdev_init_nofail(dev); 270 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); 271 272 /* NuBus */ 273 274 dev = qdev_create(NULL, TYPE_MAC_NUBUS_BRIDGE); 275 qdev_init_nofail(dev); 276 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE); 277 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE); 278 279 nubus = MAC_NUBUS_BRIDGE(dev)->bus; 280 281 /* framebuffer in nubus slot #9 */ 282 283 dev = qdev_create(BUS(nubus), TYPE_NUBUS_MACFB); 284 qdev_prop_set_uint32(dev, "width", graphic_width); 285 qdev_prop_set_uint32(dev, "height", graphic_height); 286 qdev_prop_set_uint8(dev, "depth", graphic_depth); 287 qdev_init_nofail(dev); 288 289 cs = CPU(cpu); 290 if (linux_boot) { 291 uint64_t high; 292 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 293 &elf_entry, NULL, &high, 1, 294 EM_68K, 0, 0); 295 if (kernel_size < 0) { 296 error_report("could not load kernel '%s'", kernel_filename); 297 exit(1); 298 } 299 stl_phys(cs->as, 4, elf_entry); /* reset initial PC */ 300 parameters_base = (high + 1) & ~1; 301 302 BOOTINFO1(cs->as, parameters_base, BI_MACHTYPE, MACH_MAC); 303 BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, Q800_FPU_ID); 304 BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, Q800_MMU_ID); 305 BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, Q800_CPU_ID); 306 BOOTINFO1(cs->as, parameters_base, BI_MAC_CPUID, Q800_MAC_CPU_ID); 307 BOOTINFO1(cs->as, parameters_base, BI_MAC_MODEL, Q800_MACHINE_ID); 308 BOOTINFO1(cs->as, parameters_base, 309 BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */ 310 BOOTINFO2(cs->as, parameters_base, BI_MEMCHUNK, 0, ram_size); 311 BOOTINFO1(cs->as, parameters_base, BI_MAC_VADDR, VIDEO_BASE); 312 BOOTINFO1(cs->as, parameters_base, BI_MAC_VDEPTH, graphic_depth); 313 BOOTINFO1(cs->as, parameters_base, BI_MAC_VDIM, 314 (graphic_height << 16) | graphic_width); 315 BOOTINFO1(cs->as, parameters_base, BI_MAC_VROW, 316 (graphic_width * graphic_depth + 7) / 8); 317 BOOTINFO1(cs->as, parameters_base, BI_MAC_SCCBASE, SCC_BASE); 318 319 if (kernel_cmdline) { 320 BOOTINFOSTR(cs->as, parameters_base, BI_COMMAND_LINE, 321 kernel_cmdline); 322 } 323 324 /* load initrd */ 325 if (initrd_filename) { 326 initrd_size = get_image_size(initrd_filename); 327 if (initrd_size < 0) { 328 error_report("could not load initial ram disk '%s'", 329 initrd_filename); 330 exit(1); 331 } 332 333 initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK; 334 load_image_targphys(initrd_filename, initrd_base, 335 ram_size - initrd_base); 336 BOOTINFO2(cs->as, parameters_base, BI_RAMDISK, initrd_base, 337 initrd_size); 338 } else { 339 initrd_base = 0; 340 initrd_size = 0; 341 } 342 BOOTINFO0(cs->as, parameters_base, BI_LAST); 343 } else { 344 uint8_t *ptr; 345 /* allocate and load BIOS */ 346 rom = g_malloc(sizeof(*rom)); 347 memory_region_init_ram(rom, NULL, "m68k_mac.rom", MACROM_SIZE, 348 &error_abort); 349 if (bios_name == NULL) { 350 bios_name = MACROM_FILENAME; 351 } 352 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 353 memory_region_set_readonly(rom, true); 354 memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom); 355 356 /* Load MacROM binary */ 357 if (filename) { 358 bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE); 359 g_free(filename); 360 } else { 361 bios_size = -1; 362 } 363 364 /* Remove qtest_enabled() check once firmware files are in the tree */ 365 if (!qtest_enabled()) { 366 if (bios_size < 0 || bios_size > MACROM_SIZE) { 367 error_report("could not load MacROM '%s'", bios_name); 368 exit(1); 369 } 370 371 ptr = rom_ptr(MACROM_ADDR, MACROM_SIZE); 372 stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */ 373 stl_phys(cs->as, 4, 374 MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */ 375 } 376 } 377 } 378 379 static void q800_machine_class_init(ObjectClass *oc, void *data) 380 { 381 MachineClass *mc = MACHINE_CLASS(oc); 382 mc->desc = "Macintosh Quadra 800"; 383 mc->init = q800_init; 384 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 385 mc->max_cpus = 1; 386 mc->is_default = 0; 387 mc->block_default_type = IF_SCSI; 388 } 389 390 static const TypeInfo q800_machine_typeinfo = { 391 .name = MACHINE_TYPE_NAME("q800"), 392 .parent = TYPE_MACHINE, 393 .class_init = q800_machine_class_init, 394 }; 395 396 static void q800_machine_register_types(void) 397 { 398 type_register_static(&q800_machine_typeinfo); 399 } 400 401 type_init(q800_machine_register_types) 402