1 /* 2 * Model of Petalogix linux reference design targeting Xilinx Spartan ml605 3 * board. 4 * 5 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu> 6 * Copyright (c) 2011 PetaLogix 7 * Copyright (c) 2009 Edgar E. Iglesias. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "hw/sysbus.h" 29 #include "hw/hw.h" 30 #include "net/net.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/devices.h" 34 #include "hw/boards.h" 35 #include "sysemu/blockdev.h" 36 #include "hw/char/serial.h" 37 #include "exec/address-spaces.h" 38 #include "hw/ssi.h" 39 40 #include "boot.h" 41 42 #include "hw/stream.h" 43 44 #define LMB_BRAM_SIZE (128 * 1024) 45 #define FLASH_SIZE (32 * 1024 * 1024) 46 47 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb" 48 49 #define NUM_SPI_FLASHES 4 50 51 #define SPI_BASEADDR 0x40a00000 52 #define MEMORY_BASEADDR 0x50000000 53 #define FLASH_BASEADDR 0x86000000 54 #define INTC_BASEADDR 0x81800000 55 #define TIMER_BASEADDR 0x83c00000 56 #define UART16550_BASEADDR 0x83e00000 57 #define AXIENET_BASEADDR 0x82780000 58 #define AXIDMA_BASEADDR 0x84600000 59 60 #define AXIDMA_IRQ1 0 61 #define AXIDMA_IRQ0 1 62 #define TIMER_IRQ 2 63 #define AXIENET_IRQ 3 64 #define SPI_IRQ 4 65 #define UART16550_IRQ 5 66 67 static void machine_cpu_reset(MicroBlazeCPU *cpu) 68 { 69 CPUMBState *env = &cpu->env; 70 71 env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ 72 /* setup pvr to match kernel setting */ 73 env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; 74 env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI; 75 env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); 76 env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK; 77 env->pvr.regs[4] = 0xc56b8000; 78 env->pvr.regs[5] = 0xc56be000; 79 } 80 81 static void 82 petalogix_ml605_init(MachineState *machine) 83 { 84 ram_addr_t ram_size = machine->ram_size; 85 MemoryRegion *address_space_mem = get_system_memory(); 86 DeviceState *dev, *dma, *eth0; 87 Object *ds, *cs; 88 MicroBlazeCPU *cpu; 89 SysBusDevice *busdev; 90 DriveInfo *dinfo; 91 int i; 92 hwaddr ddr_base = MEMORY_BASEADDR; 93 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); 94 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 95 qemu_irq irq[32]; 96 97 /* init CPUs */ 98 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); 99 object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); 100 101 /* Attach emulated BRAM through the LMB. */ 102 memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram", 103 LMB_BRAM_SIZE); 104 vmstate_register_ram_global(phys_lmb_bram); 105 memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram); 106 107 memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size); 108 vmstate_register_ram_global(phys_ram); 109 memory_region_add_subregion(address_space_mem, ddr_base, phys_ram); 110 111 dinfo = drive_get(IF_PFLASH, 0, 0); 112 /* 5th parameter 2 means bank-width 113 * 10th paremeter 0 means little-endian */ 114 pflash_cfi01_register(FLASH_BASEADDR, 115 NULL, "petalogix_ml605.flash", FLASH_SIZE, 116 dinfo ? dinfo->bdrv : NULL, (64 * 1024), 117 FLASH_SIZE >> 16, 118 2, 0x89, 0x18, 0x0000, 0x0, 0); 119 120 121 dev = qdev_create(NULL, "xlnx.xps-intc"); 122 qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); 123 qdev_init_nofail(dev); 124 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 125 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 126 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ)); 127 for (i = 0; i < 32; i++) { 128 irq[i] = qdev_get_gpio_in(dev, i); 129 } 130 131 serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2, 132 irq[UART16550_IRQ], 115200, serial_hds[0], 133 DEVICE_LITTLE_ENDIAN); 134 135 /* 2 timers at irq 2 @ 100 Mhz. */ 136 dev = qdev_create(NULL, "xlnx.xps-timer"); 137 qdev_prop_set_uint32(dev, "one-timer-only", 0); 138 qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); 139 qdev_init_nofail(dev); 140 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 141 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 142 143 /* axi ethernet and dma initialization. */ 144 qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet"); 145 eth0 = qdev_create(NULL, "xlnx.axi-ethernet"); 146 dma = qdev_create(NULL, "xlnx.axi-dma"); 147 148 /* FIXME: attach to the sysbus instead */ 149 object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0), 150 NULL); 151 object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma), 152 NULL); 153 154 ds = object_property_get_link(OBJECT(dma), 155 "axistream-connected-target", NULL); 156 cs = object_property_get_link(OBJECT(dma), 157 "axistream-control-connected-target", NULL); 158 qdev_set_nic_properties(eth0, &nd_table[0]); 159 qdev_prop_set_uint32(eth0, "rxmem", 0x1000); 160 qdev_prop_set_uint32(eth0, "txmem", 0x1000); 161 object_property_set_link(OBJECT(eth0), OBJECT(ds), 162 "axistream-connected", &error_abort); 163 object_property_set_link(OBJECT(eth0), OBJECT(cs), 164 "axistream-control-connected", &error_abort); 165 qdev_init_nofail(eth0); 166 sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR); 167 sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]); 168 169 ds = object_property_get_link(OBJECT(eth0), 170 "axistream-connected-target", NULL); 171 cs = object_property_get_link(OBJECT(eth0), 172 "axistream-control-connected-target", NULL); 173 qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000); 174 object_property_set_link(OBJECT(dma), OBJECT(ds), 175 "axistream-connected", &error_abort); 176 object_property_set_link(OBJECT(dma), OBJECT(cs), 177 "axistream-control-connected", &error_abort); 178 qdev_init_nofail(dma); 179 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); 180 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]); 181 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]); 182 183 { 184 SSIBus *spi; 185 186 dev = qdev_create(NULL, "xlnx.xps-spi"); 187 qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); 188 qdev_init_nofail(dev); 189 busdev = SYS_BUS_DEVICE(dev); 190 sysbus_mmio_map(busdev, 0, SPI_BASEADDR); 191 sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]); 192 193 spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); 194 195 for (i = 0; i < NUM_SPI_FLASHES; i++) { 196 qemu_irq cs_line; 197 198 dev = ssi_create_slave(spi, "n25q128"); 199 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 200 sysbus_connect_irq(busdev, i+1, cs_line); 201 } 202 } 203 204 microblaze_load_kernel(cpu, ddr_base, ram_size, 205 machine->initrd_filename, 206 BINARY_DEVICE_TREE_FILE, 207 machine_cpu_reset); 208 209 } 210 211 static QEMUMachine petalogix_ml605_machine = { 212 .name = "petalogix-ml605", 213 .desc = "PetaLogix linux refdesign for xilinx ml605 little endian", 214 .init = petalogix_ml605_init, 215 .is_default = 0, 216 }; 217 218 static void petalogix_ml605_machine_init(void) 219 { 220 qemu_register_machine(&petalogix_ml605_machine); 221 } 222 223 machine_init(petalogix_ml605_machine_init); 224