1 /* 2 * QEMU Malta board support 3 * 4 * Copyright (c) 2006 Aurelien Jarno 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/bitops.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "hw/clock.h" 31 #include "hw/southbridge/piix.h" 32 #include "hw/isa/superio.h" 33 #include "hw/char/serial.h" 34 #include "net/net.h" 35 #include "hw/boards.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/block/flash.h" 38 #include "hw/mips/mips.h" 39 #include "hw/mips/cpudevs.h" 40 #include "hw/pci/pci.h" 41 #include "qemu/log.h" 42 #include "hw/mips/bios.h" 43 #include "hw/ide.h" 44 #include "hw/irq.h" 45 #include "hw/loader.h" 46 #include "elf.h" 47 #include "qom/object.h" 48 #include "hw/sysbus.h" /* SysBusDevice */ 49 #include "qemu/host-utils.h" 50 #include "sysemu/qtest.h" 51 #include "sysemu/reset.h" 52 #include "sysemu/runstate.h" 53 #include "qapi/error.h" 54 #include "qemu/error-report.h" 55 #include "hw/misc/empty_slot.h" 56 #include "sysemu/kvm.h" 57 #include "semihosting/semihost.h" 58 #include "hw/mips/cps.h" 59 #include "hw/qdev-clock.h" 60 61 #define ENVP_PADDR 0x2000 62 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) 63 #define ENVP_NB_ENTRIES 16 64 #define ENVP_ENTRY_SIZE 256 65 66 /* Hardware addresses */ 67 #define FLASH_ADDRESS 0x1e000000ULL 68 #define FPGA_ADDRESS 0x1f000000ULL 69 #define RESET_ADDRESS 0x1fc00000ULL 70 71 #define FLASH_SIZE 0x400000 72 73 #define MAX_IDE_BUS 2 74 75 typedef struct { 76 MemoryRegion iomem; 77 MemoryRegion iomem_lo; /* 0 - 0x900 */ 78 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */ 79 uint32_t leds; 80 uint32_t brk; 81 uint32_t gpout; 82 uint32_t i2cin; 83 uint32_t i2coe; 84 uint32_t i2cout; 85 uint32_t i2csel; 86 CharBackend display; 87 char display_text[9]; 88 SerialMM *uart; 89 bool display_inited; 90 } MaltaFPGAState; 91 92 #define TYPE_MIPS_MALTA "mips-malta" 93 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) 94 95 struct MaltaState { 96 SysBusDevice parent_obj; 97 98 Clock *cpuclk; 99 MIPSCPSState cps; 100 }; 101 102 static struct _loaderparams { 103 int ram_size, ram_low_size; 104 const char *kernel_filename; 105 const char *kernel_cmdline; 106 const char *initrd_filename; 107 } loaderparams; 108 109 /* Malta FPGA */ 110 static void malta_fpga_update_display(void *opaque) 111 { 112 char leds_text[9]; 113 int i; 114 MaltaFPGAState *s = opaque; 115 116 for (i = 7 ; i >= 0 ; i--) { 117 if (s->leds & (1 << i)) { 118 leds_text[i] = '#'; 119 } else { 120 leds_text[i] = ' '; 121 } 122 } 123 leds_text[8] = '\0'; 124 125 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", 126 leds_text); 127 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", 128 s->display_text); 129 } 130 131 /* 132 * EEPROM 24C01 / 24C02 emulation. 133 * 134 * Emulation for serial EEPROMs: 135 * 24C01 - 1024 bit (128 x 8) 136 * 24C02 - 2048 bit (256 x 8) 137 * 138 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. 139 */ 140 141 #if defined(DEBUG) 142 # define logout(fmt, ...) \ 143 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) 144 #else 145 # define logout(fmt, ...) ((void)0) 146 #endif 147 148 struct _eeprom24c0x_t { 149 uint8_t tick; 150 uint8_t address; 151 uint8_t command; 152 uint8_t ack; 153 uint8_t scl; 154 uint8_t sda; 155 uint8_t data; 156 /* uint16_t size; */ 157 uint8_t contents[256]; 158 }; 159 160 typedef struct _eeprom24c0x_t eeprom24c0x_t; 161 162 static eeprom24c0x_t spd_eeprom = { 163 .contents = { 164 /* 00000000: */ 165 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, 166 /* 00000008: */ 167 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, 168 /* 00000010: */ 169 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 170 /* 00000018: */ 171 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, 172 /* 00000020: */ 173 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, 174 /* 00000028: */ 175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 176 /* 00000030: */ 177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 178 /* 00000038: */ 179 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, 180 /* 00000040: */ 181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 182 /* 00000048: */ 183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 184 /* 00000050: */ 185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 186 /* 00000058: */ 187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 188 /* 00000060: */ 189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 190 /* 00000068: */ 191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 192 /* 00000070: */ 193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 194 /* 00000078: */ 195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, 196 }, 197 }; 198 199 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) 200 { 201 enum { SDR = 0x4, DDR2 = 0x8 } type; 202 uint8_t *spd = spd_eeprom.contents; 203 uint8_t nbanks = 0; 204 uint16_t density = 0; 205 int i; 206 207 /* work in terms of MB */ 208 ram_size /= MiB; 209 210 while ((ram_size >= 4) && (nbanks <= 2)) { 211 int sz_log2 = MIN(31 - clz32(ram_size), 14); 212 nbanks++; 213 density |= 1 << (sz_log2 - 2); 214 ram_size -= 1 << sz_log2; 215 } 216 217 /* split to 2 banks if possible */ 218 if ((nbanks == 1) && (density > 1)) { 219 nbanks++; 220 density >>= 1; 221 } 222 223 if (density & 0xff00) { 224 density = (density & 0xe0) | ((density >> 8) & 0x1f); 225 type = DDR2; 226 } else if (!(density & 0x1f)) { 227 type = DDR2; 228 } else { 229 type = SDR; 230 } 231 232 if (ram_size) { 233 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" 234 " of SDRAM", ram_size); 235 } 236 237 /* fill in SPD memory information */ 238 spd[2] = type; 239 spd[5] = nbanks; 240 spd[31] = density; 241 242 /* checksum */ 243 spd[63] = 0; 244 for (i = 0; i < 63; i++) { 245 spd[63] += spd[i]; 246 } 247 248 /* copy for SMBUS */ 249 memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); 250 } 251 252 static void generate_eeprom_serial(uint8_t *eeprom) 253 { 254 int i, pos = 0; 255 uint8_t mac[6] = { 0x00 }; 256 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; 257 258 /* version */ 259 eeprom[pos++] = 0x01; 260 261 /* count */ 262 eeprom[pos++] = 0x02; 263 264 /* MAC address */ 265 eeprom[pos++] = 0x01; /* MAC */ 266 eeprom[pos++] = 0x06; /* length */ 267 memcpy(&eeprom[pos], mac, sizeof(mac)); 268 pos += sizeof(mac); 269 270 /* serial number */ 271 eeprom[pos++] = 0x02; /* serial */ 272 eeprom[pos++] = 0x05; /* length */ 273 memcpy(&eeprom[pos], sn, sizeof(sn)); 274 pos += sizeof(sn); 275 276 /* checksum */ 277 eeprom[pos] = 0; 278 for (i = 0; i < pos; i++) { 279 eeprom[pos] += eeprom[i]; 280 } 281 } 282 283 static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) 284 { 285 logout("%u: scl = %u, sda = %u, data = 0x%02x\n", 286 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); 287 return eeprom->sda; 288 } 289 290 static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) 291 { 292 if (eeprom->scl && scl && (eeprom->sda != sda)) { 293 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", 294 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, 295 sda ? "stop" : "start"); 296 if (!sda) { 297 eeprom->tick = 1; 298 eeprom->command = 0; 299 } 300 } else if (eeprom->tick == 0 && !eeprom->ack) { 301 /* Waiting for start. */ 302 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", 303 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 304 } else if (!eeprom->scl && scl) { 305 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", 306 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 307 if (eeprom->ack) { 308 logout("\ti2c ack bit = 0\n"); 309 sda = 0; 310 eeprom->ack = 0; 311 } else if (eeprom->sda == sda) { 312 uint8_t bit = (sda != 0); 313 logout("\ti2c bit = %d\n", bit); 314 if (eeprom->tick < 9) { 315 eeprom->command <<= 1; 316 eeprom->command += bit; 317 eeprom->tick++; 318 if (eeprom->tick == 9) { 319 logout("\tcommand 0x%04x, %s\n", eeprom->command, 320 bit ? "read" : "write"); 321 eeprom->ack = 1; 322 } 323 } else if (eeprom->tick < 17) { 324 if (eeprom->command & 1) { 325 sda = ((eeprom->data & 0x80) != 0); 326 } 327 eeprom->address <<= 1; 328 eeprom->address += bit; 329 eeprom->tick++; 330 eeprom->data <<= 1; 331 if (eeprom->tick == 17) { 332 eeprom->data = eeprom->contents[eeprom->address]; 333 logout("\taddress 0x%04x, data 0x%02x\n", 334 eeprom->address, eeprom->data); 335 eeprom->ack = 1; 336 eeprom->tick = 0; 337 } 338 } else if (eeprom->tick >= 17) { 339 sda = 0; 340 } 341 } else { 342 logout("\tsda changed with raising scl\n"); 343 } 344 } else { 345 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, 346 scl, eeprom->sda, sda); 347 } 348 eeprom->scl = scl; 349 eeprom->sda = sda; 350 } 351 352 static uint64_t malta_fpga_read(void *opaque, hwaddr addr, 353 unsigned size) 354 { 355 MaltaFPGAState *s = opaque; 356 uint32_t val = 0; 357 uint32_t saddr; 358 359 saddr = (addr & 0xfffff); 360 361 switch (saddr) { 362 363 /* SWITCH Register */ 364 case 0x00200: 365 val = 0x00000000; 366 break; 367 368 /* STATUS Register */ 369 case 0x00208: 370 #ifdef TARGET_WORDS_BIGENDIAN 371 val = 0x00000012; 372 #else 373 val = 0x00000010; 374 #endif 375 break; 376 377 /* JMPRS Register */ 378 case 0x00210: 379 val = 0x00; 380 break; 381 382 /* LEDBAR Register */ 383 case 0x00408: 384 val = s->leds; 385 break; 386 387 /* BRKRES Register */ 388 case 0x00508: 389 val = s->brk; 390 break; 391 392 /* UART Registers are handled directly by the serial device */ 393 394 /* GPOUT Register */ 395 case 0x00a00: 396 val = s->gpout; 397 break; 398 399 /* XXX: implement a real I2C controller */ 400 401 /* GPINP Register */ 402 case 0x00a08: 403 /* IN = OUT until a real I2C control is implemented */ 404 if (s->i2csel) { 405 val = s->i2cout; 406 } else { 407 val = 0x00; 408 } 409 break; 410 411 /* I2CINP Register */ 412 case 0x00b00: 413 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); 414 break; 415 416 /* I2COE Register */ 417 case 0x00b08: 418 val = s->i2coe; 419 break; 420 421 /* I2COUT Register */ 422 case 0x00b10: 423 val = s->i2cout; 424 break; 425 426 /* I2CSEL Register */ 427 case 0x00b18: 428 val = s->i2csel; 429 break; 430 431 default: 432 qemu_log_mask(LOG_GUEST_ERROR, 433 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", 434 addr); 435 break; 436 } 437 return val; 438 } 439 440 static void malta_fpga_write(void *opaque, hwaddr addr, 441 uint64_t val, unsigned size) 442 { 443 MaltaFPGAState *s = opaque; 444 uint32_t saddr; 445 446 saddr = (addr & 0xfffff); 447 448 switch (saddr) { 449 450 /* SWITCH Register */ 451 case 0x00200: 452 break; 453 454 /* JMPRS Register */ 455 case 0x00210: 456 break; 457 458 /* LEDBAR Register */ 459 case 0x00408: 460 s->leds = val & 0xff; 461 malta_fpga_update_display(s); 462 break; 463 464 /* ASCIIWORD Register */ 465 case 0x00410: 466 snprintf(s->display_text, 9, "%08X", (uint32_t)val); 467 malta_fpga_update_display(s); 468 break; 469 470 /* ASCIIPOS0 to ASCIIPOS7 Registers */ 471 case 0x00418: 472 case 0x00420: 473 case 0x00428: 474 case 0x00430: 475 case 0x00438: 476 case 0x00440: 477 case 0x00448: 478 case 0x00450: 479 s->display_text[(saddr - 0x00418) >> 3] = (char) val; 480 malta_fpga_update_display(s); 481 break; 482 483 /* SOFTRES Register */ 484 case 0x00500: 485 if (val == 0x42) { 486 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 487 } 488 break; 489 490 /* BRKRES Register */ 491 case 0x00508: 492 s->brk = val & 0xff; 493 break; 494 495 /* UART Registers are handled directly by the serial device */ 496 497 /* GPOUT Register */ 498 case 0x00a00: 499 s->gpout = val & 0xff; 500 break; 501 502 /* I2COE Register */ 503 case 0x00b08: 504 s->i2coe = val & 0x03; 505 break; 506 507 /* I2COUT Register */ 508 case 0x00b10: 509 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); 510 s->i2cout = val; 511 break; 512 513 /* I2CSEL Register */ 514 case 0x00b18: 515 s->i2csel = val & 0x01; 516 break; 517 518 default: 519 qemu_log_mask(LOG_GUEST_ERROR, 520 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", 521 addr); 522 break; 523 } 524 } 525 526 static const MemoryRegionOps malta_fpga_ops = { 527 .read = malta_fpga_read, 528 .write = malta_fpga_write, 529 .endianness = DEVICE_NATIVE_ENDIAN, 530 }; 531 532 static void malta_fpga_reset(void *opaque) 533 { 534 MaltaFPGAState *s = opaque; 535 536 s->leds = 0x00; 537 s->brk = 0x0a; 538 s->gpout = 0x00; 539 s->i2cin = 0x3; 540 s->i2coe = 0x0; 541 s->i2cout = 0x3; 542 s->i2csel = 0x1; 543 544 s->display_text[8] = '\0'; 545 snprintf(s->display_text, 9, " "); 546 } 547 548 static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) 549 { 550 MaltaFPGAState *s = opaque; 551 552 if (event == CHR_EVENT_OPENED && !s->display_inited) { 553 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n"); 554 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 555 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 556 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 557 qemu_chr_fe_printf(&s->display, "\n"); 558 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n"); 559 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 560 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 561 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 562 s->display_inited = true; 563 } 564 } 565 566 static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, 567 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr) 568 { 569 MaltaFPGAState *s; 570 Chardev *chr; 571 572 s = g_new0(MaltaFPGAState, 1); 573 574 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, 575 "malta-fpga", 0x100000); 576 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", 577 &s->iomem, 0, 0x900); 578 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", 579 &s->iomem, 0xa00, 0x100000 - 0xa00); 580 581 memory_region_add_subregion(address_space, base, &s->iomem_lo); 582 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); 583 584 chr = qemu_chr_new("fpga", "vc:320x200", NULL); 585 qemu_chr_fe_init(&s->display, chr, NULL); 586 qemu_chr_fe_set_handlers(&s->display, NULL, NULL, 587 malta_fgpa_display_event, NULL, s, NULL, true); 588 589 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, 590 230400, uart_chr, DEVICE_NATIVE_ENDIAN); 591 592 malta_fpga_reset(s); 593 qemu_register_reset(malta_fpga_reset, s); 594 595 return s; 596 } 597 598 /* Network support */ 599 static void network_init(PCIBus *pci_bus) 600 { 601 int i; 602 603 for (i = 0; i < nb_nics; i++) { 604 NICInfo *nd = &nd_table[i]; 605 const char *default_devaddr = NULL; 606 607 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0)) 608 /* The malta board has a PCNet card using PCI SLOT 11 */ 609 default_devaddr = "0b"; 610 611 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr); 612 } 613 } 614 615 static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, 616 uint64_t kernel_entry) 617 { 618 uint16_t *p; 619 620 /* Small bootloader */ 621 p = (uint16_t *)base; 622 623 #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f) 624 #define NM_HI2(VAL) \ 625 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1)) 626 #define NM_LO(VAL) ((VAL) & 0xfff) 627 628 stw_p(p++, 0x2800); stw_p(p++, 0x001c); 629 /* bc to_here */ 630 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 631 /* nop */ 632 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 633 /* nop */ 634 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 635 /* nop */ 636 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 637 /* nop */ 638 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 639 /* nop */ 640 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 641 /* nop */ 642 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 643 /* nop */ 644 645 /* to_here: */ 646 if (semihosting_get_argc()) { 647 /* Preserve a0 content as arguments have been passed */ 648 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 649 /* nop */ 650 } else { 651 stw_p(p++, 0x0080); stw_p(p++, 0x0002); 652 /* li a0,2 */ 653 } 654 655 stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64)); 656 657 stw_p(p++, NM_HI2(ENVP_VADDR - 64)); 658 /* lui sp,%hi(ENVP_VADDR - 64) */ 659 660 stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64)); 661 /* ori sp,sp,%lo(ENVP_VADDR - 64) */ 662 663 stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR)); 664 665 stw_p(p++, NM_HI2(ENVP_VADDR)); 666 /* lui a1,%hi(ENVP_VADDR) */ 667 668 stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR)); 669 /* ori a1,a1,%lo(ENVP_VADDR) */ 670 671 stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8)); 672 673 stw_p(p++, NM_HI2(ENVP_VADDR + 8)); 674 /* lui a2,%hi(ENVP_VADDR + 8) */ 675 676 stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8)); 677 /* ori a2,a2,%lo(ENVP_VADDR + 8) */ 678 679 stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size)); 680 681 stw_p(p++, NM_HI2(loaderparams.ram_low_size)); 682 /* lui a3,%hi(loaderparams.ram_low_size) */ 683 684 stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); 685 /* ori a3,a3,%lo(loaderparams.ram_low_size) */ 686 687 /* 688 * Load BAR registers as done by YAMON: 689 * 690 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff 691 * - set up PCI0 MEM0 at 0x10000000, size 0x8000000 692 * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000 693 * 694 */ 695 stw_p(p++, 0xe040); stw_p(p++, 0x0681); 696 /* lui t1, %hi(0xb4000000) */ 697 698 #ifdef TARGET_WORDS_BIGENDIAN 699 700 stw_p(p++, 0xe020); stw_p(p++, 0x0be1); 701 /* lui t0, %hi(0xdf000000) */ 702 703 /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */ 704 stw_p(p++, 0x8422); stw_p(p++, 0x9068); 705 /* sw t0, 0x68(t1) */ 706 707 stw_p(p++, 0xe040); stw_p(p++, 0x077d); 708 /* lui t1, %hi(0xbbe00000) */ 709 710 stw_p(p++, 0xe020); stw_p(p++, 0x0801); 711 /* lui t0, %hi(0xc0000000) */ 712 713 /* 0x48 corresponds to GT_PCI0IOLD */ 714 stw_p(p++, 0x8422); stw_p(p++, 0x9048); 715 /* sw t0, 0x48(t1) */ 716 717 stw_p(p++, 0xe020); stw_p(p++, 0x0800); 718 /* lui t0, %hi(0x40000000) */ 719 720 /* 0x50 corresponds to GT_PCI0IOHD */ 721 stw_p(p++, 0x8422); stw_p(p++, 0x9050); 722 /* sw t0, 0x50(t1) */ 723 724 stw_p(p++, 0xe020); stw_p(p++, 0x0001); 725 /* lui t0, %hi(0x80000000) */ 726 727 /* 0x58 corresponds to GT_PCI0M0LD */ 728 stw_p(p++, 0x8422); stw_p(p++, 0x9058); 729 /* sw t0, 0x58(t1) */ 730 731 stw_p(p++, 0xe020); stw_p(p++, 0x07e0); 732 /* lui t0, %hi(0x3f000000) */ 733 734 /* 0x60 corresponds to GT_PCI0M0HD */ 735 stw_p(p++, 0x8422); stw_p(p++, 0x9060); 736 /* sw t0, 0x60(t1) */ 737 738 stw_p(p++, 0xe020); stw_p(p++, 0x0821); 739 /* lui t0, %hi(0xc1000000) */ 740 741 /* 0x80 corresponds to GT_PCI0M1LD */ 742 stw_p(p++, 0x8422); stw_p(p++, 0x9080); 743 /* sw t0, 0x80(t1) */ 744 745 stw_p(p++, 0xe020); stw_p(p++, 0x0bc0); 746 /* lui t0, %hi(0x5e000000) */ 747 748 #else 749 750 stw_p(p++, 0x0020); stw_p(p++, 0x00df); 751 /* addiu[32] t0, $0, 0xdf */ 752 753 /* 0x68 corresponds to GT_ISD */ 754 stw_p(p++, 0x8422); stw_p(p++, 0x9068); 755 /* sw t0, 0x68(t1) */ 756 757 /* Use kseg2 remapped address 0x1be00000 */ 758 stw_p(p++, 0xe040); stw_p(p++, 0x077d); 759 /* lui t1, %hi(0xbbe00000) */ 760 761 stw_p(p++, 0x0020); stw_p(p++, 0x00c0); 762 /* addiu[32] t0, $0, 0xc0 */ 763 764 /* 0x48 corresponds to GT_PCI0IOLD */ 765 stw_p(p++, 0x8422); stw_p(p++, 0x9048); 766 /* sw t0, 0x48(t1) */ 767 768 stw_p(p++, 0x0020); stw_p(p++, 0x0040); 769 /* addiu[32] t0, $0, 0x40 */ 770 771 /* 0x50 corresponds to GT_PCI0IOHD */ 772 stw_p(p++, 0x8422); stw_p(p++, 0x9050); 773 /* sw t0, 0x50(t1) */ 774 775 stw_p(p++, 0x0020); stw_p(p++, 0x0080); 776 /* addiu[32] t0, $0, 0x80 */ 777 778 /* 0x58 corresponds to GT_PCI0M0LD */ 779 stw_p(p++, 0x8422); stw_p(p++, 0x9058); 780 /* sw t0, 0x58(t1) */ 781 782 stw_p(p++, 0x0020); stw_p(p++, 0x003f); 783 /* addiu[32] t0, $0, 0x3f */ 784 785 /* 0x60 corresponds to GT_PCI0M0HD */ 786 stw_p(p++, 0x8422); stw_p(p++, 0x9060); 787 /* sw t0, 0x60(t1) */ 788 789 stw_p(p++, 0x0020); stw_p(p++, 0x00c1); 790 /* addiu[32] t0, $0, 0xc1 */ 791 792 /* 0x80 corresponds to GT_PCI0M1LD */ 793 stw_p(p++, 0x8422); stw_p(p++, 0x9080); 794 /* sw t0, 0x80(t1) */ 795 796 stw_p(p++, 0x0020); stw_p(p++, 0x005e); 797 /* addiu[32] t0, $0, 0x5e */ 798 799 #endif 800 801 /* 0x88 corresponds to GT_PCI0M1HD */ 802 stw_p(p++, 0x8422); stw_p(p++, 0x9088); 803 /* sw t0, 0x88(t1) */ 804 805 stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); 806 807 stw_p(p++, NM_HI2(kernel_entry)); 808 /* lui t9,%hi(kernel_entry) */ 809 810 stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry)); 811 /* ori t9,t9,%lo(kernel_entry) */ 812 813 stw_p(p++, 0x4bf9); stw_p(p++, 0x0000); 814 /* jalrc t8 */ 815 } 816 817 /* 818 * ROM and pseudo bootloader 819 * 820 * The following code implements a very very simple bootloader. It first 821 * loads the registers a0 to a3 to the values expected by the OS, and 822 * then jump at the kernel address. 823 * 824 * The bootloader should pass the locations of the kernel arguments and 825 * environment variables tables. Those tables contain the 32-bit address 826 * of NULL terminated strings. The environment variables table should be 827 * terminated by a NULL address. 828 * 829 * For a simpler implementation, the number of kernel arguments is fixed 830 * to two (the name of the kernel and the command line), and the two 831 * tables are actually the same one. 832 * 833 * The registers a0 to a3 should contain the following values: 834 * a0 - number of kernel arguments 835 * a1 - 32-bit address of the kernel arguments table 836 * a2 - 32-bit address of the environment variables table 837 * a3 - RAM size in bytes 838 */ 839 static void write_bootloader(uint8_t *base, uint64_t run_addr, 840 uint64_t kernel_entry) 841 { 842 uint32_t *p; 843 844 /* Small bootloader */ 845 p = (uint32_t *)base; 846 847 stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ 848 ((run_addr + 0x580) & 0x0fffffff) >> 2); 849 stl_p(p++, 0x00000000); /* nop */ 850 851 /* YAMON service vector */ 852 stl_p(base + 0x500, run_addr + 0x0580); /* start: */ 853 stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ 854 stl_p(base + 0x520, run_addr + 0x0580); /* start: */ 855 stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ 856 stl_p(base + 0x534, run_addr + 0x0808); /* print: */ 857 stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ 858 stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ 859 stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ 860 stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ 861 stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ 862 stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ 863 stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ 864 stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ 865 866 867 /* Second part of the bootloader */ 868 p = (uint32_t *) (base + 0x580); 869 870 if (semihosting_get_argc()) { 871 /* Preserve a0 content as arguments have been passed */ 872 stl_p(p++, 0x00000000); /* nop */ 873 } else { 874 stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */ 875 } 876 877 /* lui sp, high(ENVP_VADDR) */ 878 stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff)); 879 /* ori sp, sp, low(ENVP_VADDR) */ 880 stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff)); 881 /* lui a1, high(ENVP_VADDR) */ 882 stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff)); 883 /* ori a1, a1, low(ENVP_VADDR) */ 884 stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff)); 885 /* lui a2, high(ENVP_VADDR + 8) */ 886 stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff)); 887 /* ori a2, a2, low(ENVP_VADDR + 8) */ 888 stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff)); 889 /* lui a3, high(ram_low_size) */ 890 stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); 891 /* ori a3, a3, low(ram_low_size) */ 892 stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); 893 894 /* Load BAR registers as done by YAMON */ 895 stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ 896 897 #ifdef TARGET_WORDS_BIGENDIAN 898 stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */ 899 #else 900 stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */ 901 #endif 902 stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */ 903 904 stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */ 905 906 #ifdef TARGET_WORDS_BIGENDIAN 907 stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */ 908 #else 909 stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */ 910 #endif 911 stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */ 912 #ifdef TARGET_WORDS_BIGENDIAN 913 stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */ 914 #else 915 stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */ 916 #endif 917 stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */ 918 919 #ifdef TARGET_WORDS_BIGENDIAN 920 stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */ 921 #else 922 stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */ 923 #endif 924 stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */ 925 #ifdef TARGET_WORDS_BIGENDIAN 926 stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */ 927 #else 928 stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */ 929 #endif 930 stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */ 931 932 #ifdef TARGET_WORDS_BIGENDIAN 933 stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */ 934 #else 935 stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */ 936 #endif 937 stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */ 938 #ifdef TARGET_WORDS_BIGENDIAN 939 stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */ 940 #else 941 stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */ 942 #endif 943 stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */ 944 945 /* Jump to kernel code */ 946 stl_p(p++, 0x3c1f0000 | 947 ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */ 948 stl_p(p++, 0x37ff0000 | 949 (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */ 950 stl_p(p++, 0x03e00009); /* jalr ra */ 951 stl_p(p++, 0x00000000); /* nop */ 952 953 /* YAMON subroutines */ 954 p = (uint32_t *) (base + 0x800); 955 stl_p(p++, 0x03e00009); /* jalr ra */ 956 stl_p(p++, 0x24020000); /* li v0,0 */ 957 /* 808 YAMON print */ 958 stl_p(p++, 0x03e06821); /* move t5,ra */ 959 stl_p(p++, 0x00805821); /* move t3,a0 */ 960 stl_p(p++, 0x00a05021); /* move t2,a1 */ 961 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 962 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 963 stl_p(p++, 0x10800005); /* beqz a0,834 */ 964 stl_p(p++, 0x00000000); /* nop */ 965 stl_p(p++, 0x0ff0021c); /* jal 870 */ 966 stl_p(p++, 0x00000000); /* nop */ 967 stl_p(p++, 0x1000fff9); /* b 814 */ 968 stl_p(p++, 0x00000000); /* nop */ 969 stl_p(p++, 0x01a00009); /* jalr t5 */ 970 stl_p(p++, 0x01602021); /* move a0,t3 */ 971 /* 0x83c YAMON print_count */ 972 stl_p(p++, 0x03e06821); /* move t5,ra */ 973 stl_p(p++, 0x00805821); /* move t3,a0 */ 974 stl_p(p++, 0x00a05021); /* move t2,a1 */ 975 stl_p(p++, 0x00c06021); /* move t4,a2 */ 976 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 977 stl_p(p++, 0x0ff0021c); /* jal 870 */ 978 stl_p(p++, 0x00000000); /* nop */ 979 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 980 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ 981 stl_p(p++, 0x1580fffa); /* bnez t4,84c */ 982 stl_p(p++, 0x00000000); /* nop */ 983 stl_p(p++, 0x01a00009); /* jalr t5 */ 984 stl_p(p++, 0x01602021); /* move a0,t3 */ 985 /* 0x870 */ 986 stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ 987 stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ 988 stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ 989 stl_p(p++, 0x00000000); /* nop */ 990 stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ 991 stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ 992 stl_p(p++, 0x00000000); /* nop */ 993 stl_p(p++, 0x03e00009); /* jalr ra */ 994 stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ 995 996 } 997 998 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, 999 const char *string, ...) 1000 { 1001 va_list ap; 1002 uint32_t table_addr; 1003 1004 if (index >= ENVP_NB_ENTRIES) { 1005 return; 1006 } 1007 1008 if (string == NULL) { 1009 prom_buf[index] = 0; 1010 return; 1011 } 1012 1013 table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; 1014 prom_buf[index] = tswap32(ENVP_VADDR + table_addr); 1015 1016 va_start(ap, string); 1017 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); 1018 va_end(ap); 1019 } 1020 1021 /* Kernel */ 1022 static uint64_t load_kernel(void) 1023 { 1024 uint64_t kernel_entry, kernel_high, initrd_size; 1025 long kernel_size; 1026 ram_addr_t initrd_offset; 1027 int big_endian; 1028 uint32_t *prom_buf; 1029 long prom_size; 1030 int prom_index = 0; 1031 uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr); 1032 1033 #ifdef TARGET_WORDS_BIGENDIAN 1034 big_endian = 1; 1035 #else 1036 big_endian = 0; 1037 #endif 1038 1039 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 1040 cpu_mips_kseg0_to_phys, NULL, 1041 &kernel_entry, NULL, 1042 &kernel_high, NULL, big_endian, EM_MIPS, 1043 1, 0); 1044 if (kernel_size < 0) { 1045 error_report("could not load kernel '%s': %s", 1046 loaderparams.kernel_filename, 1047 load_elf_strerror(kernel_size)); 1048 exit(1); 1049 } 1050 1051 /* Check where the kernel has been linked */ 1052 if (kernel_entry & 0x80000000ll) { 1053 if (kvm_enabled()) { 1054 error_report("KVM guest kernels must be linked in useg. " 1055 "Did you forget to enable CONFIG_KVM_GUEST?"); 1056 exit(1); 1057 } 1058 1059 xlate_to_kseg0 = cpu_mips_phys_to_kseg0; 1060 } else { 1061 /* if kernel entry is in useg it is probably a KVM T&E kernel */ 1062 mips_um_ksegs_enable(); 1063 1064 xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0; 1065 } 1066 1067 /* load initrd */ 1068 initrd_size = 0; 1069 initrd_offset = 0; 1070 if (loaderparams.initrd_filename) { 1071 initrd_size = get_image_size(loaderparams.initrd_filename); 1072 if (initrd_size > 0) { 1073 /* 1074 * The kernel allocates the bootmap memory in the low memory after 1075 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB 1076 * pages. 1077 */ 1078 initrd_offset = ROUND_UP(loaderparams.ram_low_size 1079 - (initrd_size + 128 * KiB), 1080 INITRD_PAGE_SIZE); 1081 if (kernel_high >= initrd_offset) { 1082 error_report("memory too small for initial ram disk '%s'", 1083 loaderparams.initrd_filename); 1084 exit(1); 1085 } 1086 initrd_size = load_image_targphys(loaderparams.initrd_filename, 1087 initrd_offset, 1088 loaderparams.ram_size - initrd_offset); 1089 } 1090 if (initrd_size == (target_ulong) -1) { 1091 error_report("could not load initial ram disk '%s'", 1092 loaderparams.initrd_filename); 1093 exit(1); 1094 } 1095 } 1096 1097 /* Setup prom parameters. */ 1098 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); 1099 prom_buf = g_malloc(prom_size); 1100 1101 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); 1102 if (initrd_size > 0) { 1103 prom_set(prom_buf, prom_index++, 1104 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", 1105 xlate_to_kseg0(NULL, initrd_offset), 1106 initrd_size, loaderparams.kernel_cmdline); 1107 } else { 1108 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); 1109 } 1110 1111 prom_set(prom_buf, prom_index++, "memsize"); 1112 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size); 1113 1114 prom_set(prom_buf, prom_index++, "ememsize"); 1115 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size); 1116 1117 prom_set(prom_buf, prom_index++, "modetty0"); 1118 prom_set(prom_buf, prom_index++, "38400n8r"); 1119 prom_set(prom_buf, prom_index++, NULL); 1120 1121 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR); 1122 1123 g_free(prom_buf); 1124 return kernel_entry; 1125 } 1126 1127 static void malta_mips_config(MIPSCPU *cpu) 1128 { 1129 MachineState *ms = MACHINE(qdev_get_machine()); 1130 unsigned int smp_cpus = ms->smp.cpus; 1131 CPUMIPSState *env = &cpu->env; 1132 CPUState *cs = CPU(cpu); 1133 1134 if (ase_mt_available(env)) { 1135 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, 1136 CP0MVPC0_PTC, 8, 1137 smp_cpus * cs->nr_threads - 1); 1138 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, 1139 CP0MVPC0_PVPE, 4, smp_cpus - 1); 1140 } 1141 } 1142 1143 static void main_cpu_reset(void *opaque) 1144 { 1145 MIPSCPU *cpu = opaque; 1146 CPUMIPSState *env = &cpu->env; 1147 1148 cpu_reset(CPU(cpu)); 1149 1150 /* 1151 * The bootloader does not need to be rewritten as it is located in a 1152 * read only location. The kernel location and the arguments table 1153 * location does not change. 1154 */ 1155 if (loaderparams.kernel_filename) { 1156 env->CP0_Status &= ~(1 << CP0St_ERL); 1157 } 1158 1159 malta_mips_config(cpu); 1160 1161 if (kvm_enabled()) { 1162 /* Start running from the bootloader we wrote to end of RAM */ 1163 env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size; 1164 } 1165 } 1166 1167 static void create_cpu_without_cps(MachineState *ms, MaltaState *s, 1168 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1169 { 1170 CPUMIPSState *env; 1171 MIPSCPU *cpu; 1172 int i; 1173 1174 for (i = 0; i < ms->smp.cpus; i++) { 1175 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); 1176 1177 /* Init internal devices */ 1178 cpu_mips_irq_init_cpu(cpu); 1179 cpu_mips_clock_init(cpu); 1180 qemu_register_reset(main_cpu_reset, cpu); 1181 } 1182 1183 cpu = MIPS_CPU(first_cpu); 1184 env = &cpu->env; 1185 *i8259_irq = env->irq[2]; 1186 *cbus_irq = env->irq[4]; 1187 } 1188 1189 static void create_cps(MachineState *ms, MaltaState *s, 1190 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1191 { 1192 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); 1193 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, 1194 &error_fatal); 1195 object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, 1196 &error_fatal); 1197 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); 1198 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 1199 1200 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 1201 1202 *i8259_irq = get_cps_irq(&s->cps, 3); 1203 *cbus_irq = NULL; 1204 } 1205 1206 static void mips_create_cpu(MachineState *ms, MaltaState *s, 1207 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1208 { 1209 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { 1210 create_cps(ms, s, cbus_irq, i8259_irq); 1211 } else { 1212 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); 1213 } 1214 } 1215 1216 static 1217 void mips_malta_init(MachineState *machine) 1218 { 1219 ram_addr_t ram_size = machine->ram_size; 1220 ram_addr_t ram_low_size; 1221 const char *kernel_filename = machine->kernel_filename; 1222 const char *kernel_cmdline = machine->kernel_cmdline; 1223 const char *initrd_filename = machine->initrd_filename; 1224 char *filename; 1225 PFlashCFI01 *fl; 1226 MemoryRegion *system_memory = get_system_memory(); 1227 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); 1228 MemoryRegion *ram_low_postio; 1229 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); 1230 const size_t smbus_eeprom_size = 8 * 256; 1231 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); 1232 uint64_t kernel_entry, bootloader_run_addr; 1233 PCIBus *pci_bus; 1234 ISABus *isa_bus; 1235 qemu_irq cbus_irq, i8259_irq; 1236 I2CBus *smbus; 1237 DriveInfo *dinfo; 1238 int fl_idx = 0; 1239 int be; 1240 MaltaState *s; 1241 DeviceState *dev; 1242 1243 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); 1244 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); 1245 1246 /* create CPU */ 1247 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); 1248 1249 /* allocate RAM */ 1250 if (ram_size > 2 * GiB) { 1251 error_report("Too much memory for this machine: %" PRId64 "MB," 1252 " maximum 2048MB", ram_size / MiB); 1253 exit(1); 1254 } 1255 1256 /* register RAM at high address where it is undisturbed by IO */ 1257 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 1258 1259 /* alias for pre IO hole access */ 1260 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", 1261 machine->ram, 0, MIN(ram_size, 256 * MiB)); 1262 memory_region_add_subregion(system_memory, 0, ram_low_preio); 1263 1264 /* alias for post IO hole access, if there is enough RAM */ 1265 if (ram_size > 512 * MiB) { 1266 ram_low_postio = g_new(MemoryRegion, 1); 1267 memory_region_init_alias(ram_low_postio, NULL, 1268 "mips_malta_low_postio.ram", 1269 machine->ram, 512 * MiB, 1270 ram_size - 512 * MiB); 1271 memory_region_add_subregion(system_memory, 512 * MiB, 1272 ram_low_postio); 1273 } 1274 1275 #ifdef TARGET_WORDS_BIGENDIAN 1276 be = 1; 1277 #else 1278 be = 0; 1279 #endif 1280 1281 /* FPGA */ 1282 1283 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ 1284 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); 1285 1286 /* Load firmware in flash / BIOS. */ 1287 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 1288 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", 1289 FLASH_SIZE, 1290 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 1291 65536, 1292 4, 0x0000, 0x0000, 0x0000, 0x0000, be); 1293 bios = pflash_cfi01_get_memory(fl); 1294 fl_idx++; 1295 if (kernel_filename) { 1296 ram_low_size = MIN(ram_size, 256 * MiB); 1297 /* For KVM we reserve 1MB of RAM for running bootloader */ 1298 if (kvm_enabled()) { 1299 ram_low_size -= 0x100000; 1300 bootloader_run_addr = cpu_mips_kvm_um_phys_to_kseg0(NULL, ram_low_size); 1301 } else { 1302 bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS); 1303 } 1304 1305 /* Write a small bootloader to the flash location. */ 1306 loaderparams.ram_size = ram_size; 1307 loaderparams.ram_low_size = ram_low_size; 1308 loaderparams.kernel_filename = kernel_filename; 1309 loaderparams.kernel_cmdline = kernel_cmdline; 1310 loaderparams.initrd_filename = initrd_filename; 1311 kernel_entry = load_kernel(); 1312 1313 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { 1314 write_bootloader(memory_region_get_ram_ptr(bios), 1315 bootloader_run_addr, kernel_entry); 1316 } else { 1317 write_bootloader_nanomips(memory_region_get_ram_ptr(bios), 1318 bootloader_run_addr, kernel_entry); 1319 } 1320 if (kvm_enabled()) { 1321 /* Write the bootloader code @ the end of RAM, 1MB reserved */ 1322 write_bootloader(memory_region_get_ram_ptr(ram_low_preio) + 1323 ram_low_size, 1324 bootloader_run_addr, kernel_entry); 1325 } 1326 } else { 1327 target_long bios_size = FLASH_SIZE; 1328 /* The flash region isn't executable from a KVM guest */ 1329 if (kvm_enabled()) { 1330 error_report("KVM enabled but no -kernel argument was specified. " 1331 "Booting from flash is not supported with KVM."); 1332 exit(1); 1333 } 1334 /* Load firmware from flash. */ 1335 if (!dinfo) { 1336 /* Load a BIOS image. */ 1337 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 1338 machine->firmware ?: BIOS_FILENAME); 1339 if (filename) { 1340 bios_size = load_image_targphys(filename, FLASH_ADDRESS, 1341 BIOS_SIZE); 1342 g_free(filename); 1343 } else { 1344 bios_size = -1; 1345 } 1346 if ((bios_size < 0 || bios_size > BIOS_SIZE) && 1347 machine->firmware && !qtest_enabled()) { 1348 error_report("Could not load MIPS bios '%s'", machine->firmware); 1349 exit(1); 1350 } 1351 } 1352 /* 1353 * In little endian mode the 32bit words in the bios are swapped, 1354 * a neat trick which allows bi-endian firmware. 1355 */ 1356 #ifndef TARGET_WORDS_BIGENDIAN 1357 { 1358 uint32_t *end, *addr; 1359 const size_t swapsize = MIN(bios_size, 0x3e0000); 1360 addr = rom_ptr(FLASH_ADDRESS, swapsize); 1361 if (!addr) { 1362 addr = memory_region_get_ram_ptr(bios); 1363 } 1364 end = (void *)addr + swapsize; 1365 while (addr < end) { 1366 bswap32s(addr); 1367 addr++; 1368 } 1369 } 1370 #endif 1371 } 1372 1373 /* 1374 * Map the BIOS at a 2nd physical location, as on the real board. 1375 * Copy it so that we can patch in the MIPS revision, which cannot be 1376 * handled by an overlapping region as the resulting ROM code subpage 1377 * regions are not executable. 1378 */ 1379 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, 1380 &error_fatal); 1381 if (!rom_copy(memory_region_get_ram_ptr(bios_copy), 1382 FLASH_ADDRESS, BIOS_SIZE)) { 1383 memcpy(memory_region_get_ram_ptr(bios_copy), 1384 memory_region_get_ram_ptr(bios), BIOS_SIZE); 1385 } 1386 memory_region_set_readonly(bios_copy, true); 1387 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); 1388 1389 /* Board ID = 0x420 (Malta Board with CoreLV) */ 1390 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); 1391 1392 /* Northbridge */ 1393 dev = sysbus_create_simple("gt64120", -1, NULL); 1394 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 1395 /* 1396 * The whole address space decoded by the GT-64120A doesn't generate 1397 * exception when accessing invalid memory. Create an empty slot to 1398 * emulate this feature. 1399 */ 1400 empty_slot_init("GT64120", 0, 0x20000000); 1401 1402 /* Southbridge */ 1403 dev = piix4_create(pci_bus, &isa_bus, &smbus); 1404 1405 /* Interrupt controller */ 1406 qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); 1407 1408 /* generate SPD EEPROM data */ 1409 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); 1410 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); 1411 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); 1412 g_free(smbus_eeprom_buf); 1413 1414 /* Super I/O: SMS FDC37M817 */ 1415 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); 1416 1417 /* Network card */ 1418 network_init(pci_bus); 1419 1420 /* Optional PCI video card */ 1421 pci_vga_init(pci_bus); 1422 } 1423 1424 static void mips_malta_instance_init(Object *obj) 1425 { 1426 MaltaState *s = MIPS_MALTA(obj); 1427 1428 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); 1429 clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ 1430 } 1431 1432 static const TypeInfo mips_malta_device = { 1433 .name = TYPE_MIPS_MALTA, 1434 .parent = TYPE_SYS_BUS_DEVICE, 1435 .instance_size = sizeof(MaltaState), 1436 .instance_init = mips_malta_instance_init, 1437 }; 1438 1439 static void mips_malta_machine_init(MachineClass *mc) 1440 { 1441 mc->desc = "MIPS Malta Core LV"; 1442 mc->init = mips_malta_init; 1443 mc->block_default_type = IF_IDE; 1444 mc->max_cpus = 16; 1445 mc->is_default = true; 1446 #ifdef TARGET_MIPS64 1447 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); 1448 #else 1449 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); 1450 #endif 1451 mc->default_ram_id = "mips_malta.ram"; 1452 } 1453 1454 DEFINE_MACHINE("malta", mips_malta_machine_init) 1455 1456 static void mips_malta_register_types(void) 1457 { 1458 type_register_static(&mips_malta_device); 1459 } 1460 1461 type_init(mips_malta_register_types) 1462