1 /* 2 * Status and system control registers for ARM RealView/Versatile boards. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/hw.h" 12 #include "qemu/timer.h" 13 #include "qemu/bitops.h" 14 #include "hw/sysbus.h" 15 #include "hw/arm/primecell.h" 16 #include "sysemu/sysemu.h" 17 18 #define LOCK_VALUE 0xa05f 19 20 #define TYPE_ARM_SYSCTL "realview_sysctl" 21 #define ARM_SYSCTL(obj) \ 22 OBJECT_CHECK(arm_sysctl_state, (obj), TYPE_ARM_SYSCTL) 23 24 typedef struct { 25 SysBusDevice parent_obj; 26 27 MemoryRegion iomem; 28 qemu_irq pl110_mux_ctrl; 29 30 uint32_t sys_id; 31 uint32_t leds; 32 uint16_t lockval; 33 uint32_t cfgdata1; 34 uint32_t cfgdata2; 35 uint32_t flags; 36 uint32_t nvflags; 37 uint32_t resetlevel; 38 uint32_t proc_id; 39 uint32_t sys_mci; 40 uint32_t sys_cfgdata; 41 uint32_t sys_cfgctrl; 42 uint32_t sys_cfgstat; 43 uint32_t sys_clcd; 44 uint32_t mb_clock[6]; 45 uint32_t *db_clock; 46 uint32_t db_num_vsensors; 47 uint32_t *db_voltage; 48 uint32_t db_num_clocks; 49 uint32_t *db_clock_reset; 50 } arm_sysctl_state; 51 52 static const VMStateDescription vmstate_arm_sysctl = { 53 .name = "realview_sysctl", 54 .version_id = 4, 55 .minimum_version_id = 1, 56 .fields = (VMStateField[]) { 57 VMSTATE_UINT32(leds, arm_sysctl_state), 58 VMSTATE_UINT16(lockval, arm_sysctl_state), 59 VMSTATE_UINT32(cfgdata1, arm_sysctl_state), 60 VMSTATE_UINT32(cfgdata2, arm_sysctl_state), 61 VMSTATE_UINT32(flags, arm_sysctl_state), 62 VMSTATE_UINT32(nvflags, arm_sysctl_state), 63 VMSTATE_UINT32(resetlevel, arm_sysctl_state), 64 VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2), 65 VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2), 66 VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2), 67 VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2), 68 VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3), 69 VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4), 70 VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks, 71 4, vmstate_info_uint32, uint32_t), 72 VMSTATE_END_OF_LIST() 73 } 74 }; 75 76 /* The PB926 actually uses a different format for 77 * its SYS_ID register. Fortunately the bits which are 78 * board type on later boards are distinct. 79 */ 80 #define BOARD_ID_PB926 0x100 81 #define BOARD_ID_EB 0x140 82 #define BOARD_ID_PBA8 0x178 83 #define BOARD_ID_PBX 0x182 84 #define BOARD_ID_VEXPRESS 0x190 85 86 static int board_id(arm_sysctl_state *s) 87 { 88 /* Extract the board ID field from the SYS_ID register value */ 89 return (s->sys_id >> 16) & 0xfff; 90 } 91 92 static void arm_sysctl_reset(DeviceState *d) 93 { 94 arm_sysctl_state *s = ARM_SYSCTL(d); 95 int i; 96 97 s->leds = 0; 98 s->lockval = 0; 99 s->cfgdata1 = 0; 100 s->cfgdata2 = 0; 101 s->flags = 0; 102 s->resetlevel = 0; 103 /* Motherboard oscillators (in Hz) */ 104 s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */ 105 s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */ 106 s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */ 107 s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */ 108 s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */ 109 s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */ 110 /* Daughterboard oscillators: reset from property values */ 111 for (i = 0; i < s->db_num_clocks; i++) { 112 s->db_clock[i] = s->db_clock_reset[i]; 113 } 114 if (board_id(s) == BOARD_ID_VEXPRESS) { 115 /* On VExpress this register will RAZ/WI */ 116 s->sys_clcd = 0; 117 } else { 118 /* All others: CLCDID 0x1f, indicating VGA */ 119 s->sys_clcd = 0x1f00; 120 } 121 } 122 123 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset, 124 unsigned size) 125 { 126 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 127 128 switch (offset) { 129 case 0x00: /* ID */ 130 return s->sys_id; 131 case 0x04: /* SW */ 132 /* General purpose hardware switches. 133 We don't have a useful way of exposing these to the user. */ 134 return 0; 135 case 0x08: /* LED */ 136 return s->leds; 137 case 0x20: /* LOCK */ 138 return s->lockval; 139 case 0x0c: /* OSC0 */ 140 case 0x10: /* OSC1 */ 141 case 0x14: /* OSC2 */ 142 case 0x18: /* OSC3 */ 143 case 0x1c: /* OSC4 */ 144 case 0x24: /* 100HZ */ 145 /* ??? Implement these. */ 146 return 0; 147 case 0x28: /* CFGDATA1 */ 148 return s->cfgdata1; 149 case 0x2c: /* CFGDATA2 */ 150 return s->cfgdata2; 151 case 0x30: /* FLAGS */ 152 return s->flags; 153 case 0x38: /* NVFLAGS */ 154 return s->nvflags; 155 case 0x40: /* RESETCTL */ 156 if (board_id(s) == BOARD_ID_VEXPRESS) { 157 /* reserved: RAZ/WI */ 158 return 0; 159 } 160 return s->resetlevel; 161 case 0x44: /* PCICTL */ 162 return 1; 163 case 0x48: /* MCI */ 164 return s->sys_mci; 165 case 0x4c: /* FLASH */ 166 return 0; 167 case 0x50: /* CLCD */ 168 return s->sys_clcd; 169 case 0x54: /* CLCDSER */ 170 return 0; 171 case 0x58: /* BOOTCS */ 172 return 0; 173 case 0x5c: /* 24MHz */ 174 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000, get_ticks_per_sec()); 175 case 0x60: /* MISC */ 176 return 0; 177 case 0x84: /* PROCID0 */ 178 return s->proc_id; 179 case 0x88: /* PROCID1 */ 180 return 0xff000000; 181 case 0x64: /* DMAPSR0 */ 182 case 0x68: /* DMAPSR1 */ 183 case 0x6c: /* DMAPSR2 */ 184 case 0x70: /* IOSEL */ 185 case 0x74: /* PLDCTL */ 186 case 0x80: /* BUSID */ 187 case 0x8c: /* OSCRESET0 */ 188 case 0x90: /* OSCRESET1 */ 189 case 0x94: /* OSCRESET2 */ 190 case 0x98: /* OSCRESET3 */ 191 case 0x9c: /* OSCRESET4 */ 192 case 0xc0: /* SYS_TEST_OSC0 */ 193 case 0xc4: /* SYS_TEST_OSC1 */ 194 case 0xc8: /* SYS_TEST_OSC2 */ 195 case 0xcc: /* SYS_TEST_OSC3 */ 196 case 0xd0: /* SYS_TEST_OSC4 */ 197 return 0; 198 case 0xa0: /* SYS_CFGDATA */ 199 if (board_id(s) != BOARD_ID_VEXPRESS) { 200 goto bad_reg; 201 } 202 return s->sys_cfgdata; 203 case 0xa4: /* SYS_CFGCTRL */ 204 if (board_id(s) != BOARD_ID_VEXPRESS) { 205 goto bad_reg; 206 } 207 return s->sys_cfgctrl; 208 case 0xa8: /* SYS_CFGSTAT */ 209 if (board_id(s) != BOARD_ID_VEXPRESS) { 210 goto bad_reg; 211 } 212 return s->sys_cfgstat; 213 default: 214 bad_reg: 215 qemu_log_mask(LOG_GUEST_ERROR, 216 "arm_sysctl_read: Bad register offset 0x%x\n", 217 (int)offset); 218 return 0; 219 } 220 } 221 222 /* SYS_CFGCTRL functions */ 223 #define SYS_CFG_OSC 1 224 #define SYS_CFG_VOLT 2 225 #define SYS_CFG_AMP 3 226 #define SYS_CFG_TEMP 4 227 #define SYS_CFG_RESET 5 228 #define SYS_CFG_SCC 6 229 #define SYS_CFG_MUXFPGA 7 230 #define SYS_CFG_SHUTDOWN 8 231 #define SYS_CFG_REBOOT 9 232 #define SYS_CFG_DVIMODE 11 233 #define SYS_CFG_POWER 12 234 #define SYS_CFG_ENERGY 13 235 236 /* SYS_CFGCTRL site field values */ 237 #define SYS_CFG_SITE_MB 0 238 #define SYS_CFG_SITE_DB1 1 239 #define SYS_CFG_SITE_DB2 2 240 241 /** 242 * vexpress_cfgctrl_read: 243 * @s: arm_sysctl_state pointer 244 * @dcc, @function, @site, @position, @device: split out values from 245 * SYS_CFGCTRL register 246 * @val: pointer to where to put the read data on success 247 * 248 * Handle a VExpress SYS_CFGCTRL register read. On success, return true and 249 * write the read value to *val. On failure, return false (and val may 250 * or may not be written to). 251 */ 252 static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc, 253 unsigned int function, unsigned int site, 254 unsigned int position, unsigned int device, 255 uint32_t *val) 256 { 257 /* We don't support anything other than DCC 0, board stack position 0 258 * or sites other than motherboard/daughterboard: 259 */ 260 if (dcc != 0 || position != 0 || 261 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 262 goto cfgctrl_unimp; 263 } 264 265 switch (function) { 266 case SYS_CFG_VOLT: 267 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) { 268 *val = s->db_voltage[device]; 269 return true; 270 } 271 if (site == SYS_CFG_SITE_MB && device == 0) { 272 /* There is only one motherboard voltage sensor: 273 * VIO : 3.3V : bus voltage between mother and daughterboard 274 */ 275 *val = 3300000; 276 return true; 277 } 278 break; 279 case SYS_CFG_OSC: 280 if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) { 281 /* motherboard clock */ 282 *val = s->mb_clock[device]; 283 return true; 284 } 285 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 286 /* daughterboard clock */ 287 *val = s->db_clock[device]; 288 return true; 289 } 290 break; 291 default: 292 break; 293 } 294 295 cfgctrl_unimp: 296 qemu_log_mask(LOG_UNIMP, 297 "arm_sysctl: Unimplemented SYS_CFGCTRL read of function " 298 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 299 function, dcc, site, position, device); 300 return false; 301 } 302 303 /** 304 * vexpress_cfgctrl_write: 305 * @s: arm_sysctl_state pointer 306 * @dcc, @function, @site, @position, @device: split out values from 307 * SYS_CFGCTRL register 308 * @val: data to write 309 * 310 * Handle a VExpress SYS_CFGCTRL register write. On success, return true. 311 * On failure, return false. 312 */ 313 static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc, 314 unsigned int function, unsigned int site, 315 unsigned int position, unsigned int device, 316 uint32_t val) 317 { 318 /* We don't support anything other than DCC 0, board stack position 0 319 * or sites other than motherboard/daughterboard: 320 */ 321 if (dcc != 0 || position != 0 || 322 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) { 323 goto cfgctrl_unimp; 324 } 325 326 switch (function) { 327 case SYS_CFG_OSC: 328 if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) { 329 /* motherboard clock */ 330 s->mb_clock[device] = val; 331 return true; 332 } 333 if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) { 334 /* daughterboard clock */ 335 s->db_clock[device] = val; 336 return true; 337 } 338 break; 339 case SYS_CFG_MUXFPGA: 340 if (site == SYS_CFG_SITE_MB && device == 0) { 341 /* Select whether video output comes from motherboard 342 * or daughterboard: log and ignore as QEMU doesn't 343 * support this. 344 */ 345 qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output " 346 "not supported, ignoring\n"); 347 return true; 348 } 349 break; 350 case SYS_CFG_SHUTDOWN: 351 if (site == SYS_CFG_SITE_MB && device == 0) { 352 qemu_system_shutdown_request(); 353 return true; 354 } 355 break; 356 case SYS_CFG_REBOOT: 357 if (site == SYS_CFG_SITE_MB && device == 0) { 358 qemu_system_reset_request(); 359 return true; 360 } 361 break; 362 case SYS_CFG_DVIMODE: 363 if (site == SYS_CFG_SITE_MB && device == 0) { 364 /* Selecting DVI mode is meaningless for QEMU: we will 365 * always display the output correctly according to the 366 * pixel height/width programmed into the CLCD controller. 367 */ 368 return true; 369 } 370 default: 371 break; 372 } 373 374 cfgctrl_unimp: 375 qemu_log_mask(LOG_UNIMP, 376 "arm_sysctl: Unimplemented SYS_CFGCTRL write of function " 377 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n", 378 function, dcc, site, position, device); 379 return false; 380 } 381 382 static void arm_sysctl_write(void *opaque, hwaddr offset, 383 uint64_t val, unsigned size) 384 { 385 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 386 387 switch (offset) { 388 case 0x08: /* LED */ 389 s->leds = val; 390 break; 391 case 0x0c: /* OSC0 */ 392 case 0x10: /* OSC1 */ 393 case 0x14: /* OSC2 */ 394 case 0x18: /* OSC3 */ 395 case 0x1c: /* OSC4 */ 396 /* ??? */ 397 break; 398 case 0x20: /* LOCK */ 399 if (val == LOCK_VALUE) 400 s->lockval = val; 401 else 402 s->lockval = val & 0x7fff; 403 break; 404 case 0x28: /* CFGDATA1 */ 405 /* ??? Need to implement this. */ 406 s->cfgdata1 = val; 407 break; 408 case 0x2c: /* CFGDATA2 */ 409 /* ??? Need to implement this. */ 410 s->cfgdata2 = val; 411 break; 412 case 0x30: /* FLAGSSET */ 413 s->flags |= val; 414 break; 415 case 0x34: /* FLAGSCLR */ 416 s->flags &= ~val; 417 break; 418 case 0x38: /* NVFLAGSSET */ 419 s->nvflags |= val; 420 break; 421 case 0x3c: /* NVFLAGSCLR */ 422 s->nvflags &= ~val; 423 break; 424 case 0x40: /* RESETCTL */ 425 switch (board_id(s)) { 426 case BOARD_ID_PB926: 427 if (s->lockval == LOCK_VALUE) { 428 s->resetlevel = val; 429 if (val & 0x100) { 430 qemu_system_reset_request(); 431 } 432 } 433 break; 434 case BOARD_ID_PBX: 435 case BOARD_ID_PBA8: 436 if (s->lockval == LOCK_VALUE) { 437 s->resetlevel = val; 438 if (val & 0x04) { 439 qemu_system_reset_request(); 440 } 441 } 442 break; 443 case BOARD_ID_VEXPRESS: 444 case BOARD_ID_EB: 445 default: 446 /* reserved: RAZ/WI */ 447 break; 448 } 449 break; 450 case 0x44: /* PCICTL */ 451 /* nothing to do. */ 452 break; 453 case 0x4c: /* FLASH */ 454 break; 455 case 0x50: /* CLCD */ 456 switch (board_id(s)) { 457 case BOARD_ID_PB926: 458 /* On 926 bits 13:8 are R/O, bits 1:0 control 459 * the mux that defines how to interpret the PL110 460 * graphics format, and other bits are r/w but we 461 * don't implement them to do anything. 462 */ 463 s->sys_clcd &= 0x3f00; 464 s->sys_clcd |= val & ~0x3f00; 465 qemu_set_irq(s->pl110_mux_ctrl, val & 3); 466 break; 467 case BOARD_ID_EB: 468 /* The EB is the same except that there is no mux since 469 * the EB has a PL111. 470 */ 471 s->sys_clcd &= 0x3f00; 472 s->sys_clcd |= val & ~0x3f00; 473 break; 474 case BOARD_ID_PBA8: 475 case BOARD_ID_PBX: 476 /* On PBA8 and PBX bit 7 is r/w and all other bits 477 * are either r/o or RAZ/WI. 478 */ 479 s->sys_clcd &= (1 << 7); 480 s->sys_clcd |= val & ~(1 << 7); 481 break; 482 case BOARD_ID_VEXPRESS: 483 default: 484 /* On VExpress this register is unimplemented and will RAZ/WI */ 485 break; 486 } 487 break; 488 case 0x54: /* CLCDSER */ 489 case 0x64: /* DMAPSR0 */ 490 case 0x68: /* DMAPSR1 */ 491 case 0x6c: /* DMAPSR2 */ 492 case 0x70: /* IOSEL */ 493 case 0x74: /* PLDCTL */ 494 case 0x80: /* BUSID */ 495 case 0x84: /* PROCID0 */ 496 case 0x88: /* PROCID1 */ 497 case 0x8c: /* OSCRESET0 */ 498 case 0x90: /* OSCRESET1 */ 499 case 0x94: /* OSCRESET2 */ 500 case 0x98: /* OSCRESET3 */ 501 case 0x9c: /* OSCRESET4 */ 502 break; 503 case 0xa0: /* SYS_CFGDATA */ 504 if (board_id(s) != BOARD_ID_VEXPRESS) { 505 goto bad_reg; 506 } 507 s->sys_cfgdata = val; 508 return; 509 case 0xa4: /* SYS_CFGCTRL */ 510 if (board_id(s) != BOARD_ID_VEXPRESS) { 511 goto bad_reg; 512 } 513 /* Undefined bits [19:18] are RAZ/WI, and writing to 514 * the start bit just triggers the action; it always reads 515 * as zero. 516 */ 517 s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31)); 518 if (val & (1 << 31)) { 519 /* Start bit set -- actually do something */ 520 unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4); 521 unsigned int function = extract32(s->sys_cfgctrl, 20, 6); 522 unsigned int site = extract32(s->sys_cfgctrl, 16, 2); 523 unsigned int position = extract32(s->sys_cfgctrl, 12, 4); 524 unsigned int device = extract32(s->sys_cfgctrl, 0, 12); 525 s->sys_cfgstat = 1; /* complete */ 526 if (s->sys_cfgctrl & (1 << 30)) { 527 if (!vexpress_cfgctrl_write(s, dcc, function, site, position, 528 device, s->sys_cfgdata)) { 529 s->sys_cfgstat |= 2; /* error */ 530 } 531 } else { 532 uint32_t val; 533 if (!vexpress_cfgctrl_read(s, dcc, function, site, position, 534 device, &val)) { 535 s->sys_cfgstat |= 2; /* error */ 536 } else { 537 s->sys_cfgdata = val; 538 } 539 } 540 } 541 s->sys_cfgctrl &= ~(1 << 31); 542 return; 543 case 0xa8: /* SYS_CFGSTAT */ 544 if (board_id(s) != BOARD_ID_VEXPRESS) { 545 goto bad_reg; 546 } 547 s->sys_cfgstat = val & 3; 548 return; 549 default: 550 bad_reg: 551 qemu_log_mask(LOG_GUEST_ERROR, 552 "arm_sysctl_write: Bad register offset 0x%x\n", 553 (int)offset); 554 return; 555 } 556 } 557 558 static const MemoryRegionOps arm_sysctl_ops = { 559 .read = arm_sysctl_read, 560 .write = arm_sysctl_write, 561 .endianness = DEVICE_NATIVE_ENDIAN, 562 }; 563 564 static void arm_sysctl_gpio_set(void *opaque, int line, int level) 565 { 566 arm_sysctl_state *s = (arm_sysctl_state *)opaque; 567 switch (line) { 568 case ARM_SYSCTL_GPIO_MMC_WPROT: 569 { 570 /* For PB926 and EB write-protect is bit 2 of SYS_MCI; 571 * for all later boards it is bit 1. 572 */ 573 int bit = 2; 574 if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) { 575 bit = 4; 576 } 577 s->sys_mci &= ~bit; 578 if (level) { 579 s->sys_mci |= bit; 580 } 581 break; 582 } 583 case ARM_SYSCTL_GPIO_MMC_CARDIN: 584 s->sys_mci &= ~1; 585 if (level) { 586 s->sys_mci |= 1; 587 } 588 break; 589 } 590 } 591 592 static void arm_sysctl_init(Object *obj) 593 { 594 DeviceState *dev = DEVICE(obj); 595 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 596 arm_sysctl_state *s = ARM_SYSCTL(obj); 597 598 memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s, 599 "arm-sysctl", 0x1000); 600 sysbus_init_mmio(sd, &s->iomem); 601 qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2); 602 qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1); 603 } 604 605 static void arm_sysctl_realize(DeviceState *d, Error **errp) 606 { 607 arm_sysctl_state *s = ARM_SYSCTL(d); 608 609 s->db_clock = g_new0(uint32_t, s->db_num_clocks); 610 } 611 612 static void arm_sysctl_finalize(Object *obj) 613 { 614 arm_sysctl_state *s = ARM_SYSCTL(obj); 615 616 g_free(s->db_voltage); 617 g_free(s->db_clock); 618 g_free(s->db_clock_reset); 619 } 620 621 static Property arm_sysctl_properties[] = { 622 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), 623 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0), 624 /* Daughterboard power supply voltages (as reported via SYS_CFG) */ 625 DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors, 626 db_voltage, qdev_prop_uint32, uint32_t), 627 /* Daughterboard clock reset values (as reported via SYS_CFG) */ 628 DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks, 629 db_clock_reset, qdev_prop_uint32, uint32_t), 630 DEFINE_PROP_END_OF_LIST(), 631 }; 632 633 static void arm_sysctl_class_init(ObjectClass *klass, void *data) 634 { 635 DeviceClass *dc = DEVICE_CLASS(klass); 636 637 dc->realize = arm_sysctl_realize; 638 dc->reset = arm_sysctl_reset; 639 dc->vmsd = &vmstate_arm_sysctl; 640 dc->props = arm_sysctl_properties; 641 } 642 643 static const TypeInfo arm_sysctl_info = { 644 .name = TYPE_ARM_SYSCTL, 645 .parent = TYPE_SYS_BUS_DEVICE, 646 .instance_size = sizeof(arm_sysctl_state), 647 .instance_init = arm_sysctl_init, 648 .instance_finalize = arm_sysctl_finalize, 649 .class_init = arm_sysctl_class_init, 650 }; 651 652 static void arm_sysctl_register_types(void) 653 { 654 type_register_static(&arm_sysctl_info); 655 } 656 657 type_init(arm_sysctl_register_types) 658