1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/qdev-properties.h" 15 #include "qapi/error.h" 16 #include "qapi/visitor.h" 17 #include "qemu/bitops.h" 18 #include "qemu/log.h" 19 #include "trace.h" 20 21 #define TO_REG(offset) ((offset) >> 2) 22 23 #define PROT_KEY TO_REG(0x00) 24 #define SYS_RST_CTRL TO_REG(0x04) 25 #define CLK_SEL TO_REG(0x08) 26 #define CLK_STOP_CTRL TO_REG(0x0C) 27 #define FREQ_CNTR_CTRL TO_REG(0x10) 28 #define FREQ_CNTR_EVAL TO_REG(0x14) 29 #define IRQ_CTRL TO_REG(0x18) 30 #define D2PLL_PARAM TO_REG(0x1C) 31 #define MPLL_PARAM TO_REG(0x20) 32 #define HPLL_PARAM TO_REG(0x24) 33 #define FREQ_CNTR_RANGE TO_REG(0x28) 34 #define MISC_CTRL1 TO_REG(0x2C) 35 #define PCI_CTRL1 TO_REG(0x30) 36 #define PCI_CTRL2 TO_REG(0x34) 37 #define PCI_CTRL3 TO_REG(0x38) 38 #define SYS_RST_STATUS TO_REG(0x3C) 39 #define SOC_SCRATCH1 TO_REG(0x40) 40 #define SOC_SCRATCH2 TO_REG(0x44) 41 #define MAC_CLK_DELAY TO_REG(0x48) 42 #define MISC_CTRL2 TO_REG(0x4C) 43 #define VGA_SCRATCH1 TO_REG(0x50) 44 #define VGA_SCRATCH2 TO_REG(0x54) 45 #define VGA_SCRATCH3 TO_REG(0x58) 46 #define VGA_SCRATCH4 TO_REG(0x5C) 47 #define VGA_SCRATCH5 TO_REG(0x60) 48 #define VGA_SCRATCH6 TO_REG(0x64) 49 #define VGA_SCRATCH7 TO_REG(0x68) 50 #define VGA_SCRATCH8 TO_REG(0x6C) 51 #define HW_STRAP1 TO_REG(0x70) 52 #define RNG_CTRL TO_REG(0x74) 53 #define RNG_DATA TO_REG(0x78) 54 #define SILICON_REV TO_REG(0x7C) 55 #define PINMUX_CTRL1 TO_REG(0x80) 56 #define PINMUX_CTRL2 TO_REG(0x84) 57 #define PINMUX_CTRL3 TO_REG(0x88) 58 #define PINMUX_CTRL4 TO_REG(0x8C) 59 #define PINMUX_CTRL5 TO_REG(0x90) 60 #define PINMUX_CTRL6 TO_REG(0x94) 61 #define WDT_RST_CTRL TO_REG(0x9C) 62 #define PINMUX_CTRL7 TO_REG(0xA0) 63 #define PINMUX_CTRL8 TO_REG(0xA4) 64 #define PINMUX_CTRL9 TO_REG(0xA8) 65 #define WAKEUP_EN TO_REG(0xC0) 66 #define WAKEUP_CTRL TO_REG(0xC4) 67 #define HW_STRAP2 TO_REG(0xD0) 68 #define FREE_CNTR4 TO_REG(0xE0) 69 #define FREE_CNTR4_EXT TO_REG(0xE4) 70 #define CPU2_CTRL TO_REG(0x100) 71 #define CPU2_BASE_SEG1 TO_REG(0x104) 72 #define CPU2_BASE_SEG2 TO_REG(0x108) 73 #define CPU2_BASE_SEG3 TO_REG(0x10C) 74 #define CPU2_BASE_SEG4 TO_REG(0x110) 75 #define CPU2_BASE_SEG5 TO_REG(0x114) 76 #define CPU2_CACHE_CTRL TO_REG(0x118) 77 #define UART_HPLL_CLK TO_REG(0x160) 78 #define PCIE_CTRL TO_REG(0x180) 79 #define BMC_MMIO_CTRL TO_REG(0x184) 80 #define RELOC_DECODE_BASE1 TO_REG(0x188) 81 #define RELOC_DECODE_BASE2 TO_REG(0x18C) 82 #define MAILBOX_DECODE_BASE TO_REG(0x190) 83 #define SRAM_DECODE_BASE1 TO_REG(0x194) 84 #define SRAM_DECODE_BASE2 TO_REG(0x198) 85 #define BMC_REV TO_REG(0x19C) 86 #define BMC_DEV_ID TO_REG(0x1A4) 87 88 #define PROT_KEY_UNLOCK 0x1688A8A8 89 #define SCU_IO_REGION_SIZE 0x20000 90 91 #define AST2400_A0_SILICON_REV 0x02000303U 92 93 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { 94 [SYS_RST_CTRL] = 0xFFCFFEDCU, 95 [CLK_SEL] = 0xF3F40000U, 96 [CLK_STOP_CTRL] = 0x19FC3E8BU, 97 [D2PLL_PARAM] = 0x00026108U, 98 [MPLL_PARAM] = 0x00030291U, 99 [HPLL_PARAM] = 0x00000291U, 100 [MISC_CTRL1] = 0x00000010U, 101 [PCI_CTRL1] = 0x20001A03U, 102 [PCI_CTRL2] = 0x20001A03U, 103 [PCI_CTRL3] = 0x04000030U, 104 [SYS_RST_STATUS] = 0x00000001U, 105 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 106 [MISC_CTRL2] = 0x00000023U, 107 [RNG_CTRL] = 0x0000000EU, 108 [PINMUX_CTRL2] = 0x0000F000U, 109 [PINMUX_CTRL3] = 0x01000000U, 110 [PINMUX_CTRL4] = 0x000000FFU, 111 [PINMUX_CTRL5] = 0x0000A000U, 112 [WDT_RST_CTRL] = 0x003FFFF3U, 113 [PINMUX_CTRL8] = 0xFFFF0000U, 114 [PINMUX_CTRL9] = 0x000FFFFFU, 115 [FREE_CNTR4] = 0x000000FFU, 116 [FREE_CNTR4_EXT] = 0x000000FFU, 117 [CPU2_BASE_SEG1] = 0x80000000U, 118 [CPU2_BASE_SEG4] = 0x1E600000U, 119 [CPU2_BASE_SEG5] = 0xC0000000U, 120 [UART_HPLL_CLK] = 0x00001903U, 121 [PCIE_CTRL] = 0x0000007BU, 122 [BMC_DEV_ID] = 0x00002402U 123 }; 124 125 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) 126 { 127 AspeedSCUState *s = ASPEED_SCU(opaque); 128 int reg = TO_REG(offset); 129 130 if (reg >= ARRAY_SIZE(s->regs)) { 131 qemu_log_mask(LOG_GUEST_ERROR, 132 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 133 __func__, offset); 134 return 0; 135 } 136 137 switch (reg) { 138 case WAKEUP_EN: 139 qemu_log_mask(LOG_GUEST_ERROR, 140 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", 141 __func__, offset); 142 break; 143 } 144 145 return s->regs[reg]; 146 } 147 148 static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, 149 unsigned size) 150 { 151 AspeedSCUState *s = ASPEED_SCU(opaque); 152 int reg = TO_REG(offset); 153 154 if (reg >= ARRAY_SIZE(s->regs)) { 155 qemu_log_mask(LOG_GUEST_ERROR, 156 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 157 __func__, offset); 158 return; 159 } 160 161 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 162 s->regs[PROT_KEY] != PROT_KEY_UNLOCK) { 163 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 164 return; 165 } 166 167 trace_aspeed_scu_write(offset, size, data); 168 169 switch (reg) { 170 case FREQ_CNTR_EVAL: 171 case VGA_SCRATCH1 ... VGA_SCRATCH8: 172 case RNG_DATA: 173 case SILICON_REV: 174 case FREE_CNTR4: 175 case FREE_CNTR4_EXT: 176 qemu_log_mask(LOG_GUEST_ERROR, 177 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 178 __func__, offset); 179 return; 180 } 181 182 s->regs[reg] = data; 183 } 184 185 static const MemoryRegionOps aspeed_scu_ops = { 186 .read = aspeed_scu_read, 187 .write = aspeed_scu_write, 188 .endianness = DEVICE_LITTLE_ENDIAN, 189 .valid.min_access_size = 4, 190 .valid.max_access_size = 4, 191 .valid.unaligned = false, 192 }; 193 194 static void aspeed_scu_reset(DeviceState *dev) 195 { 196 AspeedSCUState *s = ASPEED_SCU(dev); 197 const uint32_t *reset; 198 199 switch (s->silicon_rev) { 200 case AST2400_A0_SILICON_REV: 201 reset = ast2400_a0_resets; 202 break; 203 default: 204 g_assert_not_reached(); 205 } 206 207 memcpy(s->regs, reset, sizeof(s->regs)); 208 s->regs[SILICON_REV] = s->silicon_rev; 209 s->regs[HW_STRAP1] = s->hw_strap1; 210 s->regs[HW_STRAP2] = s->hw_strap2; 211 } 212 213 static uint32_t aspeed_silicon_revs[] = { AST2400_A0_SILICON_REV, }; 214 215 static bool is_supported_silicon_rev(uint32_t silicon_rev) 216 { 217 int i; 218 219 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) { 220 if (silicon_rev == aspeed_silicon_revs[i]) { 221 return true; 222 } 223 } 224 225 return false; 226 } 227 228 static void aspeed_scu_realize(DeviceState *dev, Error **errp) 229 { 230 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 231 AspeedSCUState *s = ASPEED_SCU(dev); 232 233 if (!is_supported_silicon_rev(s->silicon_rev)) { 234 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, 235 s->silicon_rev); 236 return; 237 } 238 239 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s, 240 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); 241 242 sysbus_init_mmio(sbd, &s->iomem); 243 } 244 245 static const VMStateDescription vmstate_aspeed_scu = { 246 .name = "aspeed.scu", 247 .version_id = 1, 248 .minimum_version_id = 1, 249 .fields = (VMStateField[]) { 250 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS), 251 VMSTATE_END_OF_LIST() 252 } 253 }; 254 255 static Property aspeed_scu_properties[] = { 256 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), 257 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), 258 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap1, 0), 259 DEFINE_PROP_END_OF_LIST(), 260 }; 261 262 static void aspeed_scu_class_init(ObjectClass *klass, void *data) 263 { 264 DeviceClass *dc = DEVICE_CLASS(klass); 265 dc->realize = aspeed_scu_realize; 266 dc->reset = aspeed_scu_reset; 267 dc->desc = "ASPEED System Control Unit"; 268 dc->vmsd = &vmstate_aspeed_scu; 269 dc->props = aspeed_scu_properties; 270 } 271 272 static const TypeInfo aspeed_scu_info = { 273 .name = TYPE_ASPEED_SCU, 274 .parent = TYPE_SYS_BUS_DEVICE, 275 .instance_size = sizeof(AspeedSCUState), 276 .class_init = aspeed_scu_class_init, 277 }; 278 279 static void aspeed_scu_register_types(void) 280 { 281 type_register_static(&aspeed_scu_info); 282 } 283 284 type_init(aspeed_scu_register_types); 285