1 /* 2 * auxbus.c 3 * 4 * Copyright 2015 : GreenSocs Ltd 5 * http://www.greensocs.com/ , email: info@greensocs.com 6 * 7 * Developed by : 8 * Frederic Konrad <fred.konrad@greensocs.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option)any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 * 23 */ 24 25 /* 26 * This is an implementation of the AUX bus for VESA Display Port v1.1a. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qemu/units.h" 31 #include "qemu/log.h" 32 #include "qemu/module.h" 33 #include "hw/misc/auxbus.h" 34 #include "hw/i2c/i2c.h" 35 #include "monitor/monitor.h" 36 #include "qapi/error.h" 37 38 #ifndef DEBUG_AUX 39 #define DEBUG_AUX 0 40 #endif 41 42 #define DPRINTF(fmt, ...) do { \ 43 if (DEBUG_AUX) { \ 44 qemu_log("aux: " fmt , ## __VA_ARGS__); \ 45 } \ 46 } while (0) 47 48 49 static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent); 50 static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge); 51 52 /* aux-bus implementation (internal not public) */ 53 static void aux_bus_class_init(ObjectClass *klass, void *data) 54 { 55 BusClass *k = BUS_CLASS(klass); 56 57 /* AUXSlave has an MMIO so we need to change the way we print information 58 * in monitor. 59 */ 60 k->print_dev = aux_slave_dev_print; 61 } 62 63 AUXBus *aux_bus_init(DeviceState *parent, const char *name) 64 { 65 AUXBus *bus; 66 Object *auxtoi2c; 67 68 bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name)); 69 auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c", 70 &error_abort, NULL); 71 72 bus->bridge = AUXTOI2C(auxtoi2c); 73 74 /* Memory related. */ 75 bus->aux_io = g_malloc(sizeof(*bus->aux_io)); 76 memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 1 * MiB); 77 address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io"); 78 return bus; 79 } 80 81 void aux_bus_realize(AUXBus *bus) 82 { 83 qdev_realize(DEVICE(bus->bridge), BUS(bus), &error_fatal); 84 } 85 86 void aux_map_slave(AUXSlave *aux_dev, hwaddr addr) 87 { 88 DeviceState *dev = DEVICE(aux_dev); 89 AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev)); 90 memory_region_add_subregion(bus->aux_io, addr, aux_dev->mmio); 91 } 92 93 static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev) 94 { 95 return (dev == DEVICE(bus->bridge)); 96 } 97 98 I2CBus *aux_get_i2c_bus(AUXBus *bus) 99 { 100 return aux_bridge_get_i2c_bus(bus->bridge); 101 } 102 103 AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address, 104 uint8_t len, uint8_t *data) 105 { 106 AUXReply ret = AUX_NACK; 107 I2CBus *i2c_bus = aux_get_i2c_bus(bus); 108 size_t i; 109 110 DPRINTF("request at address 0x%" PRIX32 ", command %u, len %u\n", address, 111 cmd, len); 112 113 switch (cmd) { 114 /* 115 * Forward the request on the AUX bus.. 116 */ 117 case WRITE_AUX: 118 case READ_AUX: 119 for (i = 0; i < len; i++) { 120 if (!address_space_rw(&bus->aux_addr_space, address++, 121 MEMTXATTRS_UNSPECIFIED, data++, 1, 122 cmd == WRITE_AUX)) { 123 ret = AUX_I2C_ACK; 124 } else { 125 ret = AUX_NACK; 126 break; 127 } 128 } 129 break; 130 /* 131 * Classic I2C transactions.. 132 */ 133 case READ_I2C: 134 if (i2c_bus_busy(i2c_bus)) { 135 i2c_end_transfer(i2c_bus); 136 } 137 138 if (i2c_start_transfer(i2c_bus, address, true)) { 139 ret = AUX_I2C_NACK; 140 break; 141 } 142 143 ret = AUX_I2C_ACK; 144 while (len > 0) { 145 if (i2c_send_recv(i2c_bus, data++, false) < 0) { 146 ret = AUX_I2C_NACK; 147 break; 148 } 149 len--; 150 } 151 i2c_end_transfer(i2c_bus); 152 break; 153 case WRITE_I2C: 154 if (i2c_bus_busy(i2c_bus)) { 155 i2c_end_transfer(i2c_bus); 156 } 157 158 if (i2c_start_transfer(i2c_bus, address, false)) { 159 ret = AUX_I2C_NACK; 160 break; 161 } 162 163 ret = AUX_I2C_ACK; 164 while (len > 0) { 165 if (i2c_send_recv(i2c_bus, data++, true) < 0) { 166 ret = AUX_I2C_NACK; 167 break; 168 } 169 len--; 170 } 171 i2c_end_transfer(i2c_bus); 172 break; 173 /* 174 * I2C MOT transactions. 175 * 176 * Here we send a start when: 177 * - We didn't start transaction yet. 178 * - We had a READ and we do a WRITE. 179 * - We changed the address. 180 */ 181 case WRITE_I2C_MOT: 182 ret = AUX_I2C_NACK; 183 if (!i2c_bus_busy(i2c_bus)) { 184 /* 185 * No transactions started.. 186 */ 187 if (i2c_start_transfer(i2c_bus, address, false)) { 188 break; 189 } 190 } else if ((address != bus->last_i2c_address) || 191 (bus->last_transaction != cmd)) { 192 /* 193 * Transaction started but we need to restart.. 194 */ 195 i2c_end_transfer(i2c_bus); 196 if (i2c_start_transfer(i2c_bus, address, false)) { 197 break; 198 } 199 } 200 201 bus->last_transaction = cmd; 202 bus->last_i2c_address = address; 203 while (len > 0) { 204 if (i2c_send_recv(i2c_bus, data++, true) < 0) { 205 i2c_end_transfer(i2c_bus); 206 break; 207 } 208 len--; 209 } 210 if (len == 0) { 211 ret = AUX_I2C_ACK; 212 } 213 break; 214 case READ_I2C_MOT: 215 ret = AUX_I2C_NACK; 216 if (!i2c_bus_busy(i2c_bus)) { 217 /* 218 * No transactions started.. 219 */ 220 if (i2c_start_transfer(i2c_bus, address, true)) { 221 break; 222 } 223 } else if ((address != bus->last_i2c_address) || 224 (bus->last_transaction != cmd)) { 225 /* 226 * Transaction started but we need to restart.. 227 */ 228 i2c_end_transfer(i2c_bus); 229 if (i2c_start_transfer(i2c_bus, address, true)) { 230 break; 231 } 232 } 233 234 bus->last_transaction = cmd; 235 bus->last_i2c_address = address; 236 while (len > 0) { 237 if (i2c_send_recv(i2c_bus, data++, false) < 0) { 238 i2c_end_transfer(i2c_bus); 239 break; 240 } 241 len--; 242 } 243 if (len == 0) { 244 ret = AUX_I2C_ACK; 245 } 246 break; 247 default: 248 qemu_log_mask(LOG_UNIMP, "AUX cmd=%u not implemented\n", cmd); 249 return AUX_NACK; 250 } 251 252 DPRINTF("reply: %u\n", ret); 253 return ret; 254 } 255 256 static const TypeInfo aux_bus_info = { 257 .name = TYPE_AUX_BUS, 258 .parent = TYPE_BUS, 259 .instance_size = sizeof(AUXBus), 260 .class_init = aux_bus_class_init 261 }; 262 263 /* aux-i2c implementation (internal not public) */ 264 struct AUXTOI2CState { 265 /*< private >*/ 266 DeviceState parent_obj; 267 268 /*< public >*/ 269 I2CBus *i2c_bus; 270 }; 271 272 static void aux_bridge_class_init(ObjectClass *oc, void *data) 273 { 274 DeviceClass *dc = DEVICE_CLASS(oc); 275 276 /* This device is private and is created only once for each 277 * aux-bus in aux_bus_init(..). So don't allow the user to add one. 278 */ 279 dc->user_creatable = false; 280 } 281 282 static void aux_bridge_init(Object *obj) 283 { 284 AUXTOI2CState *s = AUXTOI2C(obj); 285 286 s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c"); 287 } 288 289 static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge) 290 { 291 return bridge->i2c_bus; 292 } 293 294 static const TypeInfo aux_to_i2c_type_info = { 295 .name = TYPE_AUXTOI2C, 296 .parent = TYPE_AUX_SLAVE, 297 .class_init = aux_bridge_class_init, 298 .instance_size = sizeof(AUXTOI2CState), 299 .instance_init = aux_bridge_init 300 }; 301 302 /* aux-slave implementation */ 303 static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent) 304 { 305 AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev)); 306 AUXSlave *s; 307 308 /* Don't print anything if the device is I2C "bridge". */ 309 if (aux_bus_is_bridge(bus, dev)) { 310 return; 311 } 312 313 s = AUX_SLAVE(dev); 314 315 monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", 316 indent, "", 317 object_property_get_uint(OBJECT(s->mmio), "addr", NULL), 318 memory_region_size(s->mmio)); 319 } 320 321 void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio) 322 { 323 assert(!aux_slave->mmio); 324 aux_slave->mmio = mmio; 325 } 326 327 static void aux_slave_class_init(ObjectClass *klass, void *data) 328 { 329 DeviceClass *k = DEVICE_CLASS(klass); 330 331 set_bit(DEVICE_CATEGORY_MISC, k->categories); 332 k->bus_type = TYPE_AUX_BUS; 333 } 334 335 static const TypeInfo aux_slave_type_info = { 336 .name = TYPE_AUX_SLAVE, 337 .parent = TYPE_DEVICE, 338 .instance_size = sizeof(AUXSlave), 339 .abstract = true, 340 .class_init = aux_slave_class_init, 341 }; 342 343 static void aux_register_types(void) 344 { 345 type_register_static(&aux_bus_info); 346 type_register_static(&aux_slave_type_info); 347 type_register_static(&aux_to_i2c_type_info); 348 } 349 350 type_init(aux_register_types) 351