1 /* 2 * auxbus.c 3 * 4 * Copyright 2015 : GreenSocs Ltd 5 * http://www.greensocs.com/ , email: info@greensocs.com 6 * 7 * Developed by : 8 * Frederic Konrad <fred.konrad@greensocs.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option)any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 * 23 */ 24 25 /* 26 * This is an implementation of the AUX bus for VESA Display Port v1.1a. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qemu/units.h" 31 #include "qemu/log.h" 32 #include "qemu/module.h" 33 #include "hw/misc/auxbus.h" 34 #include "hw/i2c/i2c.h" 35 #include "monitor/monitor.h" 36 #include "qapi/error.h" 37 38 #ifndef DEBUG_AUX 39 #define DEBUG_AUX 0 40 #endif 41 42 #define DPRINTF(fmt, ...) do { \ 43 if (DEBUG_AUX) { \ 44 qemu_log("aux: " fmt , ## __VA_ARGS__); \ 45 } \ 46 } while (0) 47 48 49 static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent); 50 static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge); 51 52 /* aux-bus implementation (internal not public) */ 53 static void aux_bus_class_init(ObjectClass *klass, void *data) 54 { 55 BusClass *k = BUS_CLASS(klass); 56 57 /* AUXSlave has an MMIO so we need to change the way we print information 58 * in monitor. 59 */ 60 k->print_dev = aux_slave_dev_print; 61 } 62 63 AUXBus *aux_bus_init(DeviceState *parent, const char *name) 64 { 65 AUXBus *bus; 66 Object *auxtoi2c; 67 68 bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name)); 69 auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c", 70 &error_abort, NULL); 71 72 bus->bridge = AUXTOI2C(auxtoi2c); 73 74 /* Memory related. */ 75 bus->aux_io = g_malloc(sizeof(*bus->aux_io)); 76 memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 1 * MiB); 77 address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io"); 78 return bus; 79 } 80 81 void aux_bus_realize(AUXBus *bus) 82 { 83 qdev_realize(DEVICE(bus->bridge), BUS(bus), &error_fatal); 84 } 85 86 void aux_map_slave(AUXSlave *aux_dev, hwaddr addr) 87 { 88 DeviceState *dev = DEVICE(aux_dev); 89 AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev)); 90 memory_region_add_subregion(bus->aux_io, addr, aux_dev->mmio); 91 } 92 93 static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev) 94 { 95 return (dev == DEVICE(bus->bridge)); 96 } 97 98 I2CBus *aux_get_i2c_bus(AUXBus *bus) 99 { 100 return aux_bridge_get_i2c_bus(bus->bridge); 101 } 102 103 AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address, 104 uint8_t len, uint8_t *data) 105 { 106 AUXReply ret = AUX_NACK; 107 I2CBus *i2c_bus = aux_get_i2c_bus(bus); 108 size_t i; 109 bool is_write = false; 110 111 DPRINTF("request at address 0x%" PRIX32 ", command %u, len %u\n", address, 112 cmd, len); 113 114 switch (cmd) { 115 /* 116 * Forward the request on the AUX bus.. 117 */ 118 case WRITE_AUX: 119 case READ_AUX: 120 is_write = cmd == READ_AUX ? false : true; 121 for (i = 0; i < len; i++) { 122 if (!address_space_rw(&bus->aux_addr_space, address++, 123 MEMTXATTRS_UNSPECIFIED, data++, 1, 124 is_write)) { 125 ret = AUX_I2C_ACK; 126 } else { 127 ret = AUX_NACK; 128 break; 129 } 130 } 131 break; 132 /* 133 * Classic I2C transactions.. 134 */ 135 case READ_I2C: 136 is_write = cmd == READ_I2C ? false : true; 137 if (i2c_bus_busy(i2c_bus)) { 138 i2c_end_transfer(i2c_bus); 139 } 140 141 if (i2c_start_transfer(i2c_bus, address, !is_write)) { 142 ret = AUX_I2C_NACK; 143 break; 144 } 145 146 ret = AUX_I2C_ACK; 147 while (len > 0) { 148 if (i2c_send_recv(i2c_bus, data++, is_write) < 0) { 149 ret = AUX_I2C_NACK; 150 break; 151 } 152 len--; 153 } 154 i2c_end_transfer(i2c_bus); 155 break; 156 case WRITE_I2C: 157 is_write = cmd == READ_I2C ? false : true; 158 if (i2c_bus_busy(i2c_bus)) { 159 i2c_end_transfer(i2c_bus); 160 } 161 162 if (i2c_start_transfer(i2c_bus, address, !is_write)) { 163 ret = AUX_I2C_NACK; 164 break; 165 } 166 167 ret = AUX_I2C_ACK; 168 while (len > 0) { 169 if (i2c_send_recv(i2c_bus, data++, is_write) < 0) { 170 ret = AUX_I2C_NACK; 171 break; 172 } 173 len--; 174 } 175 i2c_end_transfer(i2c_bus); 176 break; 177 /* 178 * I2C MOT transactions. 179 * 180 * Here we send a start when: 181 * - We didn't start transaction yet. 182 * - We had a READ and we do a WRITE. 183 * - We changed the address. 184 */ 185 case WRITE_I2C_MOT: 186 is_write = cmd == READ_I2C_MOT ? false : true; 187 ret = AUX_I2C_NACK; 188 if (!i2c_bus_busy(i2c_bus)) { 189 /* 190 * No transactions started.. 191 */ 192 if (i2c_start_transfer(i2c_bus, address, !is_write)) { 193 break; 194 } 195 } else if ((address != bus->last_i2c_address) || 196 (bus->last_transaction != cmd)) { 197 /* 198 * Transaction started but we need to restart.. 199 */ 200 i2c_end_transfer(i2c_bus); 201 if (i2c_start_transfer(i2c_bus, address, !is_write)) { 202 break; 203 } 204 } 205 206 bus->last_transaction = cmd; 207 bus->last_i2c_address = address; 208 while (len > 0) { 209 if (i2c_send_recv(i2c_bus, data++, is_write) < 0) { 210 i2c_end_transfer(i2c_bus); 211 break; 212 } 213 len--; 214 } 215 if (len == 0) { 216 ret = AUX_I2C_ACK; 217 } 218 break; 219 case READ_I2C_MOT: 220 is_write = cmd == READ_I2C_MOT ? false : true; 221 ret = AUX_I2C_NACK; 222 if (!i2c_bus_busy(i2c_bus)) { 223 /* 224 * No transactions started.. 225 */ 226 if (i2c_start_transfer(i2c_bus, address, !is_write)) { 227 break; 228 } 229 } else if ((address != bus->last_i2c_address) || 230 (bus->last_transaction != cmd)) { 231 /* 232 * Transaction started but we need to restart.. 233 */ 234 i2c_end_transfer(i2c_bus); 235 if (i2c_start_transfer(i2c_bus, address, !is_write)) { 236 break; 237 } 238 } 239 240 bus->last_transaction = cmd; 241 bus->last_i2c_address = address; 242 while (len > 0) { 243 if (i2c_send_recv(i2c_bus, data++, is_write) < 0) { 244 i2c_end_transfer(i2c_bus); 245 break; 246 } 247 len--; 248 } 249 if (len == 0) { 250 ret = AUX_I2C_ACK; 251 } 252 break; 253 default: 254 qemu_log_mask(LOG_UNIMP, "AUX cmd=%u not implemented\n", cmd); 255 return AUX_NACK; 256 } 257 258 DPRINTF("reply: %u\n", ret); 259 return ret; 260 } 261 262 static const TypeInfo aux_bus_info = { 263 .name = TYPE_AUX_BUS, 264 .parent = TYPE_BUS, 265 .instance_size = sizeof(AUXBus), 266 .class_init = aux_bus_class_init 267 }; 268 269 /* aux-i2c implementation (internal not public) */ 270 struct AUXTOI2CState { 271 /*< private >*/ 272 DeviceState parent_obj; 273 274 /*< public >*/ 275 I2CBus *i2c_bus; 276 }; 277 278 static void aux_bridge_class_init(ObjectClass *oc, void *data) 279 { 280 DeviceClass *dc = DEVICE_CLASS(oc); 281 282 /* This device is private and is created only once for each 283 * aux-bus in aux_bus_init(..). So don't allow the user to add one. 284 */ 285 dc->user_creatable = false; 286 } 287 288 static void aux_bridge_init(Object *obj) 289 { 290 AUXTOI2CState *s = AUXTOI2C(obj); 291 292 s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c"); 293 } 294 295 static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge) 296 { 297 return bridge->i2c_bus; 298 } 299 300 static const TypeInfo aux_to_i2c_type_info = { 301 .name = TYPE_AUXTOI2C, 302 .parent = TYPE_AUX_SLAVE, 303 .class_init = aux_bridge_class_init, 304 .instance_size = sizeof(AUXTOI2CState), 305 .instance_init = aux_bridge_init 306 }; 307 308 /* aux-slave implementation */ 309 static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent) 310 { 311 AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev)); 312 AUXSlave *s; 313 314 /* Don't print anything if the device is I2C "bridge". */ 315 if (aux_bus_is_bridge(bus, dev)) { 316 return; 317 } 318 319 s = AUX_SLAVE(dev); 320 321 monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", 322 indent, "", 323 object_property_get_uint(OBJECT(s->mmio), "addr", NULL), 324 memory_region_size(s->mmio)); 325 } 326 327 void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio) 328 { 329 assert(!aux_slave->mmio); 330 aux_slave->mmio = mmio; 331 } 332 333 static void aux_slave_class_init(ObjectClass *klass, void *data) 334 { 335 DeviceClass *k = DEVICE_CLASS(klass); 336 337 set_bit(DEVICE_CATEGORY_MISC, k->categories); 338 k->bus_type = TYPE_AUX_BUS; 339 } 340 341 static const TypeInfo aux_slave_type_info = { 342 .name = TYPE_AUX_SLAVE, 343 .parent = TYPE_DEVICE, 344 .instance_size = sizeof(AUXSlave), 345 .abstract = true, 346 .class_init = aux_slave_class_init, 347 }; 348 349 static void aux_register_types(void) 350 { 351 type_register_static(&aux_bus_info); 352 type_register_static(&aux_slave_type_info); 353 type_register_static(&aux_to_i2c_type_info); 354 } 355 356 type_init(aux_register_types) 357