1 /* 2 * Exynos4210 Clock Controller Emulation 3 * 4 * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/sysbus.h" 22 #include "migration/vmstate.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "qom/object.h" 26 27 #define TYPE_EXYNOS4210_CLK "exynos4210.clk" 28 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210ClkState, EXYNOS4210_CLK) 29 30 #define CLK_PLL_LOCKED BIT(29) 31 32 #define EXYNOS4210_CLK_REGS_MEM_SIZE 0x15104 33 34 typedef struct Exynos4210Reg { 35 const char *name; /* for debug only */ 36 uint32_t offset; 37 uint32_t reset_value; 38 } Exynos4210Reg; 39 40 /* Clock controller register base: 0x10030000 */ 41 static const Exynos4210Reg exynos4210_clk_regs[] = { 42 {"EPLL_LOCK", 0xc010, 0x00000fff}, 43 {"VPLL_LOCK", 0xc020, 0x00000fff}, 44 {"EPLL_CON0", 0xc110, 0x00300301 | CLK_PLL_LOCKED}, 45 {"EPLL_CON1", 0xc114, 0x00000000}, 46 {"VPLL_CON0", 0xc120, 0x00240201 | CLK_PLL_LOCKED}, 47 {"VPLL_CON1", 0xc124, 0x66010464}, 48 {"APLL_LOCK", 0x14000, 0x00000fff}, 49 {"MPLL_LOCK", 0x14004, 0x00000fff}, 50 {"APLL_CON0", 0x14100, 0x00c80601 | CLK_PLL_LOCKED}, 51 {"APLL_CON1", 0x14104, 0x0000001c}, 52 {"MPLL_CON0", 0x14108, 0x00c80601 | CLK_PLL_LOCKED}, 53 {"MPLL_CON1", 0x1410c, 0x0000001c}, 54 }; 55 56 #define EXYNOS4210_REGS_NUM ARRAY_SIZE(exynos4210_clk_regs) 57 58 struct Exynos4210ClkState { 59 SysBusDevice parent_obj; 60 61 MemoryRegion iomem; 62 uint32_t reg[EXYNOS4210_REGS_NUM]; 63 }; 64 65 static uint64_t exynos4210_clk_read(void *opaque, hwaddr offset, 66 unsigned size) 67 { 68 const Exynos4210ClkState *s = (Exynos4210ClkState *)opaque; 69 const Exynos4210Reg *regs = exynos4210_clk_regs; 70 unsigned int i; 71 72 for (i = 0; i < EXYNOS4210_REGS_NUM; i++) { 73 if (regs->offset == offset) { 74 return s->reg[i]; 75 } 76 regs++; 77 } 78 qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n", 79 __func__, (uint32_t)offset); 80 return 0; 81 } 82 83 static void exynos4210_clk_write(void *opaque, hwaddr offset, 84 uint64_t val, unsigned size) 85 { 86 Exynos4210ClkState *s = (Exynos4210ClkState *)opaque; 87 const Exynos4210Reg *regs = exynos4210_clk_regs; 88 unsigned int i; 89 90 for (i = 0; i < EXYNOS4210_REGS_NUM; i++) { 91 if (regs->offset == offset) { 92 s->reg[i] = val; 93 return; 94 } 95 regs++; 96 } 97 qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n", 98 __func__, (uint32_t)offset); 99 } 100 101 static const MemoryRegionOps exynos4210_clk_ops = { 102 .read = exynos4210_clk_read, 103 .write = exynos4210_clk_write, 104 .endianness = DEVICE_NATIVE_ENDIAN, 105 .valid = { 106 .min_access_size = 4, 107 .max_access_size = 4, 108 .unaligned = false 109 } 110 }; 111 112 static void exynos4210_clk_reset(DeviceState *dev) 113 { 114 Exynos4210ClkState *s = EXYNOS4210_CLK(dev); 115 unsigned int i; 116 117 /* Set default values for registers */ 118 for (i = 0; i < EXYNOS4210_REGS_NUM; i++) { 119 s->reg[i] = exynos4210_clk_regs[i].reset_value; 120 } 121 } 122 123 static void exynos4210_clk_init(Object *obj) 124 { 125 Exynos4210ClkState *s = EXYNOS4210_CLK(obj); 126 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 127 128 /* memory mapping */ 129 memory_region_init_io(&s->iomem, obj, &exynos4210_clk_ops, s, 130 TYPE_EXYNOS4210_CLK, EXYNOS4210_CLK_REGS_MEM_SIZE); 131 sysbus_init_mmio(dev, &s->iomem); 132 } 133 134 static const VMStateDescription exynos4210_clk_vmstate = { 135 .name = TYPE_EXYNOS4210_CLK, 136 .version_id = 1, 137 .minimum_version_id = 1, 138 .fields = (VMStateField[]) { 139 VMSTATE_UINT32_ARRAY(reg, Exynos4210ClkState, EXYNOS4210_REGS_NUM), 140 VMSTATE_END_OF_LIST() 141 } 142 }; 143 144 static void exynos4210_clk_class_init(ObjectClass *klass, void *data) 145 { 146 DeviceClass *dc = DEVICE_CLASS(klass); 147 148 dc->reset = exynos4210_clk_reset; 149 dc->vmsd = &exynos4210_clk_vmstate; 150 } 151 152 static const TypeInfo exynos4210_clk_info = { 153 .name = TYPE_EXYNOS4210_CLK, 154 .parent = TYPE_SYS_BUS_DEVICE, 155 .instance_size = sizeof(Exynos4210ClkState), 156 .instance_init = exynos4210_clk_init, 157 .class_init = exynos4210_clk_class_init, 158 }; 159 160 static void exynos4210_clk_register(void) 161 { 162 qemu_log_mask(LOG_GUEST_ERROR, "Clock init\n"); 163 type_register_static(&exynos4210_clk_info); 164 } 165 166 type_init(exynos4210_clk_register) 167