1 /* 2 * PowerMac MacIO device emulation 3 * 4 * Copyright (c) 2005-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "hw/hw.h" 28 #include "hw/ppc/mac.h" 29 #include "hw/misc/macio/cuda.h" 30 #include "hw/pci/pci.h" 31 #include "hw/ppc/mac_dbdma.h" 32 #include "hw/char/escc.h" 33 #include "hw/misc/macio/macio.h" 34 #include "hw/intc/heathrow_pic.h" 35 36 /* Note: this code is strongly inspirated from the corresponding code 37 * in PearPC */ 38 39 /* 40 * The mac-io has two interfaces to the ESCC. One is called "escc-legacy", 41 * while the other one is the normal, current ESCC interface. 42 * 43 * The magic below creates memory aliases to spawn the escc-legacy device 44 * purely by rerouting the respective registers to our escc region. This 45 * works because the only difference between the two memory regions is the 46 * register layout, not their semantics. 47 * 48 * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 49 */ 50 static void macio_escc_legacy_setup(MacIOState *s) 51 { 52 ESCCState *escc = ESCC(&s->escc); 53 SysBusDevice *sbd = SYS_BUS_DEVICE(escc); 54 MemoryRegion *escc_legacy = g_new(MemoryRegion, 1); 55 MemoryRegion *bar = &s->bar; 56 int i; 57 static const int maps[] = { 58 0x00, 0x00, /* Command B */ 59 0x02, 0x20, /* Command A */ 60 0x04, 0x10, /* Data B */ 61 0x06, 0x30, /* Data A */ 62 0x08, 0x40, /* Enhancement B */ 63 0x0A, 0x50, /* Enhancement A */ 64 0x80, 0x80, /* Recovery count */ 65 0x90, 0x90, /* Start A */ 66 0xa0, 0xa0, /* Start B */ 67 0xb0, 0xb0, /* Detect AB */ 68 }; 69 70 memory_region_init(escc_legacy, OBJECT(s), "escc-legacy", 256); 71 for (i = 0; i < ARRAY_SIZE(maps); i += 2) { 72 MemoryRegion *port = g_new(MemoryRegion, 1); 73 memory_region_init_alias(port, OBJECT(s), "escc-legacy-port", 74 sysbus_mmio_get_region(sbd, 0), 75 maps[i + 1], 0x2); 76 memory_region_add_subregion(escc_legacy, maps[i], port); 77 } 78 79 memory_region_add_subregion(bar, 0x12000, escc_legacy); 80 } 81 82 static void macio_bar_setup(MacIOState *s) 83 { 84 ESCCState *escc = ESCC(&s->escc); 85 SysBusDevice *sbd = SYS_BUS_DEVICE(escc); 86 MemoryRegion *bar = &s->bar; 87 88 memory_region_add_subregion(bar, 0x13000, sysbus_mmio_get_region(sbd, 0)); 89 macio_escc_legacy_setup(s); 90 } 91 92 static void macio_common_realize(PCIDevice *d, Error **errp) 93 { 94 MacIOState *s = MACIO(d); 95 SysBusDevice *sysbus_dev; 96 Error *err = NULL; 97 98 object_property_set_bool(OBJECT(&s->dbdma), true, "realized", &err); 99 if (err) { 100 error_propagate(errp, err); 101 return; 102 } 103 sysbus_dev = SYS_BUS_DEVICE(&s->dbdma); 104 memory_region_add_subregion(&s->bar, 0x08000, 105 sysbus_mmio_get_region(sysbus_dev, 0)); 106 107 qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency", 108 s->frequency); 109 object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err); 110 if (err) { 111 error_propagate(errp, err); 112 return; 113 } 114 sysbus_dev = SYS_BUS_DEVICE(&s->cuda); 115 memory_region_add_subregion(&s->bar, 0x16000, 116 sysbus_mmio_get_region(sysbus_dev, 0)); 117 118 object_property_set_bool(OBJECT(&s->escc), true, "realized", &err); 119 if (err) { 120 error_propagate(errp, err); 121 return; 122 } 123 124 macio_bar_setup(s); 125 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar); 126 } 127 128 static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide, 129 qemu_irq irq0, qemu_irq irq1, int dmaid, 130 Error **errp) 131 { 132 SysBusDevice *sysbus_dev; 133 134 sysbus_dev = SYS_BUS_DEVICE(ide); 135 sysbus_connect_irq(sysbus_dev, 0, irq0); 136 sysbus_connect_irq(sysbus_dev, 1, irq1); 137 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); 138 object_property_set_link(OBJECT(ide), OBJECT(&s->dbdma), "dbdma", errp); 139 macio_ide_register_dma(ide); 140 141 object_property_set_bool(OBJECT(ide), true, "realized", errp); 142 } 143 144 static void macio_oldworld_realize(PCIDevice *d, Error **errp) 145 { 146 MacIOState *s = MACIO(d); 147 OldWorldMacIOState *os = OLDWORLD_MACIO(d); 148 Error *err = NULL; 149 SysBusDevice *sysbus_dev; 150 int i; 151 int cur_irq = 0; 152 153 macio_common_realize(d, &err); 154 if (err) { 155 error_propagate(errp, err); 156 return; 157 } 158 159 sysbus_dev = SYS_BUS_DEVICE(&s->cuda); 160 sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]); 161 162 sysbus_dev = SYS_BUS_DEVICE(&s->escc); 163 sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]); 164 sysbus_connect_irq(sysbus_dev, 1, os->irqs[cur_irq++]); 165 166 object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err); 167 if (err) { 168 error_propagate(errp, err); 169 return; 170 } 171 sysbus_dev = SYS_BUS_DEVICE(&os->nvram); 172 memory_region_add_subregion(&s->bar, 0x60000, 173 sysbus_mmio_get_region(sysbus_dev, 0)); 174 pmac_format_nvram_partition(&os->nvram, os->nvram.size); 175 176 /* Heathrow PIC */ 177 sysbus_dev = SYS_BUS_DEVICE(os->pic); 178 memory_region_add_subregion(&s->bar, 0x0, 179 sysbus_mmio_get_region(sysbus_dev, 0)); 180 181 /* IDE buses */ 182 for (i = 0; i < ARRAY_SIZE(os->ide); i++) { 183 qemu_irq irq0 = os->irqs[cur_irq++]; 184 qemu_irq irq1 = os->irqs[cur_irq++]; 185 186 macio_realize_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4), &err); 187 if (err) { 188 error_propagate(errp, err); 189 return; 190 } 191 } 192 } 193 194 static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, size_t ide_size, 195 int index) 196 { 197 gchar *name; 198 199 object_initialize(ide, ide_size, TYPE_MACIO_IDE); 200 qdev_set_parent_bus(DEVICE(ide), sysbus_get_default()); 201 memory_region_add_subregion(&s->bar, 0x1f000 + ((index + 1) * 0x1000), 202 &ide->mem); 203 name = g_strdup_printf("ide[%i]", index); 204 object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL); 205 g_free(name); 206 } 207 208 static void macio_oldworld_init(Object *obj) 209 { 210 MacIOState *s = MACIO(obj); 211 OldWorldMacIOState *os = OLDWORLD_MACIO(obj); 212 DeviceState *dev; 213 int i; 214 215 qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs)); 216 217 object_property_add_link(obj, "pic", TYPE_HEATHROW, 218 (Object **) &os->pic, 219 qdev_prop_allow_set_link_before_realize, 220 0, NULL); 221 222 object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM); 223 dev = DEVICE(&os->nvram); 224 qdev_prop_set_uint32(dev, "size", 0x2000); 225 qdev_prop_set_uint32(dev, "it_shift", 4); 226 227 for (i = 0; i < 2; i++) { 228 macio_init_ide(s, &os->ide[i], sizeof(os->ide[i]), i); 229 } 230 } 231 232 static void timer_write(void *opaque, hwaddr addr, uint64_t value, 233 unsigned size) 234 { 235 } 236 237 static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size) 238 { 239 uint32_t value = 0; 240 uint64_t systime = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 241 uint64_t kltime; 242 243 kltime = muldiv64(systime, 4194300, NANOSECONDS_PER_SECOND * 4); 244 kltime = muldiv64(kltime, 18432000, 1048575); 245 246 switch (addr) { 247 case 0x38: 248 value = kltime; 249 break; 250 case 0x3c: 251 value = kltime >> 32; 252 break; 253 } 254 255 return value; 256 } 257 258 static const MemoryRegionOps timer_ops = { 259 .read = timer_read, 260 .write = timer_write, 261 .endianness = DEVICE_LITTLE_ENDIAN, 262 }; 263 264 static void macio_newworld_realize(PCIDevice *d, Error **errp) 265 { 266 MacIOState *s = MACIO(d); 267 NewWorldMacIOState *ns = NEWWORLD_MACIO(d); 268 Error *err = NULL; 269 SysBusDevice *sysbus_dev; 270 MemoryRegion *timer_memory = NULL; 271 int i; 272 int cur_irq = 0; 273 274 macio_common_realize(d, &err); 275 if (err) { 276 error_propagate(errp, err); 277 return; 278 } 279 280 sysbus_dev = SYS_BUS_DEVICE(&s->cuda); 281 sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]); 282 283 sysbus_dev = SYS_BUS_DEVICE(&s->escc); 284 sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]); 285 sysbus_connect_irq(sysbus_dev, 1, ns->irqs[cur_irq++]); 286 287 /* OpenPIC */ 288 sysbus_dev = SYS_BUS_DEVICE(ns->pic); 289 memory_region_add_subregion(&s->bar, 0x40000, 290 sysbus_mmio_get_region(sysbus_dev, 0)); 291 292 /* IDE buses */ 293 for (i = 0; i < ARRAY_SIZE(ns->ide); i++) { 294 qemu_irq irq0 = ns->irqs[cur_irq++]; 295 qemu_irq irq1 = ns->irqs[cur_irq++]; 296 297 macio_realize_ide(s, &ns->ide[i], irq0, irq1, 0x16 + (i * 4), &err); 298 if (err) { 299 error_propagate(errp, err); 300 return; 301 } 302 } 303 304 /* Timer */ 305 timer_memory = g_new(MemoryRegion, 1); 306 memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer", 307 0x1000); 308 memory_region_add_subregion(&s->bar, 0x15000, timer_memory); 309 } 310 311 static void macio_newworld_init(Object *obj) 312 { 313 MacIOState *s = MACIO(obj); 314 NewWorldMacIOState *ns = NEWWORLD_MACIO(obj); 315 int i; 316 317 qdev_init_gpio_out(DEVICE(obj), ns->irqs, ARRAY_SIZE(ns->irqs)); 318 319 object_property_add_link(obj, "pic", TYPE_OPENPIC, 320 (Object **) &ns->pic, 321 qdev_prop_allow_set_link_before_realize, 322 0, NULL); 323 324 for (i = 0; i < 2; i++) { 325 macio_init_ide(s, &ns->ide[i], sizeof(ns->ide[i]), i); 326 } 327 } 328 329 static void macio_instance_init(Object *obj) 330 { 331 MacIOState *s = MACIO(obj); 332 333 memory_region_init(&s->bar, obj, "macio", 0x80000); 334 335 object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA); 336 qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default()); 337 object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL); 338 339 object_initialize(&s->dbdma, sizeof(s->dbdma), TYPE_MAC_DBDMA); 340 qdev_set_parent_bus(DEVICE(&s->dbdma), sysbus_get_default()); 341 object_property_add_child(obj, "dbdma", OBJECT(&s->dbdma), NULL); 342 343 object_initialize(&s->escc, sizeof(s->escc), TYPE_ESCC); 344 qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0); 345 qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK); 346 qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4); 347 qdev_prop_set_chr(DEVICE(&s->escc), "chrA", serial_hds[0]); 348 qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hds[1]); 349 qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial); 350 qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial); 351 qdev_set_parent_bus(DEVICE(&s->escc), sysbus_get_default()); 352 object_property_add_child(obj, "escc", OBJECT(&s->escc), NULL); 353 } 354 355 static const VMStateDescription vmstate_macio_oldworld = { 356 .name = "macio-oldworld", 357 .version_id = 0, 358 .minimum_version_id = 0, 359 .fields = (VMStateField[]) { 360 VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState), 361 VMSTATE_END_OF_LIST() 362 } 363 }; 364 365 static void macio_oldworld_class_init(ObjectClass *oc, void *data) 366 { 367 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc); 368 DeviceClass *dc = DEVICE_CLASS(oc); 369 370 pdc->realize = macio_oldworld_realize; 371 pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201; 372 dc->vmsd = &vmstate_macio_oldworld; 373 } 374 375 static const VMStateDescription vmstate_macio_newworld = { 376 .name = "macio-newworld", 377 .version_id = 0, 378 .minimum_version_id = 0, 379 .fields = (VMStateField[]) { 380 VMSTATE_PCI_DEVICE(parent_obj.parent, NewWorldMacIOState), 381 VMSTATE_END_OF_LIST() 382 } 383 }; 384 385 static void macio_newworld_class_init(ObjectClass *oc, void *data) 386 { 387 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc); 388 DeviceClass *dc = DEVICE_CLASS(oc); 389 390 pdc->realize = macio_newworld_realize; 391 pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL; 392 dc->vmsd = &vmstate_macio_newworld; 393 } 394 395 static Property macio_properties[] = { 396 DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0), 397 DEFINE_PROP_END_OF_LIST() 398 }; 399 400 static void macio_class_init(ObjectClass *klass, void *data) 401 { 402 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 403 DeviceClass *dc = DEVICE_CLASS(klass); 404 405 k->vendor_id = PCI_VENDOR_ID_APPLE; 406 k->class_id = PCI_CLASS_OTHERS << 8; 407 dc->props = macio_properties; 408 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 409 } 410 411 static const TypeInfo macio_oldworld_type_info = { 412 .name = TYPE_OLDWORLD_MACIO, 413 .parent = TYPE_MACIO, 414 .instance_size = sizeof(OldWorldMacIOState), 415 .instance_init = macio_oldworld_init, 416 .class_init = macio_oldworld_class_init, 417 }; 418 419 static const TypeInfo macio_newworld_type_info = { 420 .name = TYPE_NEWWORLD_MACIO, 421 .parent = TYPE_MACIO, 422 .instance_size = sizeof(NewWorldMacIOState), 423 .instance_init = macio_newworld_init, 424 .class_init = macio_newworld_class_init, 425 }; 426 427 static const TypeInfo macio_type_info = { 428 .name = TYPE_MACIO, 429 .parent = TYPE_PCI_DEVICE, 430 .instance_size = sizeof(MacIOState), 431 .instance_init = macio_instance_init, 432 .abstract = true, 433 .class_init = macio_class_init, 434 .interfaces = (InterfaceInfo[]) { 435 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 436 { }, 437 }, 438 }; 439 440 static void macio_register_types(void) 441 { 442 type_register_static(&macio_type_info); 443 type_register_static(&macio_oldworld_type_info); 444 type_register_static(&macio_newworld_type_info); 445 } 446 447 type_init(macio_register_types) 448