10f25065cSBin Meng /*
20f25065cSBin Meng * Microchip PolarFire SoC SYSREG module emulation
30f25065cSBin Meng *
40f25065cSBin Meng * Copyright (c) 2020 Wind River Systems, Inc.
50f25065cSBin Meng *
60f25065cSBin Meng * Author:
70f25065cSBin Meng * Bin Meng <bin.meng@windriver.com>
80f25065cSBin Meng *
90f25065cSBin Meng * This program is free software; you can redistribute it and/or
100f25065cSBin Meng * modify it under the terms of the GNU General Public License as
110f25065cSBin Meng * published by the Free Software Foundation; either version 2 or
120f25065cSBin Meng * (at your option) version 3 of the License.
130f25065cSBin Meng *
140f25065cSBin Meng * This program is distributed in the hope that it will be useful,
150f25065cSBin Meng * but WITHOUT ANY WARRANTY; without even the implied warranty of
160f25065cSBin Meng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
170f25065cSBin Meng * GNU General Public License for more details.
180f25065cSBin Meng *
190f25065cSBin Meng * You should have received a copy of the GNU General Public License along
200f25065cSBin Meng * with this program; if not, see <http://www.gnu.org/licenses/>.
210f25065cSBin Meng */
220f25065cSBin Meng
230f25065cSBin Meng #include "qemu/osdep.h"
240f25065cSBin Meng #include "qemu/bitops.h"
250f25065cSBin Meng #include "qemu/log.h"
260f25065cSBin Meng #include "qapi/error.h"
27592f0a94SConor Dooley #include "hw/irq.h"
280f25065cSBin Meng #include "hw/sysbus.h"
290f25065cSBin Meng #include "hw/misc/mchp_pfsoc_sysreg.h"
300f25065cSBin Meng
310f25065cSBin Meng #define ENVM_CR 0xb8
32592f0a94SConor Dooley #define MESSAGE_INT 0x118c
330f25065cSBin Meng
mchp_pfsoc_sysreg_read(void * opaque,hwaddr offset,unsigned size)340f25065cSBin Meng static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
350f25065cSBin Meng unsigned size)
360f25065cSBin Meng {
370f25065cSBin Meng uint32_t val = 0;
380f25065cSBin Meng
390f25065cSBin Meng switch (offset) {
400f25065cSBin Meng case ENVM_CR:
410f25065cSBin Meng /* Indicate the eNVM is running at the configured divider rate */
420f25065cSBin Meng val = BIT(6);
430f25065cSBin Meng break;
440f25065cSBin Meng default:
450f25065cSBin Meng qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
460f25065cSBin Meng "(size %d, offset 0x%" HWADDR_PRIx ")\n",
470f25065cSBin Meng __func__, size, offset);
480f25065cSBin Meng break;
490f25065cSBin Meng }
500f25065cSBin Meng
510f25065cSBin Meng return val;
520f25065cSBin Meng }
530f25065cSBin Meng
mchp_pfsoc_sysreg_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)540f25065cSBin Meng static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
550f25065cSBin Meng uint64_t value, unsigned size)
560f25065cSBin Meng {
57592f0a94SConor Dooley MchpPfSoCSysregState *s = opaque;
58592f0a94SConor Dooley switch (offset) {
59592f0a94SConor Dooley case MESSAGE_INT:
60592f0a94SConor Dooley qemu_irq_lower(s->irq);
61592f0a94SConor Dooley break;
62592f0a94SConor Dooley default:
630f25065cSBin Meng qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
640f25065cSBin Meng "(size %d, value 0x%" PRIx64
650f25065cSBin Meng ", offset 0x%" HWADDR_PRIx ")\n",
660f25065cSBin Meng __func__, size, value, offset);
670f25065cSBin Meng }
68592f0a94SConor Dooley }
690f25065cSBin Meng
700f25065cSBin Meng static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
710f25065cSBin Meng .read = mchp_pfsoc_sysreg_read,
720f25065cSBin Meng .write = mchp_pfsoc_sysreg_write,
730f25065cSBin Meng .endianness = DEVICE_LITTLE_ENDIAN,
740f25065cSBin Meng };
750f25065cSBin Meng
mchp_pfsoc_sysreg_realize(DeviceState * dev,Error ** errp)760f25065cSBin Meng static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
770f25065cSBin Meng {
780f25065cSBin Meng MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
790f25065cSBin Meng
800f25065cSBin Meng memory_region_init_io(&s->sysreg, OBJECT(dev),
810f25065cSBin Meng &mchp_pfsoc_sysreg_ops, s,
820f25065cSBin Meng "mchp.pfsoc.sysreg",
830f25065cSBin Meng MCHP_PFSOC_SYSREG_REG_SIZE);
840f25065cSBin Meng sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
85592f0a94SConor Dooley sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
860f25065cSBin Meng }
870f25065cSBin Meng
mchp_pfsoc_sysreg_class_init(ObjectClass * klass,void * data)880f25065cSBin Meng static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
890f25065cSBin Meng {
900f25065cSBin Meng DeviceClass *dc = DEVICE_CLASS(klass);
910f25065cSBin Meng
920f25065cSBin Meng dc->desc = "Microchip PolarFire SoC SYSREG module";
930f25065cSBin Meng dc->realize = mchp_pfsoc_sysreg_realize;
940f25065cSBin Meng }
950f25065cSBin Meng
960f25065cSBin Meng static const TypeInfo mchp_pfsoc_sysreg_info = {
970f25065cSBin Meng .name = TYPE_MCHP_PFSOC_SYSREG,
980f25065cSBin Meng .parent = TYPE_SYS_BUS_DEVICE,
990f25065cSBin Meng .instance_size = sizeof(MchpPfSoCSysregState),
1000f25065cSBin Meng .class_init = mchp_pfsoc_sysreg_class_init,
1010f25065cSBin Meng };
1020f25065cSBin Meng
mchp_pfsoc_sysreg_register_types(void)1030f25065cSBin Meng static void mchp_pfsoc_sysreg_register_types(void)
1040f25065cSBin Meng {
1050f25065cSBin Meng type_register_static(&mchp_pfsoc_sysreg_info);
1060f25065cSBin Meng }
1070f25065cSBin Meng
1080f25065cSBin Meng type_init(mchp_pfsoc_sysreg_register_types)
109