134fa7e83SLeon Alrae /* 234fa7e83SLeon Alrae * Inter-Thread Communication Unit emulation. 334fa7e83SLeon Alrae * 434fa7e83SLeon Alrae * Copyright (c) 2016 Imagination Technologies 534fa7e83SLeon Alrae * 634fa7e83SLeon Alrae * This library is free software; you can redistribute it and/or 734fa7e83SLeon Alrae * modify it under the terms of the GNU Lesser General Public 834fa7e83SLeon Alrae * License as published by the Free Software Foundation; either 9d136ecc0SChetan Pant * version 2.1 of the License, or (at your option) any later version. 1034fa7e83SLeon Alrae * 1134fa7e83SLeon Alrae * This library is distributed in the hope that it will be useful, 1234fa7e83SLeon Alrae * but WITHOUT ANY WARRANTY; without even the implied warranty of 1334fa7e83SLeon Alrae * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1434fa7e83SLeon Alrae * Lesser General Public License for more details. 1534fa7e83SLeon Alrae * 1634fa7e83SLeon Alrae * You should have received a copy of the GNU Lesser General Public 1734fa7e83SLeon Alrae * License along with this library; if not, see <http://www.gnu.org/licenses/>. 1834fa7e83SLeon Alrae */ 1934fa7e83SLeon Alrae 2034fa7e83SLeon Alrae #include "qemu/osdep.h" 21be01029eSPhilippe Mathieu-Daudé #include "qemu/units.h" 22921e1a2aSPhilippe Mathieu-Daudé #include "qemu/log.h" 230b8fa32fSMarkus Armbruster #include "qemu/module.h" 2434fa7e83SLeon Alrae #include "qapi/error.h" 2563c91552SPaolo Bonzini #include "exec/exec-all.h" 2634fa7e83SLeon Alrae #include "hw/misc/mips_itu.h" 27a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 2834fa7e83SLeon Alrae 2934fa7e83SLeon Alrae #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8) 3034fa7e83SLeon Alrae /* Initialize as 4kB area to fit all 32 cells with default 128B grain. 3134fa7e83SLeon Alrae Storage may be resized by the software. */ 3234fa7e83SLeon Alrae #define ITC_STORAGE_ADDRSPACE_SZ 0x1000 3334fa7e83SLeon Alrae 3434fa7e83SLeon Alrae #define ITC_FIFO_NUM_MAX 16 3534fa7e83SLeon Alrae #define ITC_SEMAPH_NUM_MAX 16 3634fa7e83SLeon Alrae #define ITC_AM1_NUMENTRIES_OFS 20 3734fa7e83SLeon Alrae 3840dc9dc3SLeon Alrae #define ITC_CELL_PV_MAX_VAL 0xFFFF 3940dc9dc3SLeon Alrae 405924c869SLeon Alrae #define ITC_CELL_TAG_FIFO_DEPTH 28 415924c869SLeon Alrae #define ITC_CELL_TAG_FIFO_PTR 18 425924c869SLeon Alrae #define ITC_CELL_TAG_FIFO 17 435924c869SLeon Alrae #define ITC_CELL_TAG_T 16 445924c869SLeon Alrae #define ITC_CELL_TAG_F 1 455924c869SLeon Alrae #define ITC_CELL_TAG_E 0 465924c869SLeon Alrae 4734fa7e83SLeon Alrae #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL 4834fa7e83SLeon Alrae #define ITC_AM0_EN_MASK 0x1 4934fa7e83SLeon Alrae 5034fa7e83SLeon Alrae #define ITC_AM1_ADDR_MASK_MASK 0x1FC00 5134fa7e83SLeon Alrae #define ITC_AM1_ENTRY_GRAIN_MASK 0x7 5234fa7e83SLeon Alrae 535924c869SLeon Alrae typedef enum ITCView { 545924c869SLeon Alrae ITCVIEW_BYPASS = 0, 555924c869SLeon Alrae ITCVIEW_CONTROL = 1, 565924c869SLeon Alrae ITCVIEW_EF_SYNC = 2, 575924c869SLeon Alrae ITCVIEW_EF_TRY = 3, 585924c869SLeon Alrae ITCVIEW_PV_SYNC = 4, 59e5345d96SYongbok Kim ITCVIEW_PV_TRY = 5, 60e5345d96SYongbok Kim ITCVIEW_PV_ICR0 = 15, 615924c869SLeon Alrae } ITCView; 625924c869SLeon Alrae 63e5345d96SYongbok Kim #define ITC_ICR0_CELL_NUM 16 64e5345d96SYongbok Kim #define ITC_ICR0_BLK_GRAIN 8 65e5345d96SYongbok Kim #define ITC_ICR0_BLK_GRAIN_MASK 0x7 66e5345d96SYongbok Kim #define ITC_ICR0_ERR_AXI 2 67e5345d96SYongbok Kim #define ITC_ICR0_ERR_PARITY 1 68e5345d96SYongbok Kim #define ITC_ICR0_ERR_EXEC 0 69e5345d96SYongbok Kim 7034fa7e83SLeon Alrae MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) 7134fa7e83SLeon Alrae { 7234fa7e83SLeon Alrae return &itu->tag_io; 7334fa7e83SLeon Alrae } 7434fa7e83SLeon Alrae 7534fa7e83SLeon Alrae static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) 7634fa7e83SLeon Alrae { 7734fa7e83SLeon Alrae MIPSITUState *tag = (MIPSITUState *)opaque; 7834fa7e83SLeon Alrae uint64_t index = addr >> 3; 7934fa7e83SLeon Alrae 80f2eb665aSLeon Alrae if (index >= ITC_ADDRESSMAP_NUM) { 8134fa7e83SLeon Alrae qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr); 82f2eb665aSLeon Alrae return 0; 8334fa7e83SLeon Alrae } 8434fa7e83SLeon Alrae 85f2eb665aSLeon Alrae return tag->ITCAddressMap[index]; 8634fa7e83SLeon Alrae } 8734fa7e83SLeon Alrae 88043715d1SYongbok Kim void itc_reconfigure(MIPSITUState *tag) 8934fa7e83SLeon Alrae { 9034fa7e83SLeon Alrae uint64_t *am = &tag->ITCAddressMap[0]; 9134fa7e83SLeon Alrae MemoryRegion *mr = &tag->storage_io; 9234fa7e83SLeon Alrae hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; 93be01029eSPhilippe Mathieu-Daudé uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); 9434fa7e83SLeon Alrae bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; 9534fa7e83SLeon Alrae 96043715d1SYongbok Kim if (tag->saar_present) { 97043715d1SYongbok Kim address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; 98cd3ed7dbSAleksandar Markovic size = 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f); 99043715d1SYongbok Kim is_enabled = *(uint64_t *) tag->saar & 1; 100043715d1SYongbok Kim } 101043715d1SYongbok Kim 10234fa7e83SLeon Alrae memory_region_transaction_begin(); 10334fa7e83SLeon Alrae if (!(size & (size - 1))) { 10434fa7e83SLeon Alrae memory_region_set_size(mr, size); 10534fa7e83SLeon Alrae } 10634fa7e83SLeon Alrae memory_region_set_address(mr, address); 10734fa7e83SLeon Alrae memory_region_set_enabled(mr, is_enabled); 10834fa7e83SLeon Alrae memory_region_transaction_commit(); 10934fa7e83SLeon Alrae } 11034fa7e83SLeon Alrae 11134fa7e83SLeon Alrae static void itc_tag_write(void *opaque, hwaddr addr, 11234fa7e83SLeon Alrae uint64_t data, unsigned size) 11334fa7e83SLeon Alrae { 11434fa7e83SLeon Alrae MIPSITUState *tag = (MIPSITUState *)opaque; 11534fa7e83SLeon Alrae uint64_t *am = &tag->ITCAddressMap[0]; 11634fa7e83SLeon Alrae uint64_t am_old, mask; 11734fa7e83SLeon Alrae uint64_t index = addr >> 3; 11834fa7e83SLeon Alrae 11934fa7e83SLeon Alrae switch (index) { 12034fa7e83SLeon Alrae case 0: 12134fa7e83SLeon Alrae mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK; 12234fa7e83SLeon Alrae break; 12334fa7e83SLeon Alrae case 1: 12434fa7e83SLeon Alrae mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK; 12534fa7e83SLeon Alrae break; 12634fa7e83SLeon Alrae default: 12734fa7e83SLeon Alrae qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr); 12834fa7e83SLeon Alrae return; 12934fa7e83SLeon Alrae } 13034fa7e83SLeon Alrae 13134fa7e83SLeon Alrae am_old = am[index]; 13234fa7e83SLeon Alrae am[index] = (data & mask) | (am_old & ~mask); 13334fa7e83SLeon Alrae if (am_old != am[index]) { 13434fa7e83SLeon Alrae itc_reconfigure(tag); 13534fa7e83SLeon Alrae } 13634fa7e83SLeon Alrae } 13734fa7e83SLeon Alrae 13834fa7e83SLeon Alrae static const MemoryRegionOps itc_tag_ops = { 13934fa7e83SLeon Alrae .read = itc_tag_read, 14034fa7e83SLeon Alrae .write = itc_tag_write, 14134fa7e83SLeon Alrae .impl = { 14234fa7e83SLeon Alrae .max_access_size = 8, 14334fa7e83SLeon Alrae }, 14434fa7e83SLeon Alrae .endianness = DEVICE_NATIVE_ENDIAN, 14534fa7e83SLeon Alrae }; 14634fa7e83SLeon Alrae 14734fa7e83SLeon Alrae static inline uint32_t get_num_cells(MIPSITUState *s) 14834fa7e83SLeon Alrae { 14934fa7e83SLeon Alrae return s->num_fifo + s->num_semaphores; 15034fa7e83SLeon Alrae } 15134fa7e83SLeon Alrae 1525924c869SLeon Alrae static inline ITCView get_itc_view(hwaddr addr) 1535924c869SLeon Alrae { 1545924c869SLeon Alrae return (addr >> 3) & 0xf; 1555924c869SLeon Alrae } 1565924c869SLeon Alrae 1575924c869SLeon Alrae static inline int get_cell_stride_shift(const MIPSITUState *s) 1585924c869SLeon Alrae { 1595924c869SLeon Alrae /* Minimum interval (for EntryGain = 0) is 128 B */ 160043715d1SYongbok Kim if (s->saar_present) { 161043715d1SYongbok Kim return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & 162043715d1SYongbok Kim ITC_ICR0_BLK_GRAIN_MASK); 163043715d1SYongbok Kim } else { 1645924c869SLeon Alrae return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); 1655924c869SLeon Alrae } 166043715d1SYongbok Kim } 1675924c869SLeon Alrae 1685924c869SLeon Alrae static inline ITCStorageCell *get_cell(MIPSITUState *s, 1695924c869SLeon Alrae hwaddr addr) 1705924c869SLeon Alrae { 1715924c869SLeon Alrae uint32_t cell_idx = addr >> get_cell_stride_shift(s); 1725924c869SLeon Alrae uint32_t num_cells = get_num_cells(s); 1735924c869SLeon Alrae 1745924c869SLeon Alrae if (cell_idx >= num_cells) { 1755924c869SLeon Alrae cell_idx = num_cells - 1; 1765924c869SLeon Alrae } 1775924c869SLeon Alrae 1785924c869SLeon Alrae return &s->cell[cell_idx]; 1795924c869SLeon Alrae } 1805924c869SLeon Alrae 1814051089dSLeon Alrae static void wake_blocked_threads(ITCStorageCell *c) 1824051089dSLeon Alrae { 1834051089dSLeon Alrae CPUState *cs; 1844051089dSLeon Alrae CPU_FOREACH(cs) { 1854051089dSLeon Alrae if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) { 1864051089dSLeon Alrae cpu_interrupt(cs, CPU_INTERRUPT_WAKE); 1874051089dSLeon Alrae } 1884051089dSLeon Alrae } 1894051089dSLeon Alrae c->blocked_threads = 0; 1904051089dSLeon Alrae } 1914051089dSLeon Alrae 1928905770bSMarc-André Lureau static G_NORETURN 1938905770bSMarc-André Lureau void block_thread_and_exit(ITCStorageCell *c) 1944051089dSLeon Alrae { 1954051089dSLeon Alrae c->blocked_threads |= 1ULL << current_cpu->cpu_index; 1964051089dSLeon Alrae current_cpu->halted = 1; 1974051089dSLeon Alrae current_cpu->exception_index = EXCP_HLT; 198afd46fcaSPavel Dovgalyuk cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc); 1994051089dSLeon Alrae } 2004051089dSLeon Alrae 20125a611e3SLeon Alrae /* ITC Bypass View */ 20225a611e3SLeon Alrae 20325a611e3SLeon Alrae static inline uint64_t view_bypass_read(ITCStorageCell *c) 20425a611e3SLeon Alrae { 20525a611e3SLeon Alrae if (c->tag.FIFO) { 20625a611e3SLeon Alrae return c->data[c->fifo_out]; 20725a611e3SLeon Alrae } else { 20825a611e3SLeon Alrae return c->data[0]; 20925a611e3SLeon Alrae } 21025a611e3SLeon Alrae } 21125a611e3SLeon Alrae 21225a611e3SLeon Alrae static inline void view_bypass_write(ITCStorageCell *c, uint64_t val) 21325a611e3SLeon Alrae { 21425a611e3SLeon Alrae if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) { 21525a611e3SLeon Alrae int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH; 21625a611e3SLeon Alrae c->data[idx] = val; 21725a611e3SLeon Alrae } 21825a611e3SLeon Alrae 21925a611e3SLeon Alrae /* ignore a write to the semaphore cell */ 22025a611e3SLeon Alrae } 22125a611e3SLeon Alrae 2225924c869SLeon Alrae /* ITC Control View */ 2235924c869SLeon Alrae 2245924c869SLeon Alrae static inline uint64_t view_control_read(ITCStorageCell *c) 2255924c869SLeon Alrae { 2265924c869SLeon Alrae return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) | 2275924c869SLeon Alrae (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) | 2285924c869SLeon Alrae (c->tag.FIFO << ITC_CELL_TAG_FIFO) | 2295924c869SLeon Alrae (c->tag.T << ITC_CELL_TAG_T) | 2305924c869SLeon Alrae (c->tag.E << ITC_CELL_TAG_E) | 2315924c869SLeon Alrae (c->tag.F << ITC_CELL_TAG_F); 2325924c869SLeon Alrae } 2335924c869SLeon Alrae 2345924c869SLeon Alrae static inline void view_control_write(ITCStorageCell *c, uint64_t val) 2355924c869SLeon Alrae { 2365924c869SLeon Alrae c->tag.T = (val >> ITC_CELL_TAG_T) & 1; 2375924c869SLeon Alrae c->tag.E = (val >> ITC_CELL_TAG_E) & 1; 2385924c869SLeon Alrae c->tag.F = (val >> ITC_CELL_TAG_F) & 1; 2395924c869SLeon Alrae 2405924c869SLeon Alrae if (c->tag.E) { 2415924c869SLeon Alrae c->tag.FIFOPtr = 0; 2425924c869SLeon Alrae } 2435924c869SLeon Alrae } 2445924c869SLeon Alrae 2454051089dSLeon Alrae /* ITC Empty/Full View */ 2464051089dSLeon Alrae 2474051089dSLeon Alrae static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking) 2484051089dSLeon Alrae { 2494051089dSLeon Alrae uint64_t ret = 0; 2504051089dSLeon Alrae 2514051089dSLeon Alrae if (!c->tag.FIFO) { 2524051089dSLeon Alrae return 0; 2534051089dSLeon Alrae } 2544051089dSLeon Alrae 2554051089dSLeon Alrae c->tag.F = 0; 2564051089dSLeon Alrae 2574051089dSLeon Alrae if (blocking && c->tag.E) { 2584051089dSLeon Alrae block_thread_and_exit(c); 2594051089dSLeon Alrae } 2604051089dSLeon Alrae 2614051089dSLeon Alrae if (c->blocked_threads) { 2624051089dSLeon Alrae wake_blocked_threads(c); 2634051089dSLeon Alrae } 2644051089dSLeon Alrae 2654051089dSLeon Alrae if (c->tag.FIFOPtr > 0) { 2664051089dSLeon Alrae ret = c->data[c->fifo_out]; 2674051089dSLeon Alrae c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH; 2684051089dSLeon Alrae c->tag.FIFOPtr--; 2694051089dSLeon Alrae } 2704051089dSLeon Alrae 2714051089dSLeon Alrae if (c->tag.FIFOPtr == 0) { 2724051089dSLeon Alrae c->tag.E = 1; 2734051089dSLeon Alrae } 2744051089dSLeon Alrae 2754051089dSLeon Alrae return ret; 2764051089dSLeon Alrae } 2774051089dSLeon Alrae 2784051089dSLeon Alrae static uint64_t view_ef_sync_read(ITCStorageCell *c) 2794051089dSLeon Alrae { 2804051089dSLeon Alrae return view_ef_common_read(c, true); 2814051089dSLeon Alrae } 2824051089dSLeon Alrae 2834051089dSLeon Alrae static uint64_t view_ef_try_read(ITCStorageCell *c) 2844051089dSLeon Alrae { 2854051089dSLeon Alrae return view_ef_common_read(c, false); 2864051089dSLeon Alrae } 2874051089dSLeon Alrae 2884051089dSLeon Alrae static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val, 2894051089dSLeon Alrae bool blocking) 2904051089dSLeon Alrae { 2914051089dSLeon Alrae if (!c->tag.FIFO) { 2924051089dSLeon Alrae return; 2934051089dSLeon Alrae } 2944051089dSLeon Alrae 2954051089dSLeon Alrae c->tag.E = 0; 2964051089dSLeon Alrae 2974051089dSLeon Alrae if (blocking && c->tag.F) { 2984051089dSLeon Alrae block_thread_and_exit(c); 2994051089dSLeon Alrae } 3004051089dSLeon Alrae 3014051089dSLeon Alrae if (c->blocked_threads) { 3024051089dSLeon Alrae wake_blocked_threads(c); 3034051089dSLeon Alrae } 3044051089dSLeon Alrae 3054051089dSLeon Alrae if (c->tag.FIFOPtr < ITC_CELL_DEPTH) { 3064051089dSLeon Alrae int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH; 3074051089dSLeon Alrae c->data[idx] = val; 3084051089dSLeon Alrae c->tag.FIFOPtr++; 3094051089dSLeon Alrae } 3104051089dSLeon Alrae 3114051089dSLeon Alrae if (c->tag.FIFOPtr == ITC_CELL_DEPTH) { 3124051089dSLeon Alrae c->tag.F = 1; 3134051089dSLeon Alrae } 3144051089dSLeon Alrae } 3154051089dSLeon Alrae 3164051089dSLeon Alrae static void view_ef_sync_write(ITCStorageCell *c, uint64_t val) 3174051089dSLeon Alrae { 3184051089dSLeon Alrae view_ef_common_write(c, val, true); 3194051089dSLeon Alrae } 3204051089dSLeon Alrae 3214051089dSLeon Alrae static void view_ef_try_write(ITCStorageCell *c, uint64_t val) 3224051089dSLeon Alrae { 3234051089dSLeon Alrae view_ef_common_write(c, val, false); 3244051089dSLeon Alrae } 3254051089dSLeon Alrae 32640dc9dc3SLeon Alrae /* ITC P/V View */ 32740dc9dc3SLeon Alrae 32840dc9dc3SLeon Alrae static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking) 32940dc9dc3SLeon Alrae { 33040dc9dc3SLeon Alrae uint64_t ret = c->data[0]; 33140dc9dc3SLeon Alrae 33240dc9dc3SLeon Alrae if (c->tag.FIFO) { 33340dc9dc3SLeon Alrae return 0; 33440dc9dc3SLeon Alrae } 33540dc9dc3SLeon Alrae 33640dc9dc3SLeon Alrae if (c->data[0] > 0) { 33740dc9dc3SLeon Alrae c->data[0]--; 33840dc9dc3SLeon Alrae } else if (blocking) { 33940dc9dc3SLeon Alrae block_thread_and_exit(c); 34040dc9dc3SLeon Alrae } 34140dc9dc3SLeon Alrae 34240dc9dc3SLeon Alrae return ret; 34340dc9dc3SLeon Alrae } 34440dc9dc3SLeon Alrae 34540dc9dc3SLeon Alrae static uint64_t view_pv_sync_read(ITCStorageCell *c) 34640dc9dc3SLeon Alrae { 34740dc9dc3SLeon Alrae return view_pv_common_read(c, true); 34840dc9dc3SLeon Alrae } 34940dc9dc3SLeon Alrae 35040dc9dc3SLeon Alrae static uint64_t view_pv_try_read(ITCStorageCell *c) 35140dc9dc3SLeon Alrae { 35240dc9dc3SLeon Alrae return view_pv_common_read(c, false); 35340dc9dc3SLeon Alrae } 35440dc9dc3SLeon Alrae 35540dc9dc3SLeon Alrae static inline void view_pv_common_write(ITCStorageCell *c) 35640dc9dc3SLeon Alrae { 35740dc9dc3SLeon Alrae if (c->tag.FIFO) { 35840dc9dc3SLeon Alrae return; 35940dc9dc3SLeon Alrae } 36040dc9dc3SLeon Alrae 36140dc9dc3SLeon Alrae if (c->data[0] < ITC_CELL_PV_MAX_VAL) { 36240dc9dc3SLeon Alrae c->data[0]++; 36340dc9dc3SLeon Alrae } 36440dc9dc3SLeon Alrae 36540dc9dc3SLeon Alrae if (c->blocked_threads) { 36640dc9dc3SLeon Alrae wake_blocked_threads(c); 36740dc9dc3SLeon Alrae } 36840dc9dc3SLeon Alrae } 36940dc9dc3SLeon Alrae 37040dc9dc3SLeon Alrae static void view_pv_sync_write(ITCStorageCell *c) 37140dc9dc3SLeon Alrae { 37240dc9dc3SLeon Alrae view_pv_common_write(c); 37340dc9dc3SLeon Alrae } 37440dc9dc3SLeon Alrae 37540dc9dc3SLeon Alrae static void view_pv_try_write(ITCStorageCell *c) 37640dc9dc3SLeon Alrae { 37740dc9dc3SLeon Alrae view_pv_common_write(c); 37840dc9dc3SLeon Alrae } 37940dc9dc3SLeon Alrae 38040cd7180SYongbok Kim static void raise_exception(int excp) 38140cd7180SYongbok Kim { 38240cd7180SYongbok Kim current_cpu->exception_index = excp; 38340cd7180SYongbok Kim cpu_loop_exit(current_cpu); 38440cd7180SYongbok Kim } 38540cd7180SYongbok Kim 3865924c869SLeon Alrae static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) 3875924c869SLeon Alrae { 3885924c869SLeon Alrae MIPSITUState *s = (MIPSITUState *)opaque; 3895924c869SLeon Alrae ITCStorageCell *cell = get_cell(s, addr); 3905924c869SLeon Alrae ITCView view = get_itc_view(addr); 3915924c869SLeon Alrae uint64_t ret = -1; 3925924c869SLeon Alrae 39340cd7180SYongbok Kim switch (size) { 39440cd7180SYongbok Kim case 1: 39540cd7180SYongbok Kim case 2: 39640cd7180SYongbok Kim s->icr0 |= 1 << ITC_ICR0_ERR_AXI; 39740cd7180SYongbok Kim raise_exception(EXCP_DBE); 39840cd7180SYongbok Kim return 0; 39940cd7180SYongbok Kim } 40040cd7180SYongbok Kim 4015924c869SLeon Alrae switch (view) { 40225a611e3SLeon Alrae case ITCVIEW_BYPASS: 40325a611e3SLeon Alrae ret = view_bypass_read(cell); 40425a611e3SLeon Alrae break; 4055924c869SLeon Alrae case ITCVIEW_CONTROL: 4065924c869SLeon Alrae ret = view_control_read(cell); 4075924c869SLeon Alrae break; 4084051089dSLeon Alrae case ITCVIEW_EF_SYNC: 4094051089dSLeon Alrae ret = view_ef_sync_read(cell); 4104051089dSLeon Alrae break; 4114051089dSLeon Alrae case ITCVIEW_EF_TRY: 4124051089dSLeon Alrae ret = view_ef_try_read(cell); 4134051089dSLeon Alrae break; 41440dc9dc3SLeon Alrae case ITCVIEW_PV_SYNC: 41540dc9dc3SLeon Alrae ret = view_pv_sync_read(cell); 41640dc9dc3SLeon Alrae break; 41740dc9dc3SLeon Alrae case ITCVIEW_PV_TRY: 41840dc9dc3SLeon Alrae ret = view_pv_try_read(cell); 41940dc9dc3SLeon Alrae break; 420e5345d96SYongbok Kim case ITCVIEW_PV_ICR0: 421e5345d96SYongbok Kim ret = s->icr0; 422e5345d96SYongbok Kim break; 4235924c869SLeon Alrae default: 4245924c869SLeon Alrae qemu_log_mask(LOG_GUEST_ERROR, 4255924c869SLeon Alrae "itc_storage_read: Bad ITC View %d\n", (int)view); 4265924c869SLeon Alrae break; 4275924c869SLeon Alrae } 4285924c869SLeon Alrae 4295924c869SLeon Alrae return ret; 4305924c869SLeon Alrae } 4315924c869SLeon Alrae 4325924c869SLeon Alrae static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, 4335924c869SLeon Alrae unsigned size) 4345924c869SLeon Alrae { 4355924c869SLeon Alrae MIPSITUState *s = (MIPSITUState *)opaque; 4365924c869SLeon Alrae ITCStorageCell *cell = get_cell(s, addr); 4375924c869SLeon Alrae ITCView view = get_itc_view(addr); 4385924c869SLeon Alrae 43940cd7180SYongbok Kim switch (size) { 44040cd7180SYongbok Kim case 1: 44140cd7180SYongbok Kim case 2: 44240cd7180SYongbok Kim s->icr0 |= 1 << ITC_ICR0_ERR_AXI; 44340cd7180SYongbok Kim raise_exception(EXCP_DBE); 44440cd7180SYongbok Kim return; 44540cd7180SYongbok Kim } 44640cd7180SYongbok Kim 4475924c869SLeon Alrae switch (view) { 44825a611e3SLeon Alrae case ITCVIEW_BYPASS: 44925a611e3SLeon Alrae view_bypass_write(cell, data); 45025a611e3SLeon Alrae break; 4515924c869SLeon Alrae case ITCVIEW_CONTROL: 4525924c869SLeon Alrae view_control_write(cell, data); 4535924c869SLeon Alrae break; 4544051089dSLeon Alrae case ITCVIEW_EF_SYNC: 4554051089dSLeon Alrae view_ef_sync_write(cell, data); 4564051089dSLeon Alrae break; 4574051089dSLeon Alrae case ITCVIEW_EF_TRY: 4584051089dSLeon Alrae view_ef_try_write(cell, data); 4594051089dSLeon Alrae break; 46040dc9dc3SLeon Alrae case ITCVIEW_PV_SYNC: 46140dc9dc3SLeon Alrae view_pv_sync_write(cell); 46240dc9dc3SLeon Alrae break; 46340dc9dc3SLeon Alrae case ITCVIEW_PV_TRY: 46440dc9dc3SLeon Alrae view_pv_try_write(cell); 46540dc9dc3SLeon Alrae break; 466e5345d96SYongbok Kim case ITCVIEW_PV_ICR0: 467e5345d96SYongbok Kim if (data & 0x7) { 468e5345d96SYongbok Kim /* clear ERROR bits */ 469e5345d96SYongbok Kim s->icr0 &= ~(data & 0x7); 470e5345d96SYongbok Kim } 471e5345d96SYongbok Kim /* set BLK_GRAIN */ 472e5345d96SYongbok Kim s->icr0 &= ~0x700; 473e5345d96SYongbok Kim s->icr0 |= data & 0x700; 474e5345d96SYongbok Kim break; 4755924c869SLeon Alrae default: 4765924c869SLeon Alrae qemu_log_mask(LOG_GUEST_ERROR, 4775924c869SLeon Alrae "itc_storage_write: Bad ITC View %d\n", (int)view); 4785924c869SLeon Alrae break; 4795924c869SLeon Alrae } 4805924c869SLeon Alrae 4815924c869SLeon Alrae } 4825924c869SLeon Alrae 48334fa7e83SLeon Alrae static const MemoryRegionOps itc_storage_ops = { 4845924c869SLeon Alrae .read = itc_storage_read, 4855924c869SLeon Alrae .write = itc_storage_write, 48634fa7e83SLeon Alrae .endianness = DEVICE_NATIVE_ENDIAN, 48734fa7e83SLeon Alrae }; 48834fa7e83SLeon Alrae 48934fa7e83SLeon Alrae static void itc_reset_cells(MIPSITUState *s) 49034fa7e83SLeon Alrae { 49134fa7e83SLeon Alrae int i; 49234fa7e83SLeon Alrae 49334fa7e83SLeon Alrae memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0])); 49434fa7e83SLeon Alrae 49534fa7e83SLeon Alrae for (i = 0; i < s->num_fifo; i++) { 49634fa7e83SLeon Alrae s->cell[i].tag.E = 1; 49734fa7e83SLeon Alrae s->cell[i].tag.FIFO = 1; 49834fa7e83SLeon Alrae s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT; 49934fa7e83SLeon Alrae } 50034fa7e83SLeon Alrae } 50134fa7e83SLeon Alrae 50234fa7e83SLeon Alrae static void mips_itu_init(Object *obj) 50334fa7e83SLeon Alrae { 50434fa7e83SLeon Alrae SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 50534fa7e83SLeon Alrae MIPSITUState *s = MIPS_ITU(obj); 50634fa7e83SLeon Alrae 50734fa7e83SLeon Alrae memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s, 50834fa7e83SLeon Alrae "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ); 50934fa7e83SLeon Alrae sysbus_init_mmio(sbd, &s->storage_io); 51034fa7e83SLeon Alrae 51134fa7e83SLeon Alrae memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s, 51234fa7e83SLeon Alrae "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ); 51334fa7e83SLeon Alrae } 51434fa7e83SLeon Alrae 51534fa7e83SLeon Alrae static void mips_itu_realize(DeviceState *dev, Error **errp) 51634fa7e83SLeon Alrae { 51734fa7e83SLeon Alrae MIPSITUState *s = MIPS_ITU(dev); 51834fa7e83SLeon Alrae 51934fa7e83SLeon Alrae if (s->num_fifo > ITC_FIFO_NUM_MAX) { 52034fa7e83SLeon Alrae error_setg(errp, "Exceed maximum number of FIFO cells: %d", 52134fa7e83SLeon Alrae s->num_fifo); 52234fa7e83SLeon Alrae return; 52334fa7e83SLeon Alrae } 52434fa7e83SLeon Alrae if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) { 52534fa7e83SLeon Alrae error_setg(errp, "Exceed maximum number of Semaphore cells: %d", 52634fa7e83SLeon Alrae s->num_semaphores); 52734fa7e83SLeon Alrae return; 52834fa7e83SLeon Alrae } 52934fa7e83SLeon Alrae 53034fa7e83SLeon Alrae s->cell = g_new(ITCStorageCell, get_num_cells(s)); 53134fa7e83SLeon Alrae } 53234fa7e83SLeon Alrae 53334fa7e83SLeon Alrae static void mips_itu_reset(DeviceState *dev) 53434fa7e83SLeon Alrae { 53534fa7e83SLeon Alrae MIPSITUState *s = MIPS_ITU(dev); 53634fa7e83SLeon Alrae 537043715d1SYongbok Kim if (s->saar_present) { 538043715d1SYongbok Kim *(uint64_t *) s->saar = 0x11 << 1; 539043715d1SYongbok Kim s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM; 540043715d1SYongbok Kim } else { 54134fa7e83SLeon Alrae s->ITCAddressMap[0] = 0; 54234fa7e83SLeon Alrae s->ITCAddressMap[1] = 54334fa7e83SLeon Alrae ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | 54434fa7e83SLeon Alrae (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); 545043715d1SYongbok Kim } 54634fa7e83SLeon Alrae itc_reconfigure(s); 54734fa7e83SLeon Alrae 54834fa7e83SLeon Alrae itc_reset_cells(s); 54934fa7e83SLeon Alrae } 55034fa7e83SLeon Alrae 55134fa7e83SLeon Alrae static Property mips_itu_properties[] = { 55210997f2dSPhilippe Mathieu-Daudé DEFINE_PROP_UINT32("num-fifo", MIPSITUState, num_fifo, 55334fa7e83SLeon Alrae ITC_FIFO_NUM_MAX), 55410997f2dSPhilippe Mathieu-Daudé DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, 55534fa7e83SLeon Alrae ITC_SEMAPH_NUM_MAX), 556043715d1SYongbok Kim DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), 55734fa7e83SLeon Alrae DEFINE_PROP_END_OF_LIST(), 55834fa7e83SLeon Alrae }; 55934fa7e83SLeon Alrae 56034fa7e83SLeon Alrae static void mips_itu_class_init(ObjectClass *klass, void *data) 56134fa7e83SLeon Alrae { 56234fa7e83SLeon Alrae DeviceClass *dc = DEVICE_CLASS(klass); 56334fa7e83SLeon Alrae 5644f67d30bSMarc-André Lureau device_class_set_props(dc, mips_itu_properties); 56534fa7e83SLeon Alrae dc->realize = mips_itu_realize; 56634fa7e83SLeon Alrae dc->reset = mips_itu_reset; 56734fa7e83SLeon Alrae } 56834fa7e83SLeon Alrae 56934fa7e83SLeon Alrae static const TypeInfo mips_itu_info = { 57034fa7e83SLeon Alrae .name = TYPE_MIPS_ITU, 57134fa7e83SLeon Alrae .parent = TYPE_SYS_BUS_DEVICE, 57234fa7e83SLeon Alrae .instance_size = sizeof(MIPSITUState), 57334fa7e83SLeon Alrae .instance_init = mips_itu_init, 57434fa7e83SLeon Alrae .class_init = mips_itu_class_init, 57534fa7e83SLeon Alrae }; 57634fa7e83SLeon Alrae 57734fa7e83SLeon Alrae static void mips_itu_register_types(void) 57834fa7e83SLeon Alrae { 57934fa7e83SLeon Alrae type_register_static(&mips_itu_info); 58034fa7e83SLeon Alrae } 58134fa7e83SLeon Alrae 58234fa7e83SLeon Alrae type_init(mips_itu_register_types) 583