134fa7e83SLeon Alrae /* 234fa7e83SLeon Alrae * Inter-Thread Communication Unit emulation. 334fa7e83SLeon Alrae * 434fa7e83SLeon Alrae * Copyright (c) 2016 Imagination Technologies 534fa7e83SLeon Alrae * 634fa7e83SLeon Alrae * This library is free software; you can redistribute it and/or 734fa7e83SLeon Alrae * modify it under the terms of the GNU Lesser General Public 834fa7e83SLeon Alrae * License as published by the Free Software Foundation; either 934fa7e83SLeon Alrae * version 2 of the License, or (at your option) any later version. 1034fa7e83SLeon Alrae * 1134fa7e83SLeon Alrae * This library is distributed in the hope that it will be useful, 1234fa7e83SLeon Alrae * but WITHOUT ANY WARRANTY; without even the implied warranty of 1334fa7e83SLeon Alrae * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1434fa7e83SLeon Alrae * Lesser General Public License for more details. 1534fa7e83SLeon Alrae * 1634fa7e83SLeon Alrae * You should have received a copy of the GNU Lesser General Public 1734fa7e83SLeon Alrae * License along with this library; if not, see <http://www.gnu.org/licenses/>. 1834fa7e83SLeon Alrae */ 1934fa7e83SLeon Alrae 2034fa7e83SLeon Alrae #include "qemu/osdep.h" 2134fa7e83SLeon Alrae #include "qapi/error.h" 2234fa7e83SLeon Alrae #include "hw/hw.h" 2334fa7e83SLeon Alrae #include "hw/sysbus.h" 2434fa7e83SLeon Alrae #include "sysemu/sysemu.h" 2534fa7e83SLeon Alrae #include "hw/misc/mips_itu.h" 2634fa7e83SLeon Alrae 2734fa7e83SLeon Alrae #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8) 2834fa7e83SLeon Alrae /* Initialize as 4kB area to fit all 32 cells with default 128B grain. 2934fa7e83SLeon Alrae Storage may be resized by the software. */ 3034fa7e83SLeon Alrae #define ITC_STORAGE_ADDRSPACE_SZ 0x1000 3134fa7e83SLeon Alrae 3234fa7e83SLeon Alrae #define ITC_FIFO_NUM_MAX 16 3334fa7e83SLeon Alrae #define ITC_SEMAPH_NUM_MAX 16 3434fa7e83SLeon Alrae #define ITC_AM1_NUMENTRIES_OFS 20 3534fa7e83SLeon Alrae 3640dc9dc3SLeon Alrae #define ITC_CELL_PV_MAX_VAL 0xFFFF 3740dc9dc3SLeon Alrae 385924c869SLeon Alrae #define ITC_CELL_TAG_FIFO_DEPTH 28 395924c869SLeon Alrae #define ITC_CELL_TAG_FIFO_PTR 18 405924c869SLeon Alrae #define ITC_CELL_TAG_FIFO 17 415924c869SLeon Alrae #define ITC_CELL_TAG_T 16 425924c869SLeon Alrae #define ITC_CELL_TAG_F 1 435924c869SLeon Alrae #define ITC_CELL_TAG_E 0 445924c869SLeon Alrae 4534fa7e83SLeon Alrae #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL 4634fa7e83SLeon Alrae #define ITC_AM0_EN_MASK 0x1 4734fa7e83SLeon Alrae 4834fa7e83SLeon Alrae #define ITC_AM1_ADDR_MASK_MASK 0x1FC00 4934fa7e83SLeon Alrae #define ITC_AM1_ENTRY_GRAIN_MASK 0x7 5034fa7e83SLeon Alrae 515924c869SLeon Alrae typedef enum ITCView { 525924c869SLeon Alrae ITCVIEW_BYPASS = 0, 535924c869SLeon Alrae ITCVIEW_CONTROL = 1, 545924c869SLeon Alrae ITCVIEW_EF_SYNC = 2, 555924c869SLeon Alrae ITCVIEW_EF_TRY = 3, 565924c869SLeon Alrae ITCVIEW_PV_SYNC = 4, 575924c869SLeon Alrae ITCVIEW_PV_TRY = 5 585924c869SLeon Alrae } ITCView; 595924c869SLeon Alrae 6034fa7e83SLeon Alrae MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) 6134fa7e83SLeon Alrae { 6234fa7e83SLeon Alrae return &itu->tag_io; 6334fa7e83SLeon Alrae } 6434fa7e83SLeon Alrae 6534fa7e83SLeon Alrae static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) 6634fa7e83SLeon Alrae { 6734fa7e83SLeon Alrae MIPSITUState *tag = (MIPSITUState *)opaque; 6834fa7e83SLeon Alrae uint64_t index = addr >> 3; 6934fa7e83SLeon Alrae 70*f2eb665aSLeon Alrae if (index >= ITC_ADDRESSMAP_NUM) { 7134fa7e83SLeon Alrae qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr); 72*f2eb665aSLeon Alrae return 0; 7334fa7e83SLeon Alrae } 7434fa7e83SLeon Alrae 75*f2eb665aSLeon Alrae return tag->ITCAddressMap[index]; 7634fa7e83SLeon Alrae } 7734fa7e83SLeon Alrae 7834fa7e83SLeon Alrae static void itc_reconfigure(MIPSITUState *tag) 7934fa7e83SLeon Alrae { 8034fa7e83SLeon Alrae uint64_t *am = &tag->ITCAddressMap[0]; 8134fa7e83SLeon Alrae MemoryRegion *mr = &tag->storage_io; 8234fa7e83SLeon Alrae hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; 8334fa7e83SLeon Alrae uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK); 8434fa7e83SLeon Alrae bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; 8534fa7e83SLeon Alrae 8634fa7e83SLeon Alrae memory_region_transaction_begin(); 8734fa7e83SLeon Alrae if (!(size & (size - 1))) { 8834fa7e83SLeon Alrae memory_region_set_size(mr, size); 8934fa7e83SLeon Alrae } 9034fa7e83SLeon Alrae memory_region_set_address(mr, address); 9134fa7e83SLeon Alrae memory_region_set_enabled(mr, is_enabled); 9234fa7e83SLeon Alrae memory_region_transaction_commit(); 9334fa7e83SLeon Alrae } 9434fa7e83SLeon Alrae 9534fa7e83SLeon Alrae static void itc_tag_write(void *opaque, hwaddr addr, 9634fa7e83SLeon Alrae uint64_t data, unsigned size) 9734fa7e83SLeon Alrae { 9834fa7e83SLeon Alrae MIPSITUState *tag = (MIPSITUState *)opaque; 9934fa7e83SLeon Alrae uint64_t *am = &tag->ITCAddressMap[0]; 10034fa7e83SLeon Alrae uint64_t am_old, mask; 10134fa7e83SLeon Alrae uint64_t index = addr >> 3; 10234fa7e83SLeon Alrae 10334fa7e83SLeon Alrae switch (index) { 10434fa7e83SLeon Alrae case 0: 10534fa7e83SLeon Alrae mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK; 10634fa7e83SLeon Alrae break; 10734fa7e83SLeon Alrae case 1: 10834fa7e83SLeon Alrae mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK; 10934fa7e83SLeon Alrae break; 11034fa7e83SLeon Alrae default: 11134fa7e83SLeon Alrae qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr); 11234fa7e83SLeon Alrae return; 11334fa7e83SLeon Alrae } 11434fa7e83SLeon Alrae 11534fa7e83SLeon Alrae am_old = am[index]; 11634fa7e83SLeon Alrae am[index] = (data & mask) | (am_old & ~mask); 11734fa7e83SLeon Alrae if (am_old != am[index]) { 11834fa7e83SLeon Alrae itc_reconfigure(tag); 11934fa7e83SLeon Alrae } 12034fa7e83SLeon Alrae } 12134fa7e83SLeon Alrae 12234fa7e83SLeon Alrae static const MemoryRegionOps itc_tag_ops = { 12334fa7e83SLeon Alrae .read = itc_tag_read, 12434fa7e83SLeon Alrae .write = itc_tag_write, 12534fa7e83SLeon Alrae .impl = { 12634fa7e83SLeon Alrae .max_access_size = 8, 12734fa7e83SLeon Alrae }, 12834fa7e83SLeon Alrae .endianness = DEVICE_NATIVE_ENDIAN, 12934fa7e83SLeon Alrae }; 13034fa7e83SLeon Alrae 13134fa7e83SLeon Alrae static inline uint32_t get_num_cells(MIPSITUState *s) 13234fa7e83SLeon Alrae { 13334fa7e83SLeon Alrae return s->num_fifo + s->num_semaphores; 13434fa7e83SLeon Alrae } 13534fa7e83SLeon Alrae 1365924c869SLeon Alrae static inline ITCView get_itc_view(hwaddr addr) 1375924c869SLeon Alrae { 1385924c869SLeon Alrae return (addr >> 3) & 0xf; 1395924c869SLeon Alrae } 1405924c869SLeon Alrae 1415924c869SLeon Alrae static inline int get_cell_stride_shift(const MIPSITUState *s) 1425924c869SLeon Alrae { 1435924c869SLeon Alrae /* Minimum interval (for EntryGain = 0) is 128 B */ 1445924c869SLeon Alrae return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); 1455924c869SLeon Alrae } 1465924c869SLeon Alrae 1475924c869SLeon Alrae static inline ITCStorageCell *get_cell(MIPSITUState *s, 1485924c869SLeon Alrae hwaddr addr) 1495924c869SLeon Alrae { 1505924c869SLeon Alrae uint32_t cell_idx = addr >> get_cell_stride_shift(s); 1515924c869SLeon Alrae uint32_t num_cells = get_num_cells(s); 1525924c869SLeon Alrae 1535924c869SLeon Alrae if (cell_idx >= num_cells) { 1545924c869SLeon Alrae cell_idx = num_cells - 1; 1555924c869SLeon Alrae } 1565924c869SLeon Alrae 1575924c869SLeon Alrae return &s->cell[cell_idx]; 1585924c869SLeon Alrae } 1595924c869SLeon Alrae 1604051089dSLeon Alrae static void wake_blocked_threads(ITCStorageCell *c) 1614051089dSLeon Alrae { 1624051089dSLeon Alrae CPUState *cs; 1634051089dSLeon Alrae CPU_FOREACH(cs) { 1644051089dSLeon Alrae if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) { 1654051089dSLeon Alrae cpu_interrupt(cs, CPU_INTERRUPT_WAKE); 1664051089dSLeon Alrae } 1674051089dSLeon Alrae } 1684051089dSLeon Alrae c->blocked_threads = 0; 1694051089dSLeon Alrae } 1704051089dSLeon Alrae 1714051089dSLeon Alrae static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c) 1724051089dSLeon Alrae { 1734051089dSLeon Alrae c->blocked_threads |= 1ULL << current_cpu->cpu_index; 1744051089dSLeon Alrae cpu_restore_state(current_cpu, current_cpu->mem_io_pc); 1754051089dSLeon Alrae current_cpu->halted = 1; 1764051089dSLeon Alrae current_cpu->exception_index = EXCP_HLT; 1774051089dSLeon Alrae cpu_loop_exit(current_cpu); 1784051089dSLeon Alrae } 1794051089dSLeon Alrae 18025a611e3SLeon Alrae /* ITC Bypass View */ 18125a611e3SLeon Alrae 18225a611e3SLeon Alrae static inline uint64_t view_bypass_read(ITCStorageCell *c) 18325a611e3SLeon Alrae { 18425a611e3SLeon Alrae if (c->tag.FIFO) { 18525a611e3SLeon Alrae return c->data[c->fifo_out]; 18625a611e3SLeon Alrae } else { 18725a611e3SLeon Alrae return c->data[0]; 18825a611e3SLeon Alrae } 18925a611e3SLeon Alrae } 19025a611e3SLeon Alrae 19125a611e3SLeon Alrae static inline void view_bypass_write(ITCStorageCell *c, uint64_t val) 19225a611e3SLeon Alrae { 19325a611e3SLeon Alrae if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) { 19425a611e3SLeon Alrae int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH; 19525a611e3SLeon Alrae c->data[idx] = val; 19625a611e3SLeon Alrae } 19725a611e3SLeon Alrae 19825a611e3SLeon Alrae /* ignore a write to the semaphore cell */ 19925a611e3SLeon Alrae } 20025a611e3SLeon Alrae 2015924c869SLeon Alrae /* ITC Control View */ 2025924c869SLeon Alrae 2035924c869SLeon Alrae static inline uint64_t view_control_read(ITCStorageCell *c) 2045924c869SLeon Alrae { 2055924c869SLeon Alrae return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) | 2065924c869SLeon Alrae (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) | 2075924c869SLeon Alrae (c->tag.FIFO << ITC_CELL_TAG_FIFO) | 2085924c869SLeon Alrae (c->tag.T << ITC_CELL_TAG_T) | 2095924c869SLeon Alrae (c->tag.E << ITC_CELL_TAG_E) | 2105924c869SLeon Alrae (c->tag.F << ITC_CELL_TAG_F); 2115924c869SLeon Alrae } 2125924c869SLeon Alrae 2135924c869SLeon Alrae static inline void view_control_write(ITCStorageCell *c, uint64_t val) 2145924c869SLeon Alrae { 2155924c869SLeon Alrae c->tag.T = (val >> ITC_CELL_TAG_T) & 1; 2165924c869SLeon Alrae c->tag.E = (val >> ITC_CELL_TAG_E) & 1; 2175924c869SLeon Alrae c->tag.F = (val >> ITC_CELL_TAG_F) & 1; 2185924c869SLeon Alrae 2195924c869SLeon Alrae if (c->tag.E) { 2205924c869SLeon Alrae c->tag.FIFOPtr = 0; 2215924c869SLeon Alrae } 2225924c869SLeon Alrae } 2235924c869SLeon Alrae 2244051089dSLeon Alrae /* ITC Empty/Full View */ 2254051089dSLeon Alrae 2264051089dSLeon Alrae static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking) 2274051089dSLeon Alrae { 2284051089dSLeon Alrae uint64_t ret = 0; 2294051089dSLeon Alrae 2304051089dSLeon Alrae if (!c->tag.FIFO) { 2314051089dSLeon Alrae return 0; 2324051089dSLeon Alrae } 2334051089dSLeon Alrae 2344051089dSLeon Alrae c->tag.F = 0; 2354051089dSLeon Alrae 2364051089dSLeon Alrae if (blocking && c->tag.E) { 2374051089dSLeon Alrae block_thread_and_exit(c); 2384051089dSLeon Alrae } 2394051089dSLeon Alrae 2404051089dSLeon Alrae if (c->blocked_threads) { 2414051089dSLeon Alrae wake_blocked_threads(c); 2424051089dSLeon Alrae } 2434051089dSLeon Alrae 2444051089dSLeon Alrae if (c->tag.FIFOPtr > 0) { 2454051089dSLeon Alrae ret = c->data[c->fifo_out]; 2464051089dSLeon Alrae c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH; 2474051089dSLeon Alrae c->tag.FIFOPtr--; 2484051089dSLeon Alrae } 2494051089dSLeon Alrae 2504051089dSLeon Alrae if (c->tag.FIFOPtr == 0) { 2514051089dSLeon Alrae c->tag.E = 1; 2524051089dSLeon Alrae } 2534051089dSLeon Alrae 2544051089dSLeon Alrae return ret; 2554051089dSLeon Alrae } 2564051089dSLeon Alrae 2574051089dSLeon Alrae static uint64_t view_ef_sync_read(ITCStorageCell *c) 2584051089dSLeon Alrae { 2594051089dSLeon Alrae return view_ef_common_read(c, true); 2604051089dSLeon Alrae } 2614051089dSLeon Alrae 2624051089dSLeon Alrae static uint64_t view_ef_try_read(ITCStorageCell *c) 2634051089dSLeon Alrae { 2644051089dSLeon Alrae return view_ef_common_read(c, false); 2654051089dSLeon Alrae } 2664051089dSLeon Alrae 2674051089dSLeon Alrae static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val, 2684051089dSLeon Alrae bool blocking) 2694051089dSLeon Alrae { 2704051089dSLeon Alrae if (!c->tag.FIFO) { 2714051089dSLeon Alrae return; 2724051089dSLeon Alrae } 2734051089dSLeon Alrae 2744051089dSLeon Alrae c->tag.E = 0; 2754051089dSLeon Alrae 2764051089dSLeon Alrae if (blocking && c->tag.F) { 2774051089dSLeon Alrae block_thread_and_exit(c); 2784051089dSLeon Alrae } 2794051089dSLeon Alrae 2804051089dSLeon Alrae if (c->blocked_threads) { 2814051089dSLeon Alrae wake_blocked_threads(c); 2824051089dSLeon Alrae } 2834051089dSLeon Alrae 2844051089dSLeon Alrae if (c->tag.FIFOPtr < ITC_CELL_DEPTH) { 2854051089dSLeon Alrae int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH; 2864051089dSLeon Alrae c->data[idx] = val; 2874051089dSLeon Alrae c->tag.FIFOPtr++; 2884051089dSLeon Alrae } 2894051089dSLeon Alrae 2904051089dSLeon Alrae if (c->tag.FIFOPtr == ITC_CELL_DEPTH) { 2914051089dSLeon Alrae c->tag.F = 1; 2924051089dSLeon Alrae } 2934051089dSLeon Alrae } 2944051089dSLeon Alrae 2954051089dSLeon Alrae static void view_ef_sync_write(ITCStorageCell *c, uint64_t val) 2964051089dSLeon Alrae { 2974051089dSLeon Alrae view_ef_common_write(c, val, true); 2984051089dSLeon Alrae } 2994051089dSLeon Alrae 3004051089dSLeon Alrae static void view_ef_try_write(ITCStorageCell *c, uint64_t val) 3014051089dSLeon Alrae { 3024051089dSLeon Alrae view_ef_common_write(c, val, false); 3034051089dSLeon Alrae } 3044051089dSLeon Alrae 30540dc9dc3SLeon Alrae /* ITC P/V View */ 30640dc9dc3SLeon Alrae 30740dc9dc3SLeon Alrae static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking) 30840dc9dc3SLeon Alrae { 30940dc9dc3SLeon Alrae uint64_t ret = c->data[0]; 31040dc9dc3SLeon Alrae 31140dc9dc3SLeon Alrae if (c->tag.FIFO) { 31240dc9dc3SLeon Alrae return 0; 31340dc9dc3SLeon Alrae } 31440dc9dc3SLeon Alrae 31540dc9dc3SLeon Alrae if (c->data[0] > 0) { 31640dc9dc3SLeon Alrae c->data[0]--; 31740dc9dc3SLeon Alrae } else if (blocking) { 31840dc9dc3SLeon Alrae block_thread_and_exit(c); 31940dc9dc3SLeon Alrae } 32040dc9dc3SLeon Alrae 32140dc9dc3SLeon Alrae return ret; 32240dc9dc3SLeon Alrae } 32340dc9dc3SLeon Alrae 32440dc9dc3SLeon Alrae static uint64_t view_pv_sync_read(ITCStorageCell *c) 32540dc9dc3SLeon Alrae { 32640dc9dc3SLeon Alrae return view_pv_common_read(c, true); 32740dc9dc3SLeon Alrae } 32840dc9dc3SLeon Alrae 32940dc9dc3SLeon Alrae static uint64_t view_pv_try_read(ITCStorageCell *c) 33040dc9dc3SLeon Alrae { 33140dc9dc3SLeon Alrae return view_pv_common_read(c, false); 33240dc9dc3SLeon Alrae } 33340dc9dc3SLeon Alrae 33440dc9dc3SLeon Alrae static inline void view_pv_common_write(ITCStorageCell *c) 33540dc9dc3SLeon Alrae { 33640dc9dc3SLeon Alrae if (c->tag.FIFO) { 33740dc9dc3SLeon Alrae return; 33840dc9dc3SLeon Alrae } 33940dc9dc3SLeon Alrae 34040dc9dc3SLeon Alrae if (c->data[0] < ITC_CELL_PV_MAX_VAL) { 34140dc9dc3SLeon Alrae c->data[0]++; 34240dc9dc3SLeon Alrae } 34340dc9dc3SLeon Alrae 34440dc9dc3SLeon Alrae if (c->blocked_threads) { 34540dc9dc3SLeon Alrae wake_blocked_threads(c); 34640dc9dc3SLeon Alrae } 34740dc9dc3SLeon Alrae } 34840dc9dc3SLeon Alrae 34940dc9dc3SLeon Alrae static void view_pv_sync_write(ITCStorageCell *c) 35040dc9dc3SLeon Alrae { 35140dc9dc3SLeon Alrae view_pv_common_write(c); 35240dc9dc3SLeon Alrae } 35340dc9dc3SLeon Alrae 35440dc9dc3SLeon Alrae static void view_pv_try_write(ITCStorageCell *c) 35540dc9dc3SLeon Alrae { 35640dc9dc3SLeon Alrae view_pv_common_write(c); 35740dc9dc3SLeon Alrae } 35840dc9dc3SLeon Alrae 3595924c869SLeon Alrae static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) 3605924c869SLeon Alrae { 3615924c869SLeon Alrae MIPSITUState *s = (MIPSITUState *)opaque; 3625924c869SLeon Alrae ITCStorageCell *cell = get_cell(s, addr); 3635924c869SLeon Alrae ITCView view = get_itc_view(addr); 3645924c869SLeon Alrae uint64_t ret = -1; 3655924c869SLeon Alrae 3665924c869SLeon Alrae switch (view) { 36725a611e3SLeon Alrae case ITCVIEW_BYPASS: 36825a611e3SLeon Alrae ret = view_bypass_read(cell); 36925a611e3SLeon Alrae break; 3705924c869SLeon Alrae case ITCVIEW_CONTROL: 3715924c869SLeon Alrae ret = view_control_read(cell); 3725924c869SLeon Alrae break; 3734051089dSLeon Alrae case ITCVIEW_EF_SYNC: 3744051089dSLeon Alrae ret = view_ef_sync_read(cell); 3754051089dSLeon Alrae break; 3764051089dSLeon Alrae case ITCVIEW_EF_TRY: 3774051089dSLeon Alrae ret = view_ef_try_read(cell); 3784051089dSLeon Alrae break; 37940dc9dc3SLeon Alrae case ITCVIEW_PV_SYNC: 38040dc9dc3SLeon Alrae ret = view_pv_sync_read(cell); 38140dc9dc3SLeon Alrae break; 38240dc9dc3SLeon Alrae case ITCVIEW_PV_TRY: 38340dc9dc3SLeon Alrae ret = view_pv_try_read(cell); 38440dc9dc3SLeon Alrae break; 3855924c869SLeon Alrae default: 3865924c869SLeon Alrae qemu_log_mask(LOG_GUEST_ERROR, 3875924c869SLeon Alrae "itc_storage_read: Bad ITC View %d\n", (int)view); 3885924c869SLeon Alrae break; 3895924c869SLeon Alrae } 3905924c869SLeon Alrae 3915924c869SLeon Alrae return ret; 3925924c869SLeon Alrae } 3935924c869SLeon Alrae 3945924c869SLeon Alrae static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, 3955924c869SLeon Alrae unsigned size) 3965924c869SLeon Alrae { 3975924c869SLeon Alrae MIPSITUState *s = (MIPSITUState *)opaque; 3985924c869SLeon Alrae ITCStorageCell *cell = get_cell(s, addr); 3995924c869SLeon Alrae ITCView view = get_itc_view(addr); 4005924c869SLeon Alrae 4015924c869SLeon Alrae switch (view) { 40225a611e3SLeon Alrae case ITCVIEW_BYPASS: 40325a611e3SLeon Alrae view_bypass_write(cell, data); 40425a611e3SLeon Alrae break; 4055924c869SLeon Alrae case ITCVIEW_CONTROL: 4065924c869SLeon Alrae view_control_write(cell, data); 4075924c869SLeon Alrae break; 4084051089dSLeon Alrae case ITCVIEW_EF_SYNC: 4094051089dSLeon Alrae view_ef_sync_write(cell, data); 4104051089dSLeon Alrae break; 4114051089dSLeon Alrae case ITCVIEW_EF_TRY: 4124051089dSLeon Alrae view_ef_try_write(cell, data); 4134051089dSLeon Alrae break; 41440dc9dc3SLeon Alrae case ITCVIEW_PV_SYNC: 41540dc9dc3SLeon Alrae view_pv_sync_write(cell); 41640dc9dc3SLeon Alrae break; 41740dc9dc3SLeon Alrae case ITCVIEW_PV_TRY: 41840dc9dc3SLeon Alrae view_pv_try_write(cell); 41940dc9dc3SLeon Alrae break; 4205924c869SLeon Alrae default: 4215924c869SLeon Alrae qemu_log_mask(LOG_GUEST_ERROR, 4225924c869SLeon Alrae "itc_storage_write: Bad ITC View %d\n", (int)view); 4235924c869SLeon Alrae break; 4245924c869SLeon Alrae } 4255924c869SLeon Alrae 4265924c869SLeon Alrae } 4275924c869SLeon Alrae 42834fa7e83SLeon Alrae static const MemoryRegionOps itc_storage_ops = { 4295924c869SLeon Alrae .read = itc_storage_read, 4305924c869SLeon Alrae .write = itc_storage_write, 43134fa7e83SLeon Alrae .endianness = DEVICE_NATIVE_ENDIAN, 43234fa7e83SLeon Alrae }; 43334fa7e83SLeon Alrae 43434fa7e83SLeon Alrae static void itc_reset_cells(MIPSITUState *s) 43534fa7e83SLeon Alrae { 43634fa7e83SLeon Alrae int i; 43734fa7e83SLeon Alrae 43834fa7e83SLeon Alrae memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0])); 43934fa7e83SLeon Alrae 44034fa7e83SLeon Alrae for (i = 0; i < s->num_fifo; i++) { 44134fa7e83SLeon Alrae s->cell[i].tag.E = 1; 44234fa7e83SLeon Alrae s->cell[i].tag.FIFO = 1; 44334fa7e83SLeon Alrae s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT; 44434fa7e83SLeon Alrae } 44534fa7e83SLeon Alrae } 44634fa7e83SLeon Alrae 44734fa7e83SLeon Alrae static void mips_itu_init(Object *obj) 44834fa7e83SLeon Alrae { 44934fa7e83SLeon Alrae SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 45034fa7e83SLeon Alrae MIPSITUState *s = MIPS_ITU(obj); 45134fa7e83SLeon Alrae 45234fa7e83SLeon Alrae memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s, 45334fa7e83SLeon Alrae "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ); 45434fa7e83SLeon Alrae sysbus_init_mmio(sbd, &s->storage_io); 45534fa7e83SLeon Alrae 45634fa7e83SLeon Alrae memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s, 45734fa7e83SLeon Alrae "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ); 45834fa7e83SLeon Alrae } 45934fa7e83SLeon Alrae 46034fa7e83SLeon Alrae static void mips_itu_realize(DeviceState *dev, Error **errp) 46134fa7e83SLeon Alrae { 46234fa7e83SLeon Alrae MIPSITUState *s = MIPS_ITU(dev); 46334fa7e83SLeon Alrae 46434fa7e83SLeon Alrae if (s->num_fifo > ITC_FIFO_NUM_MAX) { 46534fa7e83SLeon Alrae error_setg(errp, "Exceed maximum number of FIFO cells: %d", 46634fa7e83SLeon Alrae s->num_fifo); 46734fa7e83SLeon Alrae return; 46834fa7e83SLeon Alrae } 46934fa7e83SLeon Alrae if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) { 47034fa7e83SLeon Alrae error_setg(errp, "Exceed maximum number of Semaphore cells: %d", 47134fa7e83SLeon Alrae s->num_semaphores); 47234fa7e83SLeon Alrae return; 47334fa7e83SLeon Alrae } 47434fa7e83SLeon Alrae 47534fa7e83SLeon Alrae s->cell = g_new(ITCStorageCell, get_num_cells(s)); 47634fa7e83SLeon Alrae } 47734fa7e83SLeon Alrae 47834fa7e83SLeon Alrae static void mips_itu_reset(DeviceState *dev) 47934fa7e83SLeon Alrae { 48034fa7e83SLeon Alrae MIPSITUState *s = MIPS_ITU(dev); 48134fa7e83SLeon Alrae 48234fa7e83SLeon Alrae s->ITCAddressMap[0] = 0; 48334fa7e83SLeon Alrae s->ITCAddressMap[1] = 48434fa7e83SLeon Alrae ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | 48534fa7e83SLeon Alrae (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); 48634fa7e83SLeon Alrae itc_reconfigure(s); 48734fa7e83SLeon Alrae 48834fa7e83SLeon Alrae itc_reset_cells(s); 48934fa7e83SLeon Alrae } 49034fa7e83SLeon Alrae 49134fa7e83SLeon Alrae static Property mips_itu_properties[] = { 49234fa7e83SLeon Alrae DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, 49334fa7e83SLeon Alrae ITC_FIFO_NUM_MAX), 49434fa7e83SLeon Alrae DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores, 49534fa7e83SLeon Alrae ITC_SEMAPH_NUM_MAX), 49634fa7e83SLeon Alrae DEFINE_PROP_END_OF_LIST(), 49734fa7e83SLeon Alrae }; 49834fa7e83SLeon Alrae 49934fa7e83SLeon Alrae static void mips_itu_class_init(ObjectClass *klass, void *data) 50034fa7e83SLeon Alrae { 50134fa7e83SLeon Alrae DeviceClass *dc = DEVICE_CLASS(klass); 50234fa7e83SLeon Alrae 50334fa7e83SLeon Alrae dc->props = mips_itu_properties; 50434fa7e83SLeon Alrae dc->realize = mips_itu_realize; 50534fa7e83SLeon Alrae dc->reset = mips_itu_reset; 50634fa7e83SLeon Alrae } 50734fa7e83SLeon Alrae 50834fa7e83SLeon Alrae static const TypeInfo mips_itu_info = { 50934fa7e83SLeon Alrae .name = TYPE_MIPS_ITU, 51034fa7e83SLeon Alrae .parent = TYPE_SYS_BUS_DEVICE, 51134fa7e83SLeon Alrae .instance_size = sizeof(MIPSITUState), 51234fa7e83SLeon Alrae .instance_init = mips_itu_init, 51334fa7e83SLeon Alrae .class_init = mips_itu_class_init, 51434fa7e83SLeon Alrae }; 51534fa7e83SLeon Alrae 51634fa7e83SLeon Alrae static void mips_itu_register_types(void) 51734fa7e83SLeon Alrae { 51834fa7e83SLeon Alrae type_register_static(&mips_itu_info); 51934fa7e83SLeon Alrae } 52034fa7e83SLeon Alrae 52134fa7e83SLeon Alrae type_init(mips_itu_register_types) 522