xref: /qemu/hw/misc/mips_itu.c (revision 3d100d0f) 
1 /*
2  * Inter-Thread Communication Unit emulation.
3  *
4  * Copyright (c) 2016 Imagination Technologies
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "hw/hw.h"
23 #include "hw/sysbus.h"
24 #include "sysemu/sysemu.h"
25 #include "hw/misc/mips_itu.h"
26 
27 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
28 /* Initialize as 4kB area to fit all 32 cells with default 128B grain.
29    Storage may be resized by the software. */
30 #define ITC_STORAGE_ADDRSPACE_SZ 0x1000
31 
32 #define ITC_FIFO_NUM_MAX 16
33 #define ITC_SEMAPH_NUM_MAX 16
34 #define ITC_AM1_NUMENTRIES_OFS 20
35 
36 #define ITC_CELL_PV_MAX_VAL 0xFFFF
37 
38 #define ITC_CELL_TAG_FIFO_DEPTH 28
39 #define ITC_CELL_TAG_FIFO_PTR 18
40 #define ITC_CELL_TAG_FIFO 17
41 #define ITC_CELL_TAG_T 16
42 #define ITC_CELL_TAG_F 1
43 #define ITC_CELL_TAG_E 0
44 
45 #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
46 #define ITC_AM0_EN_MASK 0x1
47 
48 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00
49 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7
50 
51 typedef enum ITCView {
52     ITCVIEW_BYPASS  = 0,
53     ITCVIEW_CONTROL = 1,
54     ITCVIEW_EF_SYNC = 2,
55     ITCVIEW_EF_TRY  = 3,
56     ITCVIEW_PV_SYNC = 4,
57     ITCVIEW_PV_TRY  = 5
58 } ITCView;
59 
60 MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
61 {
62     return &itu->tag_io;
63 }
64 
65 static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
66 {
67     MIPSITUState *tag = (MIPSITUState *)opaque;
68     uint64_t index = addr >> 3;
69     uint64_t ret = 0;
70 
71     switch (index) {
72     case 0 ... ITC_ADDRESSMAP_NUM:
73         ret = tag->ITCAddressMap[index];
74         break;
75     default:
76         qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
77         break;
78     }
79 
80     return ret;
81 }
82 
83 static void itc_reconfigure(MIPSITUState *tag)
84 {
85     uint64_t *am = &tag->ITCAddressMap[0];
86     MemoryRegion *mr = &tag->storage_io;
87     hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
88     uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
89     bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
90 
91     memory_region_transaction_begin();
92     if (!(size & (size - 1))) {
93         memory_region_set_size(mr, size);
94     }
95     memory_region_set_address(mr, address);
96     memory_region_set_enabled(mr, is_enabled);
97     memory_region_transaction_commit();
98 }
99 
100 static void itc_tag_write(void *opaque, hwaddr addr,
101                           uint64_t data, unsigned size)
102 {
103     MIPSITUState *tag = (MIPSITUState *)opaque;
104     uint64_t *am = &tag->ITCAddressMap[0];
105     uint64_t am_old, mask;
106     uint64_t index = addr >> 3;
107 
108     switch (index) {
109     case 0:
110         mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
111         break;
112     case 1:
113         mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
114         break;
115     default:
116         qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
117         return;
118     }
119 
120     am_old = am[index];
121     am[index] = (data & mask) | (am_old & ~mask);
122     if (am_old != am[index]) {
123         itc_reconfigure(tag);
124     }
125 }
126 
127 static const MemoryRegionOps itc_tag_ops = {
128     .read = itc_tag_read,
129     .write = itc_tag_write,
130     .impl = {
131         .max_access_size = 8,
132     },
133     .endianness = DEVICE_NATIVE_ENDIAN,
134 };
135 
136 static inline uint32_t get_num_cells(MIPSITUState *s)
137 {
138     return s->num_fifo + s->num_semaphores;
139 }
140 
141 static inline ITCView get_itc_view(hwaddr addr)
142 {
143     return (addr >> 3) & 0xf;
144 }
145 
146 static inline int get_cell_stride_shift(const MIPSITUState *s)
147 {
148     /* Minimum interval (for EntryGain = 0) is 128 B */
149     return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
150 }
151 
152 static inline ITCStorageCell *get_cell(MIPSITUState *s,
153                                        hwaddr addr)
154 {
155     uint32_t cell_idx = addr >> get_cell_stride_shift(s);
156     uint32_t num_cells = get_num_cells(s);
157 
158     if (cell_idx >= num_cells) {
159         cell_idx = num_cells - 1;
160     }
161 
162     return &s->cell[cell_idx];
163 }
164 
165 static void wake_blocked_threads(ITCStorageCell *c)
166 {
167     CPUState *cs;
168     CPU_FOREACH(cs) {
169         if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
170             cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
171         }
172     }
173     c->blocked_threads = 0;
174 }
175 
176 static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
177 {
178     c->blocked_threads |= 1ULL << current_cpu->cpu_index;
179     cpu_restore_state(current_cpu, current_cpu->mem_io_pc);
180     current_cpu->halted = 1;
181     current_cpu->exception_index = EXCP_HLT;
182     cpu_loop_exit(current_cpu);
183 }
184 
185 /* ITC Bypass View */
186 
187 static inline uint64_t view_bypass_read(ITCStorageCell *c)
188 {
189     if (c->tag.FIFO) {
190         return c->data[c->fifo_out];
191     } else {
192         return c->data[0];
193     }
194 }
195 
196 static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
197 {
198     if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
199         int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
200         c->data[idx] = val;
201     }
202 
203     /* ignore a write to the semaphore cell */
204 }
205 
206 /* ITC Control View */
207 
208 static inline uint64_t view_control_read(ITCStorageCell *c)
209 {
210     return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
211            (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
212            (c->tag.FIFO << ITC_CELL_TAG_FIFO) |
213            (c->tag.T << ITC_CELL_TAG_T) |
214            (c->tag.E << ITC_CELL_TAG_E) |
215            (c->tag.F << ITC_CELL_TAG_F);
216 }
217 
218 static inline void view_control_write(ITCStorageCell *c, uint64_t val)
219 {
220     c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
221     c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
222     c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
223 
224     if (c->tag.E) {
225         c->tag.FIFOPtr = 0;
226     }
227 }
228 
229 /* ITC Empty/Full View */
230 
231 static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
232 {
233     uint64_t ret = 0;
234 
235     if (!c->tag.FIFO) {
236         return 0;
237     }
238 
239     c->tag.F = 0;
240 
241     if (blocking && c->tag.E) {
242         block_thread_and_exit(c);
243     }
244 
245     if (c->blocked_threads) {
246         wake_blocked_threads(c);
247     }
248 
249     if (c->tag.FIFOPtr > 0) {
250         ret = c->data[c->fifo_out];
251         c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
252         c->tag.FIFOPtr--;
253     }
254 
255     if (c->tag.FIFOPtr == 0) {
256         c->tag.E = 1;
257     }
258 
259     return ret;
260 }
261 
262 static uint64_t view_ef_sync_read(ITCStorageCell *c)
263 {
264     return view_ef_common_read(c, true);
265 }
266 
267 static uint64_t view_ef_try_read(ITCStorageCell *c)
268 {
269     return view_ef_common_read(c, false);
270 }
271 
272 static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
273                                         bool blocking)
274 {
275     if (!c->tag.FIFO) {
276         return;
277     }
278 
279     c->tag.E = 0;
280 
281     if (blocking && c->tag.F) {
282         block_thread_and_exit(c);
283     }
284 
285     if (c->blocked_threads) {
286         wake_blocked_threads(c);
287     }
288 
289     if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
290         int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
291         c->data[idx] = val;
292         c->tag.FIFOPtr++;
293     }
294 
295     if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
296         c->tag.F = 1;
297     }
298 }
299 
300 static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
301 {
302     view_ef_common_write(c, val, true);
303 }
304 
305 static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
306 {
307     view_ef_common_write(c, val, false);
308 }
309 
310 /* ITC P/V View */
311 
312 static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
313 {
314     uint64_t ret = c->data[0];
315 
316     if (c->tag.FIFO) {
317         return 0;
318     }
319 
320     if (c->data[0] > 0) {
321         c->data[0]--;
322     } else if (blocking) {
323         block_thread_and_exit(c);
324     }
325 
326     return ret;
327 }
328 
329 static uint64_t view_pv_sync_read(ITCStorageCell *c)
330 {
331     return view_pv_common_read(c, true);
332 }
333 
334 static uint64_t view_pv_try_read(ITCStorageCell *c)
335 {
336     return view_pv_common_read(c, false);
337 }
338 
339 static inline void view_pv_common_write(ITCStorageCell *c)
340 {
341     if (c->tag.FIFO) {
342         return;
343     }
344 
345     if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
346         c->data[0]++;
347     }
348 
349     if (c->blocked_threads) {
350         wake_blocked_threads(c);
351     }
352 }
353 
354 static void view_pv_sync_write(ITCStorageCell *c)
355 {
356     view_pv_common_write(c);
357 }
358 
359 static void view_pv_try_write(ITCStorageCell *c)
360 {
361     view_pv_common_write(c);
362 }
363 
364 static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
365 {
366     MIPSITUState *s = (MIPSITUState *)opaque;
367     ITCStorageCell *cell = get_cell(s, addr);
368     ITCView view = get_itc_view(addr);
369     uint64_t ret = -1;
370 
371     switch (view) {
372     case ITCVIEW_BYPASS:
373         ret = view_bypass_read(cell);
374         break;
375     case ITCVIEW_CONTROL:
376         ret = view_control_read(cell);
377         break;
378     case ITCVIEW_EF_SYNC:
379         ret = view_ef_sync_read(cell);
380         break;
381     case ITCVIEW_EF_TRY:
382         ret = view_ef_try_read(cell);
383         break;
384     case ITCVIEW_PV_SYNC:
385         ret = view_pv_sync_read(cell);
386         break;
387     case ITCVIEW_PV_TRY:
388         ret = view_pv_try_read(cell);
389         break;
390     default:
391         qemu_log_mask(LOG_GUEST_ERROR,
392                       "itc_storage_read: Bad ITC View %d\n", (int)view);
393         break;
394     }
395 
396     return ret;
397 }
398 
399 static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
400                               unsigned size)
401 {
402     MIPSITUState *s = (MIPSITUState *)opaque;
403     ITCStorageCell *cell = get_cell(s, addr);
404     ITCView view = get_itc_view(addr);
405 
406     switch (view) {
407     case ITCVIEW_BYPASS:
408         view_bypass_write(cell, data);
409         break;
410     case ITCVIEW_CONTROL:
411         view_control_write(cell, data);
412         break;
413     case ITCVIEW_EF_SYNC:
414         view_ef_sync_write(cell, data);
415         break;
416     case ITCVIEW_EF_TRY:
417         view_ef_try_write(cell, data);
418         break;
419     case ITCVIEW_PV_SYNC:
420         view_pv_sync_write(cell);
421         break;
422     case ITCVIEW_PV_TRY:
423         view_pv_try_write(cell);
424         break;
425     default:
426         qemu_log_mask(LOG_GUEST_ERROR,
427                       "itc_storage_write: Bad ITC View %d\n", (int)view);
428         break;
429     }
430 
431 }
432 
433 static const MemoryRegionOps itc_storage_ops = {
434     .read = itc_storage_read,
435     .write = itc_storage_write,
436     .endianness = DEVICE_NATIVE_ENDIAN,
437 };
438 
439 static void itc_reset_cells(MIPSITUState *s)
440 {
441     int i;
442 
443     memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
444 
445     for (i = 0; i < s->num_fifo; i++) {
446         s->cell[i].tag.E = 1;
447         s->cell[i].tag.FIFO = 1;
448         s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
449     }
450 }
451 
452 static void mips_itu_init(Object *obj)
453 {
454     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
455     MIPSITUState *s = MIPS_ITU(obj);
456 
457     memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
458                           "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
459     sysbus_init_mmio(sbd, &s->storage_io);
460 
461     memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
462                           "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
463 }
464 
465 static void mips_itu_realize(DeviceState *dev, Error **errp)
466 {
467     MIPSITUState *s = MIPS_ITU(dev);
468 
469     if (s->num_fifo > ITC_FIFO_NUM_MAX) {
470         error_setg(errp, "Exceed maximum number of FIFO cells: %d",
471                    s->num_fifo);
472         return;
473     }
474     if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
475         error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
476                    s->num_semaphores);
477         return;
478     }
479 
480     s->cell = g_new(ITCStorageCell, get_num_cells(s));
481 }
482 
483 static void mips_itu_reset(DeviceState *dev)
484 {
485     MIPSITUState *s = MIPS_ITU(dev);
486 
487     s->ITCAddressMap[0] = 0;
488     s->ITCAddressMap[1] =
489         ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
490         (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
491     itc_reconfigure(s);
492 
493     itc_reset_cells(s);
494 }
495 
496 static Property mips_itu_properties[] = {
497     DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
498                       ITC_FIFO_NUM_MAX),
499     DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
500                       ITC_SEMAPH_NUM_MAX),
501     DEFINE_PROP_END_OF_LIST(),
502 };
503 
504 static void mips_itu_class_init(ObjectClass *klass, void *data)
505 {
506     DeviceClass *dc = DEVICE_CLASS(klass);
507 
508     dc->props = mips_itu_properties;
509     dc->realize = mips_itu_realize;
510     dc->reset = mips_itu_reset;
511 }
512 
513 static const TypeInfo mips_itu_info = {
514     .name          = TYPE_MIPS_ITU,
515     .parent        = TYPE_SYS_BUS_DEVICE,
516     .instance_size = sizeof(MIPSITUState),
517     .instance_init = mips_itu_init,
518     .class_init    = mips_itu_class_init,
519 };
520 
521 static void mips_itu_register_types(void)
522 {
523     type_register_static(&mips_itu_info);
524 }
525 
526 type_init(mips_itu_register_types)
527