1 /* 2 * PXA270-based Intel Mainstone platforms. 3 * FPGA driver 4 * 5 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or 6 * <akuster@mvista.com> 7 * 8 * This code is licensed under the GNU GPL v2. 9 * 10 * Contributions after 2012-01-13 are licensed under the terms of the 11 * GNU GPL, version 2 or (at your option) any later version. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "hw/irq.h" 16 #include "hw/sysbus.h" 17 #include "migration/vmstate.h" 18 #include "qemu/module.h" 19 #include "qom/object.h" 20 21 /* Mainstone FPGA for extern irqs */ 22 #define FPGA_GPIO_PIN 0 23 #define MST_NUM_IRQS 16 24 #define MST_LEDDAT1 0x10 25 #define MST_LEDDAT2 0x14 26 #define MST_LEDCTRL 0x40 27 #define MST_GPSWR 0x60 28 #define MST_MSCWR1 0x80 29 #define MST_MSCWR2 0x84 30 #define MST_MSCWR3 0x88 31 #define MST_MSCRD 0x90 32 #define MST_INTMSKENA 0xc0 33 #define MST_INTSETCLR 0xd0 34 #define MST_PCMCIA0 0xe0 35 #define MST_PCMCIA1 0xe4 36 37 #define MST_PCMCIAx_READY (1 << 10) 38 #define MST_PCMCIAx_nCD (1 << 5) 39 40 #define MST_PCMCIA_CD0_IRQ 9 41 #define MST_PCMCIA_CD1_IRQ 13 42 43 #define TYPE_MAINSTONE_FPGA "mainstone-fpga" 44 typedef struct mst_irq_state mst_irq_state; 45 DECLARE_INSTANCE_CHECKER(mst_irq_state, MAINSTONE_FPGA, 46 TYPE_MAINSTONE_FPGA) 47 48 struct mst_irq_state { 49 SysBusDevice parent_obj; 50 51 MemoryRegion iomem; 52 53 qemu_irq parent; 54 55 uint32_t prev_level; 56 uint32_t leddat1; 57 uint32_t leddat2; 58 uint32_t ledctrl; 59 uint32_t gpswr; 60 uint32_t mscwr1; 61 uint32_t mscwr2; 62 uint32_t mscwr3; 63 uint32_t mscrd; 64 uint32_t intmskena; 65 uint32_t intsetclr; 66 uint32_t pcmcia0; 67 uint32_t pcmcia1; 68 }; 69 70 static void 71 mst_fpga_set_irq(void *opaque, int irq, int level) 72 { 73 mst_irq_state *s = (mst_irq_state *)opaque; 74 uint32_t oldint = s->intsetclr & s->intmskena; 75 76 if (level) 77 s->prev_level |= 1u << irq; 78 else 79 s->prev_level &= ~(1u << irq); 80 81 switch(irq) { 82 case MST_PCMCIA_CD0_IRQ: 83 if (level) 84 s->pcmcia0 &= ~MST_PCMCIAx_nCD; 85 else 86 s->pcmcia0 |= MST_PCMCIAx_nCD; 87 break; 88 case MST_PCMCIA_CD1_IRQ: 89 if (level) 90 s->pcmcia1 &= ~MST_PCMCIAx_nCD; 91 else 92 s->pcmcia1 |= MST_PCMCIAx_nCD; 93 break; 94 } 95 96 if ((s->intmskena & (1u << irq)) && level) 97 s->intsetclr |= 1u << irq; 98 99 if (oldint != (s->intsetclr & s->intmskena)) 100 qemu_set_irq(s->parent, s->intsetclr & s->intmskena); 101 } 102 103 104 static uint64_t 105 mst_fpga_readb(void *opaque, hwaddr addr, unsigned size) 106 { 107 mst_irq_state *s = (mst_irq_state *) opaque; 108 109 switch (addr) { 110 case MST_LEDDAT1: 111 return s->leddat1; 112 case MST_LEDDAT2: 113 return s->leddat2; 114 case MST_LEDCTRL: 115 return s->ledctrl; 116 case MST_GPSWR: 117 return s->gpswr; 118 case MST_MSCWR1: 119 return s->mscwr1; 120 case MST_MSCWR2: 121 return s->mscwr2; 122 case MST_MSCWR3: 123 return s->mscwr3; 124 case MST_MSCRD: 125 return s->mscrd; 126 case MST_INTMSKENA: 127 return s->intmskena; 128 case MST_INTSETCLR: 129 return s->intsetclr; 130 case MST_PCMCIA0: 131 return s->pcmcia0; 132 case MST_PCMCIA1: 133 return s->pcmcia1; 134 default: 135 printf("Mainstone - mst_fpga_readb: Bad register offset " 136 "0x" TARGET_FMT_plx "\n", addr); 137 } 138 return 0; 139 } 140 141 static void 142 mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, 143 unsigned size) 144 { 145 mst_irq_state *s = (mst_irq_state *) opaque; 146 value &= 0xffffffff; 147 148 switch (addr) { 149 case MST_LEDDAT1: 150 s->leddat1 = value; 151 break; 152 case MST_LEDDAT2: 153 s->leddat2 = value; 154 break; 155 case MST_LEDCTRL: 156 s->ledctrl = value; 157 break; 158 case MST_GPSWR: 159 s->gpswr = value; 160 break; 161 case MST_MSCWR1: 162 s->mscwr1 = value; 163 break; 164 case MST_MSCWR2: 165 s->mscwr2 = value; 166 break; 167 case MST_MSCWR3: 168 s->mscwr3 = value; 169 break; 170 case MST_MSCRD: 171 s->mscrd = value; 172 break; 173 case MST_INTMSKENA: /* Mask interrupt */ 174 s->intmskena = (value & 0xFEEFF); 175 qemu_set_irq(s->parent, s->intsetclr & s->intmskena); 176 break; 177 case MST_INTSETCLR: /* clear or set interrupt */ 178 s->intsetclr = (value & 0xFEEFF); 179 qemu_set_irq(s->parent, s->intsetclr & s->intmskena); 180 break; 181 /* For PCMCIAx allow the to change only power and reset */ 182 case MST_PCMCIA0: 183 s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f); 184 break; 185 case MST_PCMCIA1: 186 s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f); 187 break; 188 default: 189 printf("Mainstone - mst_fpga_writeb: Bad register offset " 190 "0x" TARGET_FMT_plx "\n", addr); 191 } 192 } 193 194 static const MemoryRegionOps mst_fpga_ops = { 195 .read = mst_fpga_readb, 196 .write = mst_fpga_writeb, 197 .endianness = DEVICE_NATIVE_ENDIAN, 198 }; 199 200 static int mst_fpga_post_load(void *opaque, int version_id) 201 { 202 mst_irq_state *s = (mst_irq_state *) opaque; 203 204 qemu_set_irq(s->parent, s->intsetclr & s->intmskena); 205 return 0; 206 } 207 208 static void mst_fpga_init(Object *obj) 209 { 210 DeviceState *dev = DEVICE(obj); 211 mst_irq_state *s = MAINSTONE_FPGA(obj); 212 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 213 214 s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD; 215 s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD; 216 217 sysbus_init_irq(sbd, &s->parent); 218 219 /* alloc the external 16 irqs */ 220 qdev_init_gpio_in(dev, mst_fpga_set_irq, MST_NUM_IRQS); 221 222 memory_region_init_io(&s->iomem, obj, &mst_fpga_ops, s, 223 "fpga", 0x00100000); 224 sysbus_init_mmio(sbd, &s->iomem); 225 } 226 227 static VMStateDescription vmstate_mst_fpga_regs = { 228 .name = "mainstone_fpga", 229 .version_id = 0, 230 .minimum_version_id = 0, 231 .post_load = mst_fpga_post_load, 232 .fields = (VMStateField[]) { 233 VMSTATE_UINT32(prev_level, mst_irq_state), 234 VMSTATE_UINT32(leddat1, mst_irq_state), 235 VMSTATE_UINT32(leddat2, mst_irq_state), 236 VMSTATE_UINT32(ledctrl, mst_irq_state), 237 VMSTATE_UINT32(gpswr, mst_irq_state), 238 VMSTATE_UINT32(mscwr1, mst_irq_state), 239 VMSTATE_UINT32(mscwr2, mst_irq_state), 240 VMSTATE_UINT32(mscwr3, mst_irq_state), 241 VMSTATE_UINT32(mscrd, mst_irq_state), 242 VMSTATE_UINT32(intmskena, mst_irq_state), 243 VMSTATE_UINT32(intsetclr, mst_irq_state), 244 VMSTATE_UINT32(pcmcia0, mst_irq_state), 245 VMSTATE_UINT32(pcmcia1, mst_irq_state), 246 VMSTATE_END_OF_LIST(), 247 }, 248 }; 249 250 static void mst_fpga_class_init(ObjectClass *klass, void *data) 251 { 252 DeviceClass *dc = DEVICE_CLASS(klass); 253 254 dc->desc = "Mainstone II FPGA"; 255 dc->vmsd = &vmstate_mst_fpga_regs; 256 } 257 258 static const TypeInfo mst_fpga_info = { 259 .name = TYPE_MAINSTONE_FPGA, 260 .parent = TYPE_SYS_BUS_DEVICE, 261 .instance_size = sizeof(mst_irq_state), 262 .instance_init = mst_fpga_init, 263 .class_init = mst_fpga_class_init, 264 }; 265 266 static void mst_fpga_register_types(void) 267 { 268 type_register_static(&mst_fpga_info); 269 } 270 271 type_init(mst_fpga_register_types) 272