1 /* 2 * STM32L4X5 RCC (Reset and clock control) 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * The reference used is the STMicroElectronics RM0351 Reference manual 13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 14 * 15 * Inspired by the BCM2835 CPRMAN clock manager implementation by Luc Michel. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "qemu/timer.h" 22 #include "qapi/error.h" 23 #include "migration/vmstate.h" 24 #include "hw/misc/stm32l4x5_rcc.h" 25 #include "hw/misc/stm32l4x5_rcc_internals.h" 26 #include "hw/clock.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-clock.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "hw/registerfields.h" 32 #include "trace.h" 33 34 #define HSE_DEFAULT_FRQ 48000000ULL 35 #define HSI_FRQ 16000000ULL 36 #define MSI_DEFAULT_FRQ 4000000ULL 37 #define LSE_FRQ 32768ULL 38 #define LSI_FRQ 32000ULL 39 40 /* 41 * Function to simply acknowledge and propagate changes in a clock mux 42 * frequency. 43 * `bypass_source` allows to bypass the period of the current source and just 44 * consider it equal to 0. This is useful during the hold phase of reset. 45 */ 46 static void clock_mux_update(RccClockMuxState *mux, bool bypass_source) 47 { 48 uint64_t src_freq; 49 Clock *current_source = mux->srcs[mux->src]; 50 uint32_t freq_multiplier = 0; 51 bool clk_changed = false; 52 53 /* 54 * To avoid rounding errors, we use the clock period instead of the 55 * frequency. 56 * This means that the multiplier of the mux becomes the divider of 57 * the clock and the divider of the mux becomes the multiplier of the 58 * clock. 59 */ 60 if (!bypass_source && mux->enabled && mux->divider) { 61 freq_multiplier = mux->divider; 62 } 63 64 clk_changed |= clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier); 65 clk_changed |= clock_set(mux->out, clock_get(current_source)); 66 if (clk_changed) { 67 clock_propagate(mux->out); 68 } 69 70 src_freq = clock_get_hz(current_source); 71 /* TODO: can we simply detect if the config changed so that we reduce log spam ? */ 72 trace_stm32l4x5_rcc_mux_update(mux->id, mux->src, src_freq, 73 mux->multiplier, mux->divider); 74 } 75 76 static void clock_mux_src_update(void *opaque, ClockEvent event) 77 { 78 RccClockMuxState **backref = opaque; 79 RccClockMuxState *s = *backref; 80 /* 81 * The backref value is equal to: 82 * s->backref + (sizeof(RccClockMuxState *) * update_src). 83 * By subtracting we can get back the index of the updated clock. 84 */ 85 const uint32_t update_src = backref - s->backref; 86 /* Only update if the clock that was updated is the current source */ 87 if (update_src == s->src) { 88 clock_mux_update(s, false); 89 } 90 } 91 92 static void clock_mux_init(Object *obj) 93 { 94 RccClockMuxState *s = RCC_CLOCK_MUX(obj); 95 size_t i; 96 97 for (i = 0; i < RCC_NUM_CLOCK_MUX_SRC; i++) { 98 char *name = g_strdup_printf("srcs[%zu]", i); 99 s->backref[i] = s; 100 s->srcs[i] = qdev_init_clock_in(DEVICE(s), name, 101 clock_mux_src_update, 102 &s->backref[i], 103 ClockUpdate); 104 g_free(name); 105 } 106 107 s->out = qdev_init_clock_out(DEVICE(s), "out"); 108 } 109 110 static void clock_mux_reset_enter(Object *obj, ResetType type) 111 { 112 RccClockMuxState *s = RCC_CLOCK_MUX(obj); 113 set_clock_mux_init_info(s, s->id); 114 } 115 116 static void clock_mux_reset_hold(Object *obj) 117 { 118 RccClockMuxState *s = RCC_CLOCK_MUX(obj); 119 clock_mux_update(s, true); 120 } 121 122 static void clock_mux_reset_exit(Object *obj) 123 { 124 RccClockMuxState *s = RCC_CLOCK_MUX(obj); 125 clock_mux_update(s, false); 126 } 127 128 static const VMStateDescription clock_mux_vmstate = { 129 .name = TYPE_RCC_CLOCK_MUX, 130 .version_id = 1, 131 .minimum_version_id = 1, 132 .fields = (VMStateField[]) { 133 VMSTATE_UINT32(id, RccClockMuxState), 134 VMSTATE_ARRAY_CLOCK(srcs, RccClockMuxState, 135 RCC_NUM_CLOCK_MUX_SRC), 136 VMSTATE_BOOL(enabled, RccClockMuxState), 137 VMSTATE_UINT32(src, RccClockMuxState), 138 VMSTATE_UINT32(multiplier, RccClockMuxState), 139 VMSTATE_UINT32(divider, RccClockMuxState), 140 VMSTATE_END_OF_LIST() 141 } 142 }; 143 144 static void clock_mux_class_init(ObjectClass *klass, void *data) 145 { 146 DeviceClass *dc = DEVICE_CLASS(klass); 147 ResettableClass *rc = RESETTABLE_CLASS(klass); 148 149 rc->phases.enter = clock_mux_reset_enter; 150 rc->phases.hold = clock_mux_reset_hold; 151 rc->phases.exit = clock_mux_reset_exit; 152 dc->vmsd = &clock_mux_vmstate; 153 } 154 155 static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled) 156 { 157 if (mux->enabled == enabled) { 158 return; 159 } 160 161 if (enabled) { 162 trace_stm32l4x5_rcc_mux_enable(mux->id); 163 } else { 164 trace_stm32l4x5_rcc_mux_disable(mux->id); 165 } 166 167 mux->enabled = enabled; 168 clock_mux_update(mux, false); 169 } 170 171 static void clock_mux_set_factor(RccClockMuxState *mux, 172 uint32_t multiplier, uint32_t divider) 173 { 174 if (mux->multiplier == multiplier && mux->divider == divider) { 175 return; 176 } 177 trace_stm32l4x5_rcc_mux_set_factor(mux->id, 178 mux->multiplier, multiplier, mux->divider, divider); 179 180 mux->multiplier = multiplier; 181 mux->divider = divider; 182 clock_mux_update(mux, false); 183 } 184 185 static void clock_mux_set_source(RccClockMuxState *mux, RccClockMuxSource src) 186 { 187 if (mux->src == src) { 188 return; 189 } 190 191 trace_stm32l4x5_rcc_mux_set_src(mux->id, mux->src, src); 192 mux->src = src; 193 clock_mux_update(mux, false); 194 } 195 196 /* 197 * Acknowledge and propagate changes in a PLL frequency. 198 * `bypass_source` allows to bypass the period of the current source and just 199 * consider it equal to 0. This is useful during the hold phase of reset. 200 */ 201 static void pll_update(RccPllState *pll, bool bypass_source) 202 { 203 uint64_t vco_freq, old_channel_freq, channel_freq; 204 int i; 205 206 /* The common PLLM factor is handled by the PLL mux */ 207 vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1); 208 209 for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) { 210 if (!pll->channel_exists[i]) { 211 continue; 212 } 213 214 old_channel_freq = clock_get_hz(pll->channels[i]); 215 if (bypass_source || 216 !pll->enabled || 217 !pll->channel_enabled[i] || 218 !pll->channel_divider[i]) { 219 channel_freq = 0; 220 } else { 221 channel_freq = muldiv64(vco_freq, 222 1, 223 pll->channel_divider[i]); 224 } 225 226 /* No change, early continue to avoid log spam and useless propagation */ 227 if (old_channel_freq == channel_freq) { 228 continue; 229 } 230 231 clock_update_hz(pll->channels[i], channel_freq); 232 trace_stm32l4x5_rcc_pll_update(pll->id, i, vco_freq, 233 old_channel_freq, channel_freq); 234 } 235 } 236 237 static void pll_src_update(void *opaque, ClockEvent event) 238 { 239 RccPllState *s = opaque; 240 pll_update(s, false); 241 } 242 243 static void pll_init(Object *obj) 244 { 245 RccPllState *s = RCC_PLL(obj); 246 size_t i; 247 248 s->in = qdev_init_clock_in(DEVICE(s), "in", 249 pll_src_update, s, ClockUpdate); 250 251 const char *names[] = { 252 "out-p", "out-q", "out-r", 253 }; 254 255 for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) { 256 s->channels[i] = qdev_init_clock_out(DEVICE(s), names[i]); 257 } 258 } 259 260 static void pll_reset_enter(Object *obj, ResetType type) 261 { 262 RccPllState *s = RCC_PLL(obj); 263 set_pll_init_info(s, s->id); 264 } 265 266 static void pll_reset_hold(Object *obj) 267 { 268 RccPllState *s = RCC_PLL(obj); 269 pll_update(s, true); 270 } 271 272 static void pll_reset_exit(Object *obj) 273 { 274 RccPllState *s = RCC_PLL(obj); 275 pll_update(s, false); 276 } 277 278 static const VMStateDescription pll_vmstate = { 279 .name = TYPE_RCC_PLL, 280 .version_id = 1, 281 .minimum_version_id = 1, 282 .fields = (VMStateField[]) { 283 VMSTATE_UINT32(id, RccPllState), 284 VMSTATE_CLOCK(in, RccPllState), 285 VMSTATE_ARRAY_CLOCK(channels, RccPllState, 286 RCC_NUM_CHANNEL_PLL_OUT), 287 VMSTATE_BOOL(enabled, RccPllState), 288 VMSTATE_UINT32(vco_multiplier, RccPllState), 289 VMSTATE_BOOL_ARRAY(channel_enabled, RccPllState, RCC_NUM_CHANNEL_PLL_OUT), 290 VMSTATE_BOOL_ARRAY(channel_exists, RccPllState, RCC_NUM_CHANNEL_PLL_OUT), 291 VMSTATE_UINT32_ARRAY(channel_divider, RccPllState, RCC_NUM_CHANNEL_PLL_OUT), 292 VMSTATE_END_OF_LIST() 293 } 294 }; 295 296 static void pll_class_init(ObjectClass *klass, void *data) 297 { 298 DeviceClass *dc = DEVICE_CLASS(klass); 299 ResettableClass *rc = RESETTABLE_CLASS(klass); 300 301 rc->phases.enter = pll_reset_enter; 302 rc->phases.hold = pll_reset_hold; 303 rc->phases.exit = pll_reset_exit; 304 dc->vmsd = &pll_vmstate; 305 } 306 307 static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier) 308 { 309 if (pll->vco_multiplier == vco_multiplier) { 310 return; 311 } 312 313 if (vco_multiplier < 8 || vco_multiplier > 86) { 314 qemu_log_mask(LOG_GUEST_ERROR, 315 "%s: VCO multiplier is out of bound (%u) for PLL %u\n", 316 __func__, vco_multiplier, pll->id); 317 return; 318 } 319 320 trace_stm32l4x5_rcc_pll_set_vco_multiplier(pll->id, 321 pll->vco_multiplier, vco_multiplier); 322 323 pll->vco_multiplier = vco_multiplier; 324 pll_update(pll, false); 325 } 326 327 static void pll_set_enable(RccPllState *pll, bool enabled) 328 { 329 if (pll->enabled == enabled) { 330 return; 331 } 332 333 pll->enabled = enabled; 334 pll_update(pll, false); 335 } 336 337 static void pll_set_channel_enable(RccPllState *pll, 338 PllCommonChannels channel, 339 bool enabled) 340 { 341 if (pll->channel_enabled[channel] == enabled) { 342 return; 343 } 344 345 if (enabled) { 346 trace_stm32l4x5_rcc_pll_channel_enable(pll->id, channel); 347 } else { 348 trace_stm32l4x5_rcc_pll_channel_disable(pll->id, channel); 349 } 350 351 pll->channel_enabled[channel] = enabled; 352 pll_update(pll, false); 353 } 354 355 static void pll_set_channel_divider(RccPllState *pll, 356 PllCommonChannels channel, 357 uint32_t divider) 358 { 359 if (pll->channel_divider[channel] == divider) { 360 return; 361 } 362 363 trace_stm32l4x5_rcc_pll_set_channel_divider(pll->id, 364 channel, pll->channel_divider[channel], divider); 365 366 pll->channel_divider[channel] = divider; 367 pll_update(pll, false); 368 } 369 370 static void rcc_update_irq(Stm32l4x5RccState *s) 371 { 372 /* 373 * TODO: Handle LSECSSF and CSSF flags when the CSS is implemented. 374 */ 375 if (s->cifr & CIFR_IRQ_MASK) { 376 qemu_irq_raise(s->irq); 377 } else { 378 qemu_irq_lower(s->irq); 379 } 380 } 381 382 static void rcc_update_msi(Stm32l4x5RccState *s, uint32_t previous_value) 383 { 384 uint32_t val; 385 386 static const uint32_t msirange[] = { 387 100000, 200000, 400000, 800000, 1000000, 2000000, 388 4000000, 8000000, 16000000, 24000000, 32000000, 48000000 389 }; 390 /* MSIRANGE and MSIRGSEL */ 391 val = extract32(s->cr, R_CR_MSIRGSEL_SHIFT, R_CR_MSIRGSEL_LENGTH); 392 if (val) { 393 /* MSIRGSEL is set, use the MSIRANGE field */ 394 val = extract32(s->cr, R_CR_MSIRANGE_SHIFT, R_CR_MSIRANGE_LENGTH); 395 } else { 396 /* MSIRGSEL is not set, use the MSISRANGE field */ 397 val = extract32(s->csr, R_CSR_MSISRANGE_SHIFT, R_CSR_MSISRANGE_LENGTH); 398 } 399 400 if (val < ARRAY_SIZE(msirange)) { 401 clock_update_hz(s->msi_rc, msirange[val]); 402 } else { 403 /* 404 * There is a hardware write protection if the value is out of bound. 405 * Restore the previous value. 406 */ 407 s->cr = (s->cr & ~R_CSR_MSISRANGE_MASK) | 408 (previous_value & R_CSR_MSISRANGE_MASK); 409 } 410 } 411 412 /* 413 * TODO: Add write-protection for all registers: 414 * DONE: CR 415 */ 416 417 static void rcc_update_cr_register(Stm32l4x5RccState *s, uint32_t previous_value) 418 { 419 int val; 420 const RccClockMuxSource current_pll_src = 421 CLOCK_MUX_INIT_INFO[RCC_CLOCK_MUX_PLL_INPUT].src_mapping[ 422 s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].src]; 423 424 /* PLLSAI2ON and update PLLSAI2RDY */ 425 val = FIELD_EX32(s->cr, CR, PLLSAI2ON); 426 pll_set_enable(&s->plls[RCC_PLL_PLLSAI2], val); 427 s->cr = (s->cr & ~R_CR_PLLSAI2RDY_MASK) | 428 (val << R_CR_PLLSAI2RDY_SHIFT); 429 if (s->cier & R_CIER_PLLSAI2RDYIE_MASK) { 430 s->cifr |= R_CIFR_PLLSAI2RDYF_MASK; 431 } 432 433 /* PLLSAI1ON and update PLLSAI1RDY */ 434 val = FIELD_EX32(s->cr, CR, PLLSAI1ON); 435 pll_set_enable(&s->plls[RCC_PLL_PLLSAI1], val); 436 s->cr = (s->cr & ~R_CR_PLLSAI1RDY_MASK) | 437 (val << R_CR_PLLSAI1RDY_SHIFT); 438 if (s->cier & R_CIER_PLLSAI1RDYIE_MASK) { 439 s->cifr |= R_CIFR_PLLSAI1RDYF_MASK; 440 } 441 442 /* 443 * PLLON and update PLLRDY 444 * PLLON cannot be reset if the PLL clock is used as the system clock. 445 */ 446 val = FIELD_EX32(s->cr, CR, PLLON); 447 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b11) { 448 pll_set_enable(&s->plls[RCC_PLL_PLL], val); 449 s->cr = (s->cr & ~R_CR_PLLRDY_MASK) | 450 (val << R_CR_PLLRDY_SHIFT); 451 if (s->cier & R_CIER_PLLRDYIE_MASK) { 452 s->cifr |= R_CIFR_PLLRDYF_MASK; 453 } 454 } else { 455 s->cr |= R_CR_PLLON_MASK; 456 } 457 458 /* CSSON: TODO */ 459 /* HSEBYP: TODO */ 460 461 /* 462 * HSEON and update HSERDY. 463 * HSEON cannot be reset if the HSE oscillator is used directly or 464 * indirectly as the system clock. 465 */ 466 val = FIELD_EX32(s->cr, CR, HSEON); 467 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b10 && 468 current_pll_src != RCC_CLOCK_MUX_SRC_HSE) { 469 s->cr = (s->cr & ~R_CR_HSERDY_MASK) | 470 (val << R_CR_HSERDY_SHIFT); 471 if (val) { 472 clock_update_hz(s->hse, s->hse_frequency); 473 if (s->cier & R_CIER_HSERDYIE_MASK) { 474 s->cifr |= R_CIFR_HSERDYF_MASK; 475 } 476 } else { 477 clock_update(s->hse, 0); 478 } 479 } else { 480 s->cr |= R_CR_HSEON_MASK; 481 } 482 483 /* HSIAFS: TODO*/ 484 /* HSIKERON: TODO*/ 485 486 /* 487 * HSION and update HSIRDY 488 * HSION is set by hardware if the HSI16 is used directly 489 * or indirectly as system clock. 490 */ 491 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b01 || 492 current_pll_src == RCC_CLOCK_MUX_SRC_HSI) { 493 s->cr |= (R_CR_HSION_MASK | R_CR_HSIRDY_MASK); 494 clock_update_hz(s->hsi16_rc, HSI_FRQ); 495 if (s->cier & R_CIER_HSIRDYIE_MASK) { 496 s->cifr |= R_CIFR_HSIRDYF_MASK; 497 } 498 } else { 499 val = FIELD_EX32(s->cr, CR, HSION); 500 if (val) { 501 clock_update_hz(s->hsi16_rc, HSI_FRQ); 502 s->cr |= R_CR_HSIRDY_MASK; 503 if (s->cier & R_CIER_HSIRDYIE_MASK) { 504 s->cifr |= R_CIFR_HSIRDYF_MASK; 505 } 506 } else { 507 clock_update(s->hsi16_rc, 0); 508 s->cr &= ~R_CR_HSIRDY_MASK; 509 } 510 } 511 512 /* MSIPLLEN: TODO */ 513 514 /* 515 * MSION and update MSIRDY 516 * Set by hardware when used directly or indirectly as system clock. 517 */ 518 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b00 || 519 current_pll_src == RCC_CLOCK_MUX_SRC_MSI) { 520 s->cr |= (R_CR_MSION_MASK | R_CR_MSIRDY_MASK); 521 if (!(previous_value & R_CR_MSION_MASK) && (s->cier & R_CIER_MSIRDYIE_MASK)) { 522 s->cifr |= R_CIFR_MSIRDYF_MASK; 523 } 524 rcc_update_msi(s, previous_value); 525 } else { 526 val = FIELD_EX32(s->cr, CR, MSION); 527 if (val) { 528 s->cr |= R_CR_MSIRDY_MASK; 529 rcc_update_msi(s, previous_value); 530 if (s->cier & R_CIER_MSIRDYIE_MASK) { 531 s->cifr |= R_CIFR_MSIRDYF_MASK; 532 } 533 } else { 534 s->cr &= ~R_CR_MSIRDY_MASK; 535 clock_update(s->msi_rc, 0); 536 } 537 } 538 rcc_update_irq(s); 539 } 540 541 static void rcc_update_cfgr_register(Stm32l4x5RccState *s) 542 { 543 uint32_t val; 544 /* MCOPRE */ 545 val = FIELD_EX32(s->cfgr, CFGR, MCOPRE); 546 assert(val <= 0b100); 547 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO], 548 1, 1 << val); 549 550 /* MCOSEL */ 551 val = FIELD_EX32(s->cfgr, CFGR, MCOSEL); 552 assert(val <= 0b111); 553 if (val == 0) { 554 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); 555 } else { 556 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true); 557 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO], 558 val - 1); 559 } 560 561 /* STOPWUCK */ 562 /* TODO */ 563 564 /* PPRE2 */ 565 val = FIELD_EX32(s->cfgr, CFGR, PPRE2); 566 if (val < 0b100) { 567 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2], 568 1, 1); 569 } else { 570 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2], 571 1, 1 << (val - 0b11)); 572 } 573 574 /* PPRE1 */ 575 val = FIELD_EX32(s->cfgr, CFGR, PPRE1); 576 if (val < 0b100) { 577 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1], 578 1, 1); 579 } else { 580 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1], 581 1, 1 << (val - 0b11)); 582 } 583 584 /* HPRE */ 585 val = FIELD_EX32(s->cfgr, CFGR, HPRE); 586 if (val < 0b1000) { 587 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK], 588 1, 1); 589 } else { 590 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK], 591 1, 1 << (val - 0b111)); 592 } 593 594 /* Update SWS */ 595 val = FIELD_EX32(s->cfgr, CFGR, SW); 596 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_SYSCLK], 597 val); 598 s->cfgr &= ~R_CFGR_SWS_MASK; 599 s->cfgr |= val << R_CFGR_SWS_SHIFT; 600 } 601 602 static void rcc_update_ahb1enr(Stm32l4x5RccState *s) 603 { 604 #define AHB1ENR_SET_ENABLE(_peripheral_name) \ 605 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ 606 FIELD_EX32(s->ahb1enr, AHB1ENR, _peripheral_name##EN)) 607 608 /* DMA2DEN: reserved for STM32L475xx */ 609 AHB1ENR_SET_ENABLE(TSC); 610 AHB1ENR_SET_ENABLE(CRC); 611 AHB1ENR_SET_ENABLE(FLASH); 612 AHB1ENR_SET_ENABLE(DMA2); 613 AHB1ENR_SET_ENABLE(DMA1); 614 615 #undef AHB1ENR_SET_ENABLE 616 } 617 618 static void rcc_update_ahb2enr(Stm32l4x5RccState *s) 619 { 620 #define AHB2ENR_SET_ENABLE(_peripheral_name) \ 621 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ 622 FIELD_EX32(s->ahb2enr, AHB2ENR, _peripheral_name##EN)) 623 624 AHB2ENR_SET_ENABLE(RNG); 625 /* HASHEN: reserved for STM32L475xx */ 626 AHB2ENR_SET_ENABLE(AES); 627 /* DCMIEN: reserved for STM32L475xx */ 628 AHB2ENR_SET_ENABLE(ADC); 629 AHB2ENR_SET_ENABLE(OTGFS); 630 /* GPIOIEN: reserved for STM32L475xx */ 631 AHB2ENR_SET_ENABLE(GPIOA); 632 AHB2ENR_SET_ENABLE(GPIOB); 633 AHB2ENR_SET_ENABLE(GPIOC); 634 AHB2ENR_SET_ENABLE(GPIOD); 635 AHB2ENR_SET_ENABLE(GPIOE); 636 AHB2ENR_SET_ENABLE(GPIOF); 637 AHB2ENR_SET_ENABLE(GPIOG); 638 AHB2ENR_SET_ENABLE(GPIOH); 639 640 #undef AHB2ENR_SET_ENABLE 641 } 642 643 static void rcc_update_ahb3enr(Stm32l4x5RccState *s) 644 { 645 #define AHB3ENR_SET_ENABLE(_peripheral_name) \ 646 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ 647 FIELD_EX32(s->ahb3enr, AHB3ENR, _peripheral_name##EN)) 648 649 AHB3ENR_SET_ENABLE(QSPI); 650 AHB3ENR_SET_ENABLE(FMC); 651 652 #undef AHB3ENR_SET_ENABLE 653 } 654 655 static void rcc_update_apb1enr(Stm32l4x5RccState *s) 656 { 657 #define APB1ENR1_SET_ENABLE(_peripheral_name) \ 658 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ 659 FIELD_EX32(s->apb1enr1, APB1ENR1, _peripheral_name##EN)) 660 #define APB1ENR2_SET_ENABLE(_peripheral_name) \ 661 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ 662 FIELD_EX32(s->apb1enr2, APB1ENR2, _peripheral_name##EN)) 663 664 /* APB1ENR1 */ 665 APB1ENR1_SET_ENABLE(LPTIM1); 666 APB1ENR1_SET_ENABLE(OPAMP); 667 APB1ENR1_SET_ENABLE(DAC1); 668 APB1ENR1_SET_ENABLE(PWR); 669 /* CAN2: reserved for STM32L4x5 */ 670 APB1ENR1_SET_ENABLE(CAN1); 671 /* CRSEN: reserved for STM32L4x5 */ 672 APB1ENR1_SET_ENABLE(I2C3); 673 APB1ENR1_SET_ENABLE(I2C2); 674 APB1ENR1_SET_ENABLE(I2C1); 675 APB1ENR1_SET_ENABLE(UART5); 676 APB1ENR1_SET_ENABLE(UART4); 677 APB1ENR1_SET_ENABLE(USART3); 678 APB1ENR1_SET_ENABLE(USART2); 679 APB1ENR1_SET_ENABLE(SPI3); 680 APB1ENR1_SET_ENABLE(SPI2); 681 APB1ENR1_SET_ENABLE(WWDG); 682 /* RTCAPB: reserved for STM32L4x5 */ 683 APB1ENR1_SET_ENABLE(LCD); 684 APB1ENR1_SET_ENABLE(TIM7); 685 APB1ENR1_SET_ENABLE(TIM6); 686 APB1ENR1_SET_ENABLE(TIM5); 687 APB1ENR1_SET_ENABLE(TIM4); 688 APB1ENR1_SET_ENABLE(TIM3); 689 APB1ENR1_SET_ENABLE(TIM2); 690 691 /* APB1ENR2 */ 692 APB1ENR2_SET_ENABLE(LPTIM2); 693 APB1ENR2_SET_ENABLE(SWPMI1); 694 /* I2C4EN: reserved for STM32L4x5 */ 695 APB1ENR2_SET_ENABLE(LPUART1); 696 697 #undef APB1ENR1_SET_ENABLE 698 #undef APB1ENR2_SET_ENABLE 699 } 700 701 static void rcc_update_apb2enr(Stm32l4x5RccState *s) 702 { 703 #define APB2ENR_SET_ENABLE(_peripheral_name) \ 704 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ 705 FIELD_EX32(s->apb2enr, APB2ENR, _peripheral_name##EN)) 706 707 APB2ENR_SET_ENABLE(DFSDM1); 708 APB2ENR_SET_ENABLE(SAI2); 709 APB2ENR_SET_ENABLE(SAI1); 710 APB2ENR_SET_ENABLE(TIM17); 711 APB2ENR_SET_ENABLE(TIM16); 712 APB2ENR_SET_ENABLE(TIM15); 713 APB2ENR_SET_ENABLE(USART1); 714 APB2ENR_SET_ENABLE(TIM8); 715 APB2ENR_SET_ENABLE(SPI1); 716 APB2ENR_SET_ENABLE(TIM1); 717 APB2ENR_SET_ENABLE(SDMMC1); 718 APB2ENR_SET_ENABLE(FW); 719 APB2ENR_SET_ENABLE(SYSCFG); 720 721 #undef APB2ENR_SET_ENABLE 722 } 723 724 /* 725 * The 3 PLLs share the same register layout 726 * so we can use the same function for all of them 727 * Note: no frequency bounds checking is done here. 728 */ 729 static void rcc_update_pllsaixcfgr(Stm32l4x5RccState *s, RccPll pll_id) 730 { 731 uint32_t reg, val; 732 switch (pll_id) { 733 case RCC_PLL_PLL: 734 reg = s->pllcfgr; 735 break; 736 case RCC_PLL_PLLSAI1: 737 reg = s->pllsai1cfgr; 738 break; 739 case RCC_PLL_PLLSAI2: 740 reg = s->pllsai2cfgr; 741 break; 742 default: 743 qemu_log_mask(LOG_GUEST_ERROR, 744 "%s: Invalid PLL ID: %u\n", __func__, pll_id); 745 return; 746 } 747 748 /* PLLPDIV */ 749 val = FIELD_EX32(reg, PLLCFGR, PLLPDIV); 750 /* 1 is a reserved value */ 751 if (val == 0) { 752 /* Get PLLP value */ 753 val = FIELD_EX32(reg, PLLCFGR, PLLP); 754 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, 755 (val ? 17 : 7)); 756 } else if (val > 1) { 757 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, 758 val); 759 } 760 761 762 /* PLLR */ 763 val = FIELD_EX32(reg, PLLCFGR, PLLR); 764 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, 765 2 * (val + 1)); 766 767 /* PLLREN */ 768 val = FIELD_EX32(reg, PLLCFGR, PLLREN); 769 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, val); 770 771 /* PLLQ */ 772 val = FIELD_EX32(reg, PLLCFGR, PLLQ); 773 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, 774 2 * (val + 1)); 775 776 /* PLLQEN */ 777 val = FIELD_EX32(reg, PLLCFGR, PLLQEN); 778 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, val); 779 780 /* PLLPEN */ 781 val = FIELD_EX32(reg, PLLCFGR, PLLPEN); 782 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, val); 783 784 /* PLLN */ 785 val = FIELD_EX32(reg, PLLCFGR, PLLN); 786 pll_set_vco_multiplier(&s->plls[pll_id], val); 787 } 788 789 static void rcc_update_pllcfgr(Stm32l4x5RccState *s) 790 { 791 int val; 792 793 /* Use common layout */ 794 rcc_update_pllsaixcfgr(s, RCC_PLL_PLL); 795 796 /* Fetch specific fields for pllcfgr */ 797 798 /* PLLM */ 799 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLM); 800 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], 1, (val + 1)); 801 802 /* PLLSRC */ 803 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLSRC); 804 if (val == 0) { 805 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], false); 806 } else { 807 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], val - 1); 808 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], true); 809 } 810 } 811 812 static void rcc_update_ccipr(Stm32l4x5RccState *s) 813 { 814 #define CCIPR_SET_SOURCE(_peripheral_name) \ 815 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ 816 FIELD_EX32(s->ccipr, CCIPR, _peripheral_name##SEL)) 817 818 CCIPR_SET_SOURCE(DFSDM1); 819 CCIPR_SET_SOURCE(SWPMI1); 820 CCIPR_SET_SOURCE(ADC); 821 CCIPR_SET_SOURCE(CLK48); 822 CCIPR_SET_SOURCE(SAI2); 823 CCIPR_SET_SOURCE(SAI1); 824 CCIPR_SET_SOURCE(LPTIM2); 825 CCIPR_SET_SOURCE(LPTIM1); 826 CCIPR_SET_SOURCE(I2C3); 827 CCIPR_SET_SOURCE(I2C2); 828 CCIPR_SET_SOURCE(I2C1); 829 CCIPR_SET_SOURCE(LPUART1); 830 CCIPR_SET_SOURCE(UART5); 831 CCIPR_SET_SOURCE(UART4); 832 CCIPR_SET_SOURCE(USART3); 833 CCIPR_SET_SOURCE(USART2); 834 CCIPR_SET_SOURCE(USART1); 835 836 #undef CCIPR_SET_SOURCE 837 } 838 839 static void rcc_update_bdcr(Stm32l4x5RccState *s) 840 { 841 int val; 842 843 /* LSCOSEL */ 844 val = FIELD_EX32(s->bdcr, BDCR, LSCOSEL); 845 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val); 846 847 val = FIELD_EX32(s->bdcr, BDCR, LSCOEN); 848 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val); 849 850 /* BDRST */ 851 /* 852 * The documentation is not clear if the RTCEN flag disables the RTC and 853 * the LCD common mux or if it only affects the RTC. 854 * As the LCDEN flag exists, we assume here that it only affects the RTC. 855 */ 856 val = FIELD_EX32(s->bdcr, BDCR, RTCEN); 857 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_RTC], val); 858 /* LCD and RTC share the same clock */ 859 val = FIELD_EX32(s->bdcr, BDCR, RTCSEL); 860 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON], val); 861 862 /* LSECSSON */ 863 /* LSEDRV[1:0] */ 864 /* LSEBYP */ 865 866 /* LSEON: Update LSERDY at the same time */ 867 val = FIELD_EX32(s->bdcr, BDCR, LSEON); 868 if (val) { 869 clock_update_hz(s->lse_crystal, LSE_FRQ); 870 s->bdcr |= R_BDCR_LSERDY_MASK; 871 if (s->cier & R_CIER_LSERDYIE_MASK) { 872 s->cifr |= R_CIFR_LSERDYF_MASK; 873 } 874 } else { 875 clock_update(s->lse_crystal, 0); 876 s->bdcr &= ~R_BDCR_LSERDY_MASK; 877 } 878 879 rcc_update_irq(s); 880 } 881 882 static void rcc_update_csr(Stm32l4x5RccState *s) 883 { 884 int val; 885 886 /* Reset flags: Not implemented */ 887 /* MSISRANGE: Not implemented after reset */ 888 889 /* LSION: Update LSIRDY at the same time */ 890 val = FIELD_EX32(s->csr, CSR, LSION); 891 if (val) { 892 clock_update_hz(s->lsi_rc, LSI_FRQ); 893 s->csr |= R_CSR_LSIRDY_MASK; 894 if (s->cier & R_CIER_LSIRDYIE_MASK) { 895 s->cifr |= R_CIFR_LSIRDYF_MASK; 896 } 897 } else { 898 /* 899 * TODO: Handle when the LSI is set independently of LSION. 900 * E.g. when the LSI is set by the RTC. 901 * See the reference manual for more details. 902 */ 903 clock_update(s->lsi_rc, 0); 904 s->csr &= ~R_CSR_LSIRDY_MASK; 905 } 906 907 rcc_update_irq(s); 908 } 909 910 static void stm32l4x5_rcc_reset_hold(Object *obj) 911 { 912 Stm32l4x5RccState *s = STM32L4X5_RCC(obj); 913 s->cr = 0x00000063; 914 /* 915 * Factory-programmed calibration data 916 * From the reference manual: 0x10XX 00XX 917 * Value taken from a real card. 918 */ 919 s->icscr = 0x106E0082; 920 s->cfgr = 0x0; 921 s->pllcfgr = 0x00001000; 922 s->pllsai1cfgr = 0x00001000; 923 s->pllsai2cfgr = 0x00001000; 924 s->cier = 0x0; 925 s->cifr = 0x0; 926 s->ahb1rstr = 0x0; 927 s->ahb2rstr = 0x0; 928 s->ahb3rstr = 0x0; 929 s->apb1rstr1 = 0x0; 930 s->apb1rstr2 = 0x0; 931 s->apb2rstr = 0x0; 932 s->ahb1enr = 0x00000100; 933 s->ahb2enr = 0x0; 934 s->ahb3enr = 0x0; 935 s->apb1enr1 = 0x0; 936 s->apb1enr2 = 0x0; 937 s->apb2enr = 0x0; 938 s->ahb1smenr = 0x00011303; 939 s->ahb2smenr = 0x000532FF; 940 s->ahb3smenr = 0x00000101; 941 s->apb1smenr1 = 0xF2FECA3F; 942 s->apb1smenr2 = 0x00000025; 943 s->apb2smenr = 0x01677C01; 944 s->ccipr = 0x0; 945 s->bdcr = 0x0; 946 s->csr = 0x0C000600; 947 } 948 949 static uint64_t stm32l4x5_rcc_read(void *opaque, hwaddr addr, 950 unsigned int size) 951 { 952 Stm32l4x5RccState *s = opaque; 953 uint64_t retvalue = 0; 954 955 switch (addr) { 956 case A_CR: 957 retvalue = s->cr; 958 break; 959 case A_ICSCR: 960 retvalue = s->icscr; 961 break; 962 case A_CFGR: 963 retvalue = s->cfgr; 964 break; 965 case A_PLLCFGR: 966 retvalue = s->pllcfgr; 967 break; 968 case A_PLLSAI1CFGR: 969 retvalue = s->pllsai1cfgr; 970 break; 971 case A_PLLSAI2CFGR: 972 retvalue = s->pllsai2cfgr; 973 break; 974 case A_CIER: 975 retvalue = s->cier; 976 break; 977 case A_CIFR: 978 retvalue = s->cifr; 979 break; 980 case A_CICR: 981 /* CICR is write only, return the reset value = 0 */ 982 break; 983 case A_AHB1RSTR: 984 retvalue = s->ahb1rstr; 985 break; 986 case A_AHB2RSTR: 987 retvalue = s->ahb2rstr; 988 break; 989 case A_AHB3RSTR: 990 retvalue = s->ahb3rstr; 991 break; 992 case A_APB1RSTR1: 993 retvalue = s->apb1rstr1; 994 break; 995 case A_APB1RSTR2: 996 retvalue = s->apb1rstr2; 997 break; 998 case A_APB2RSTR: 999 retvalue = s->apb2rstr; 1000 break; 1001 case A_AHB1ENR: 1002 retvalue = s->ahb1enr; 1003 break; 1004 case A_AHB2ENR: 1005 retvalue = s->ahb2enr; 1006 break; 1007 case A_AHB3ENR: 1008 retvalue = s->ahb3enr; 1009 break; 1010 case A_APB1ENR1: 1011 retvalue = s->apb1enr1; 1012 break; 1013 case A_APB1ENR2: 1014 retvalue = s->apb1enr2; 1015 break; 1016 case A_APB2ENR: 1017 retvalue = s->apb2enr; 1018 break; 1019 case A_AHB1SMENR: 1020 retvalue = s->ahb1smenr; 1021 break; 1022 case A_AHB2SMENR: 1023 retvalue = s->ahb2smenr; 1024 break; 1025 case A_AHB3SMENR: 1026 retvalue = s->ahb3smenr; 1027 break; 1028 case A_APB1SMENR1: 1029 retvalue = s->apb1smenr1; 1030 break; 1031 case A_APB1SMENR2: 1032 retvalue = s->apb1smenr2; 1033 break; 1034 case A_APB2SMENR: 1035 retvalue = s->apb2smenr; 1036 break; 1037 case A_CCIPR: 1038 retvalue = s->ccipr; 1039 break; 1040 case A_BDCR: 1041 retvalue = s->bdcr; 1042 break; 1043 case A_CSR: 1044 retvalue = s->csr; 1045 break; 1046 default: 1047 qemu_log_mask(LOG_GUEST_ERROR, 1048 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 1049 break; 1050 } 1051 1052 trace_stm32l4x5_rcc_read(addr, retvalue); 1053 1054 return retvalue; 1055 } 1056 1057 static void stm32l4x5_rcc_write(void *opaque, hwaddr addr, 1058 uint64_t val64, unsigned int size) 1059 { 1060 Stm32l4x5RccState *s = opaque; 1061 uint32_t previous_value = 0; 1062 const uint32_t value = val64; 1063 1064 trace_stm32l4x5_rcc_write(addr, value); 1065 1066 switch (addr) { 1067 case A_CR: 1068 previous_value = s->cr; 1069 s->cr = (s->cr & CR_READ_SET_MASK) | 1070 (value & (CR_READ_SET_MASK | ~CR_READ_ONLY_MASK)); 1071 rcc_update_cr_register(s, previous_value); 1072 break; 1073 case A_ICSCR: 1074 s->icscr = value & ~ICSCR_READ_ONLY_MASK; 1075 qemu_log_mask(LOG_UNIMP, 1076 "%s: Side-effects not implemented for ICSCR\n", __func__); 1077 break; 1078 case A_CFGR: 1079 s->cfgr = value & ~CFGR_READ_ONLY_MASK; 1080 rcc_update_cfgr_register(s); 1081 break; 1082 case A_PLLCFGR: 1083 s->pllcfgr = value; 1084 rcc_update_pllcfgr(s); 1085 break; 1086 case A_PLLSAI1CFGR: 1087 s->pllsai1cfgr = value; 1088 rcc_update_pllsaixcfgr(s, RCC_PLL_PLLSAI1); 1089 break; 1090 case A_PLLSAI2CFGR: 1091 s->pllsai2cfgr = value; 1092 rcc_update_pllsaixcfgr(s, RCC_PLL_PLLSAI2); 1093 break; 1094 case A_CIER: 1095 s->cier = value; 1096 qemu_log_mask(LOG_UNIMP, 1097 "%s: Side-effects not implemented for CIER\n", __func__); 1098 break; 1099 case A_CIFR: 1100 qemu_log_mask(LOG_GUEST_ERROR, 1101 "%s: Write attempt into read-only register (CIFR) 0x%"PRIx32"\n", 1102 __func__, value); 1103 break; 1104 case A_CICR: 1105 /* Clear interrupt flags by writing a 1 to the CICR register */ 1106 s->cifr &= ~value; 1107 rcc_update_irq(s); 1108 break; 1109 /* Reset behaviors are not implemented */ 1110 case A_AHB1RSTR: 1111 s->ahb1rstr = value; 1112 qemu_log_mask(LOG_UNIMP, 1113 "%s: Side-effects not implemented for AHB1RSTR\n", __func__); 1114 break; 1115 case A_AHB2RSTR: 1116 s->ahb2rstr = value; 1117 qemu_log_mask(LOG_UNIMP, 1118 "%s: Side-effects not implemented for AHB2RSTR\n", __func__); 1119 break; 1120 case A_AHB3RSTR: 1121 s->ahb3rstr = value; 1122 qemu_log_mask(LOG_UNIMP, 1123 "%s: Side-effects not implemented for AHB3RSTR\n", __func__); 1124 break; 1125 case A_APB1RSTR1: 1126 s->apb1rstr1 = value; 1127 qemu_log_mask(LOG_UNIMP, 1128 "%s: Side-effects not implemented for APB1RSTR1\n", __func__); 1129 break; 1130 case A_APB1RSTR2: 1131 s->apb1rstr2 = value; 1132 qemu_log_mask(LOG_UNIMP, 1133 "%s: Side-effects not implemented for APB1RSTR2\n", __func__); 1134 break; 1135 case A_APB2RSTR: 1136 s->apb2rstr = value; 1137 qemu_log_mask(LOG_UNIMP, 1138 "%s: Side-effects not implemented for APB2RSTR\n", __func__); 1139 break; 1140 case A_AHB1ENR: 1141 s->ahb1enr = value; 1142 rcc_update_ahb1enr(s); 1143 break; 1144 case A_AHB2ENR: 1145 s->ahb2enr = value; 1146 rcc_update_ahb2enr(s); 1147 break; 1148 case A_AHB3ENR: 1149 s->ahb3enr = value; 1150 rcc_update_ahb3enr(s); 1151 break; 1152 case A_APB1ENR1: 1153 s->apb1enr1 = value; 1154 rcc_update_apb1enr(s); 1155 break; 1156 case A_APB1ENR2: 1157 s->apb1enr2 = value; 1158 rcc_update_apb1enr(s); 1159 break; 1160 case A_APB2ENR: 1161 s->apb2enr = (s->apb2enr & APB2ENR_READ_SET_MASK) | value; 1162 rcc_update_apb2enr(s); 1163 break; 1164 /* Behaviors for Sleep and Stop modes are not implemented */ 1165 case A_AHB1SMENR: 1166 s->ahb1smenr = value; 1167 qemu_log_mask(LOG_UNIMP, 1168 "%s: Side-effects not implemented for AHB1SMENR\n", __func__); 1169 break; 1170 case A_AHB2SMENR: 1171 s->ahb2smenr = value; 1172 qemu_log_mask(LOG_UNIMP, 1173 "%s: Side-effects not implemented for AHB2SMENR\n", __func__); 1174 break; 1175 case A_AHB3SMENR: 1176 s->ahb3smenr = value; 1177 qemu_log_mask(LOG_UNIMP, 1178 "%s: Side-effects not implemented for AHB3SMENR\n", __func__); 1179 break; 1180 case A_APB1SMENR1: 1181 s->apb1smenr1 = value; 1182 qemu_log_mask(LOG_UNIMP, 1183 "%s: Side-effects not implemented for APB1SMENR1\n", __func__); 1184 break; 1185 case A_APB1SMENR2: 1186 s->apb1smenr2 = value; 1187 qemu_log_mask(LOG_UNIMP, 1188 "%s: Side-effects not implemented for APB1SMENR2\n", __func__); 1189 break; 1190 case A_APB2SMENR: 1191 s->apb2smenr = value; 1192 qemu_log_mask(LOG_UNIMP, 1193 "%s: Side-effects not implemented for APB2SMENR\n", __func__); 1194 break; 1195 case A_CCIPR: 1196 s->ccipr = value; 1197 rcc_update_ccipr(s); 1198 break; 1199 case A_BDCR: 1200 s->bdcr = value & ~BDCR_READ_ONLY_MASK; 1201 rcc_update_bdcr(s); 1202 break; 1203 case A_CSR: 1204 s->csr = value & ~CSR_READ_ONLY_MASK; 1205 rcc_update_csr(s); 1206 break; 1207 default: 1208 qemu_log_mask(LOG_GUEST_ERROR, 1209 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 1210 } 1211 } 1212 1213 static const MemoryRegionOps stm32l4x5_rcc_ops = { 1214 .read = stm32l4x5_rcc_read, 1215 .write = stm32l4x5_rcc_write, 1216 .endianness = DEVICE_NATIVE_ENDIAN, 1217 .valid = { 1218 .max_access_size = 4, 1219 .min_access_size = 4, 1220 .unaligned = false 1221 }, 1222 .impl = { 1223 .max_access_size = 4, 1224 .min_access_size = 4, 1225 .unaligned = false 1226 }, 1227 }; 1228 1229 static const ClockPortInitArray stm32l4x5_rcc_clocks = { 1230 QDEV_CLOCK_IN(Stm32l4x5RccState, hsi16_rc, NULL, 0), 1231 QDEV_CLOCK_IN(Stm32l4x5RccState, msi_rc, NULL, 0), 1232 QDEV_CLOCK_IN(Stm32l4x5RccState, hse, NULL, 0), 1233 QDEV_CLOCK_IN(Stm32l4x5RccState, lsi_rc, NULL, 0), 1234 QDEV_CLOCK_IN(Stm32l4x5RccState, lse_crystal, NULL, 0), 1235 QDEV_CLOCK_IN(Stm32l4x5RccState, sai1_extclk, NULL, 0), 1236 QDEV_CLOCK_IN(Stm32l4x5RccState, sai2_extclk, NULL, 0), 1237 QDEV_CLOCK_END 1238 }; 1239 1240 1241 static void stm32l4x5_rcc_init(Object *obj) 1242 { 1243 Stm32l4x5RccState *s = STM32L4X5_RCC(obj); 1244 size_t i; 1245 1246 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 1247 1248 memory_region_init_io(&s->mmio, obj, &stm32l4x5_rcc_ops, s, 1249 TYPE_STM32L4X5_RCC, 0x400); 1250 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 1251 1252 qdev_init_clocks(DEVICE(s), stm32l4x5_rcc_clocks); 1253 1254 for (i = 0; i < RCC_NUM_PLL; i++) { 1255 object_initialize_child(obj, PLL_INIT_INFO[i].name, 1256 &s->plls[i], TYPE_RCC_PLL); 1257 set_pll_init_info(&s->plls[i], i); 1258 } 1259 1260 for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) { 1261 char *alias; 1262 1263 object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name, 1264 &s->clock_muxes[i], 1265 TYPE_RCC_CLOCK_MUX); 1266 set_clock_mux_init_info(&s->clock_muxes[i], i); 1267 1268 if (!CLOCK_MUX_INIT_INFO[i].hidden) { 1269 /* Expose muxes output as RCC outputs */ 1270 alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name); 1271 qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias); 1272 g_free(alias); 1273 } 1274 } 1275 1276 s->gnd = clock_new(obj, "gnd"); 1277 } 1278 1279 static void connect_mux_sources(Stm32l4x5RccState *s, 1280 RccClockMuxState *mux, 1281 const RccClockMuxSource *clk_mapping) 1282 { 1283 size_t i; 1284 1285 Clock * const CLK_SRC_MAPPING[] = { 1286 [RCC_CLOCK_MUX_SRC_GND] = s->gnd, 1287 [RCC_CLOCK_MUX_SRC_HSI] = s->hsi16_rc, 1288 [RCC_CLOCK_MUX_SRC_HSE] = s->hse, 1289 [RCC_CLOCK_MUX_SRC_MSI] = s->msi_rc, 1290 [RCC_CLOCK_MUX_SRC_LSI] = s->lsi_rc, 1291 [RCC_CLOCK_MUX_SRC_LSE] = s->lse_crystal, 1292 [RCC_CLOCK_MUX_SRC_SAI1_EXTCLK] = s->sai1_extclk, 1293 [RCC_CLOCK_MUX_SRC_SAI2_EXTCLK] = s->sai2_extclk, 1294 [RCC_CLOCK_MUX_SRC_PLL] = 1295 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLCLK], 1296 [RCC_CLOCK_MUX_SRC_PLLSAI1] = 1297 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLSAI1CLK], 1298 [RCC_CLOCK_MUX_SRC_PLLSAI2] = 1299 s->plls[RCC_PLL_PLLSAI2].channels[RCC_PLLSAI2_CHANNEL_PLLSAI2CLK], 1300 [RCC_CLOCK_MUX_SRC_PLLSAI3] = 1301 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLSAI3CLK], 1302 [RCC_CLOCK_MUX_SRC_PLL48M1] = 1303 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLL48M1CLK], 1304 [RCC_CLOCK_MUX_SRC_PLL48M2] = 1305 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLL48M2CLK], 1306 [RCC_CLOCK_MUX_SRC_PLLADC1] = 1307 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLADC1CLK], 1308 [RCC_CLOCK_MUX_SRC_PLLADC2] = 1309 s->plls[RCC_PLL_PLLSAI2] .channels[RCC_PLLSAI2_CHANNEL_PLLADC2CLK], 1310 [RCC_CLOCK_MUX_SRC_SYSCLK] = s->clock_muxes[RCC_CLOCK_MUX_SYSCLK].out, 1311 [RCC_CLOCK_MUX_SRC_HCLK] = s->clock_muxes[RCC_CLOCK_MUX_HCLK].out, 1312 [RCC_CLOCK_MUX_SRC_PCLK1] = s->clock_muxes[RCC_CLOCK_MUX_PCLK1].out, 1313 [RCC_CLOCK_MUX_SRC_PCLK2] = s->clock_muxes[RCC_CLOCK_MUX_PCLK2].out, 1314 [RCC_CLOCK_MUX_SRC_HSE_OVER_32] = s->clock_muxes[RCC_CLOCK_MUX_HSE_OVER_32].out, 1315 [RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON] = 1316 s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON].out, 1317 }; 1318 1319 assert(ARRAY_SIZE(CLK_SRC_MAPPING) == RCC_CLOCK_MUX_SRC_NUMBER); 1320 1321 for (i = 0; i < RCC_NUM_CLOCK_MUX_SRC; i++) { 1322 RccClockMuxSource mapping = clk_mapping[i]; 1323 clock_set_source(mux->srcs[i], CLK_SRC_MAPPING[mapping]); 1324 } 1325 } 1326 1327 1328 static const VMStateDescription vmstate_stm32l4x5_rcc = { 1329 .name = TYPE_STM32L4X5_RCC, 1330 .version_id = 1, 1331 .minimum_version_id = 1, 1332 .fields = (VMStateField[]) { 1333 VMSTATE_UINT32(cr, Stm32l4x5RccState), 1334 VMSTATE_UINT32(icscr, Stm32l4x5RccState), 1335 VMSTATE_UINT32(cfgr, Stm32l4x5RccState), 1336 VMSTATE_UINT32(pllcfgr, Stm32l4x5RccState), 1337 VMSTATE_UINT32(pllsai1cfgr, Stm32l4x5RccState), 1338 VMSTATE_UINT32(pllsai2cfgr, Stm32l4x5RccState), 1339 VMSTATE_UINT32(cier, Stm32l4x5RccState), 1340 VMSTATE_UINT32(cifr, Stm32l4x5RccState), 1341 VMSTATE_UINT32(ahb1rstr, Stm32l4x5RccState), 1342 VMSTATE_UINT32(ahb2rstr, Stm32l4x5RccState), 1343 VMSTATE_UINT32(ahb3rstr, Stm32l4x5RccState), 1344 VMSTATE_UINT32(apb1rstr1, Stm32l4x5RccState), 1345 VMSTATE_UINT32(apb1rstr2, Stm32l4x5RccState), 1346 VMSTATE_UINT32(apb2rstr, Stm32l4x5RccState), 1347 VMSTATE_UINT32(ahb1enr, Stm32l4x5RccState), 1348 VMSTATE_UINT32(ahb2enr, Stm32l4x5RccState), 1349 VMSTATE_UINT32(ahb3enr, Stm32l4x5RccState), 1350 VMSTATE_UINT32(apb1enr1, Stm32l4x5RccState), 1351 VMSTATE_UINT32(apb1enr2, Stm32l4x5RccState), 1352 VMSTATE_UINT32(apb2enr, Stm32l4x5RccState), 1353 VMSTATE_UINT32(ahb1smenr, Stm32l4x5RccState), 1354 VMSTATE_UINT32(ahb2smenr, Stm32l4x5RccState), 1355 VMSTATE_UINT32(ahb3smenr, Stm32l4x5RccState), 1356 VMSTATE_UINT32(apb1smenr1, Stm32l4x5RccState), 1357 VMSTATE_UINT32(apb1smenr2, Stm32l4x5RccState), 1358 VMSTATE_UINT32(apb2smenr, Stm32l4x5RccState), 1359 VMSTATE_UINT32(ccipr, Stm32l4x5RccState), 1360 VMSTATE_UINT32(bdcr, Stm32l4x5RccState), 1361 VMSTATE_UINT32(csr, Stm32l4x5RccState), 1362 VMSTATE_CLOCK(hsi16_rc, Stm32l4x5RccState), 1363 VMSTATE_CLOCK(msi_rc, Stm32l4x5RccState), 1364 VMSTATE_CLOCK(hse, Stm32l4x5RccState), 1365 VMSTATE_CLOCK(lsi_rc, Stm32l4x5RccState), 1366 VMSTATE_CLOCK(lse_crystal, Stm32l4x5RccState), 1367 VMSTATE_CLOCK(sai1_extclk, Stm32l4x5RccState), 1368 VMSTATE_CLOCK(sai2_extclk, Stm32l4x5RccState), 1369 VMSTATE_END_OF_LIST() 1370 } 1371 }; 1372 1373 1374 static void stm32l4x5_rcc_realize(DeviceState *dev, Error **errp) 1375 { 1376 Stm32l4x5RccState *s = STM32L4X5_RCC(dev); 1377 size_t i; 1378 1379 if (s->hse_frequency < 4000000ULL || 1380 s->hse_frequency > 48000000ULL) { 1381 error_setg(errp, 1382 "HSE frequency is outside of the allowed [4-48]Mhz range: %" PRIx64 "", 1383 s->hse_frequency); 1384 return; 1385 } 1386 1387 for (i = 0; i < RCC_NUM_PLL; i++) { 1388 RccPllState *pll = &s->plls[i]; 1389 1390 clock_set_source(pll->in, s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].out); 1391 1392 if (!qdev_realize(DEVICE(pll), NULL, errp)) { 1393 return; 1394 } 1395 } 1396 1397 for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) { 1398 RccClockMuxState *clock_mux = &s->clock_muxes[i]; 1399 1400 connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping); 1401 1402 if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) { 1403 return; 1404 } 1405 } 1406 1407 /* 1408 * Start clocks after everything is connected 1409 * to propagate the frequencies along the tree. 1410 */ 1411 clock_update_hz(s->msi_rc, MSI_DEFAULT_FRQ); 1412 clock_update_hz(s->sai1_extclk, s->sai1_extclk_frequency); 1413 clock_update_hz(s->sai2_extclk, s->sai2_extclk_frequency); 1414 clock_update(s->gnd, 0); 1415 } 1416 1417 static Property stm32l4x5_rcc_properties[] = { 1418 DEFINE_PROP_UINT64("hse_frequency", Stm32l4x5RccState, 1419 hse_frequency, HSE_DEFAULT_FRQ), 1420 DEFINE_PROP_UINT64("sai1_extclk_frequency", Stm32l4x5RccState, 1421 sai1_extclk_frequency, 0), 1422 DEFINE_PROP_UINT64("sai2_extclk_frequency", Stm32l4x5RccState, 1423 sai2_extclk_frequency, 0), 1424 DEFINE_PROP_END_OF_LIST(), 1425 }; 1426 1427 static void stm32l4x5_rcc_class_init(ObjectClass *klass, void *data) 1428 { 1429 DeviceClass *dc = DEVICE_CLASS(klass); 1430 ResettableClass *rc = RESETTABLE_CLASS(klass); 1431 1432 assert(ARRAY_SIZE(CLOCK_MUX_INIT_INFO) == RCC_NUM_CLOCK_MUX); 1433 1434 rc->phases.hold = stm32l4x5_rcc_reset_hold; 1435 device_class_set_props(dc, stm32l4x5_rcc_properties); 1436 dc->realize = stm32l4x5_rcc_realize; 1437 dc->vmsd = &vmstate_stm32l4x5_rcc; 1438 } 1439 1440 static const TypeInfo stm32l4x5_rcc_types[] = { 1441 { 1442 .name = TYPE_STM32L4X5_RCC, 1443 .parent = TYPE_SYS_BUS_DEVICE, 1444 .instance_size = sizeof(Stm32l4x5RccState), 1445 .instance_init = stm32l4x5_rcc_init, 1446 .class_init = stm32l4x5_rcc_class_init, 1447 }, { 1448 .name = TYPE_RCC_CLOCK_MUX, 1449 .parent = TYPE_DEVICE, 1450 .instance_size = sizeof(RccClockMuxState), 1451 .instance_init = clock_mux_init, 1452 .class_init = clock_mux_class_init, 1453 }, { 1454 .name = TYPE_RCC_PLL, 1455 .parent = TYPE_DEVICE, 1456 .instance_size = sizeof(RccPllState), 1457 .instance_init = pll_init, 1458 .class_init = pll_class_init, 1459 } 1460 }; 1461 1462 DEFINE_TYPES(stm32l4x5_rcc_types) 1463