1211e701dSPeter Maydell /* 2211e701dSPeter Maydell * ARM TrustZone master security controller emulation 3211e701dSPeter Maydell * 4211e701dSPeter Maydell * Copyright (c) 2018 Linaro Limited 5211e701dSPeter Maydell * Written by Peter Maydell 6211e701dSPeter Maydell * 7211e701dSPeter Maydell * This program is free software; you can redistribute it and/or modify 8211e701dSPeter Maydell * it under the terms of the GNU General Public License version 2 or 9211e701dSPeter Maydell * (at your option) any later version. 10211e701dSPeter Maydell */ 11211e701dSPeter Maydell 12211e701dSPeter Maydell #include "qemu/osdep.h" 13211e701dSPeter Maydell #include "qemu/log.h" 140b8fa32fSMarkus Armbruster #include "qemu/module.h" 15211e701dSPeter Maydell #include "qapi/error.h" 16211e701dSPeter Maydell #include "trace.h" 17211e701dSPeter Maydell #include "hw/sysbus.h" 18*d6454270SMarkus Armbruster #include "migration/vmstate.h" 19211e701dSPeter Maydell #include "hw/registerfields.h" 2064552b6bSMarkus Armbruster #include "hw/irq.h" 21211e701dSPeter Maydell #include "hw/misc/tz-msc.h" 22211e701dSPeter Maydell 23211e701dSPeter Maydell static void tz_msc_update_irq(TZMSC *s) 24211e701dSPeter Maydell { 25211e701dSPeter Maydell bool level = s->irq_status; 26211e701dSPeter Maydell 27211e701dSPeter Maydell trace_tz_msc_update_irq(level); 28211e701dSPeter Maydell qemu_set_irq(s->irq, level); 29211e701dSPeter Maydell } 30211e701dSPeter Maydell 31211e701dSPeter Maydell static void tz_msc_cfg_nonsec(void *opaque, int n, int level) 32211e701dSPeter Maydell { 33211e701dSPeter Maydell TZMSC *s = TZ_MSC(opaque); 34211e701dSPeter Maydell 35211e701dSPeter Maydell trace_tz_msc_cfg_nonsec(level); 36211e701dSPeter Maydell s->cfg_nonsec = level; 37211e701dSPeter Maydell } 38211e701dSPeter Maydell 39211e701dSPeter Maydell static void tz_msc_cfg_sec_resp(void *opaque, int n, int level) 40211e701dSPeter Maydell { 41211e701dSPeter Maydell TZMSC *s = TZ_MSC(opaque); 42211e701dSPeter Maydell 43211e701dSPeter Maydell trace_tz_msc_cfg_sec_resp(level); 44211e701dSPeter Maydell s->cfg_sec_resp = level; 45211e701dSPeter Maydell } 46211e701dSPeter Maydell 47211e701dSPeter Maydell static void tz_msc_irq_clear(void *opaque, int n, int level) 48211e701dSPeter Maydell { 49211e701dSPeter Maydell TZMSC *s = TZ_MSC(opaque); 50211e701dSPeter Maydell 51211e701dSPeter Maydell trace_tz_msc_irq_clear(level); 52211e701dSPeter Maydell 53211e701dSPeter Maydell s->irq_clear = level; 54211e701dSPeter Maydell if (level) { 55211e701dSPeter Maydell s->irq_status = false; 56211e701dSPeter Maydell tz_msc_update_irq(s); 57211e701dSPeter Maydell } 58211e701dSPeter Maydell } 59211e701dSPeter Maydell 60211e701dSPeter Maydell /* The MSC may either block a transaction by aborting it, block a 61211e701dSPeter Maydell * transaction by making it RAZ/WI, allow it through with 62211e701dSPeter Maydell * MemTxAttrs indicating a secure transaction, or allow it with 63211e701dSPeter Maydell * MemTxAttrs indicating a non-secure transaction. 64211e701dSPeter Maydell */ 65211e701dSPeter Maydell typedef enum MSCAction { 66211e701dSPeter Maydell MSCBlockAbort, 67211e701dSPeter Maydell MSCBlockRAZWI, 68211e701dSPeter Maydell MSCAllowSecure, 69211e701dSPeter Maydell MSCAllowNonSecure, 70211e701dSPeter Maydell } MSCAction; 71211e701dSPeter Maydell 72211e701dSPeter Maydell static MSCAction tz_msc_check(TZMSC *s, hwaddr addr) 73211e701dSPeter Maydell { 74211e701dSPeter Maydell /* 75211e701dSPeter Maydell * Check whether to allow an access from the bus master, returning 76211e701dSPeter Maydell * an MSCAction indicating the required behaviour. If the transaction 77211e701dSPeter Maydell * is blocked, the caller must check cfg_sec_resp to determine 78211e701dSPeter Maydell * whether to abort or RAZ/WI the transaction. 79211e701dSPeter Maydell */ 80211e701dSPeter Maydell IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(s->idau); 81211e701dSPeter Maydell IDAUInterface *ii = IDAU_INTERFACE(s->idau); 82211e701dSPeter Maydell bool idau_exempt = false, idau_ns = true, idau_nsc = true; 83211e701dSPeter Maydell int idau_region = IREGION_NOTVALID; 84211e701dSPeter Maydell 85211e701dSPeter Maydell iic->check(ii, addr, &idau_region, &idau_exempt, &idau_ns, &idau_nsc); 86211e701dSPeter Maydell 87211e701dSPeter Maydell if (idau_exempt) { 88211e701dSPeter Maydell /* 89211e701dSPeter Maydell * Uncheck region -- OK, transaction type depends on 90211e701dSPeter Maydell * whether bus master is configured as Secure or NonSecure 91211e701dSPeter Maydell */ 92211e701dSPeter Maydell return s->cfg_nonsec ? MSCAllowNonSecure : MSCAllowSecure; 93211e701dSPeter Maydell } 94211e701dSPeter Maydell 95211e701dSPeter Maydell if (idau_ns) { 96211e701dSPeter Maydell /* NonSecure region -- always forward as NS transaction */ 97211e701dSPeter Maydell return MSCAllowNonSecure; 98211e701dSPeter Maydell } 99211e701dSPeter Maydell 100211e701dSPeter Maydell if (!s->cfg_nonsec) { 101211e701dSPeter Maydell /* Access to Secure region by Secure bus master: OK */ 102211e701dSPeter Maydell return MSCAllowSecure; 103211e701dSPeter Maydell } 104211e701dSPeter Maydell 105211e701dSPeter Maydell /* Attempted access to Secure region by NS bus master: block */ 106211e701dSPeter Maydell trace_tz_msc_access_blocked(addr); 107211e701dSPeter Maydell if (!s->cfg_sec_resp) { 108211e701dSPeter Maydell return MSCBlockRAZWI; 109211e701dSPeter Maydell } 110211e701dSPeter Maydell 111211e701dSPeter Maydell /* 112211e701dSPeter Maydell * The TRM isn't clear on behaviour if irq_clear is high when a 113211e701dSPeter Maydell * transaction is blocked. We assume that the MSC behaves like the 114211e701dSPeter Maydell * PPC, where holding irq_clear high suppresses the interrupt. 115211e701dSPeter Maydell */ 116211e701dSPeter Maydell if (!s->irq_clear) { 117211e701dSPeter Maydell s->irq_status = true; 118211e701dSPeter Maydell tz_msc_update_irq(s); 119211e701dSPeter Maydell } 120211e701dSPeter Maydell return MSCBlockAbort; 121211e701dSPeter Maydell } 122211e701dSPeter Maydell 123211e701dSPeter Maydell static MemTxResult tz_msc_read(void *opaque, hwaddr addr, uint64_t *pdata, 124211e701dSPeter Maydell unsigned size, MemTxAttrs attrs) 125211e701dSPeter Maydell { 126211e701dSPeter Maydell TZMSC *s = opaque; 127211e701dSPeter Maydell AddressSpace *as = &s->downstream_as; 128211e701dSPeter Maydell uint64_t data; 129211e701dSPeter Maydell MemTxResult res; 130211e701dSPeter Maydell 131211e701dSPeter Maydell switch (tz_msc_check(s, addr)) { 132211e701dSPeter Maydell case MSCBlockAbort: 133211e701dSPeter Maydell return MEMTX_ERROR; 134211e701dSPeter Maydell case MSCBlockRAZWI: 135211e701dSPeter Maydell *pdata = 0; 136211e701dSPeter Maydell return MEMTX_OK; 137211e701dSPeter Maydell case MSCAllowSecure: 138211e701dSPeter Maydell attrs.secure = 1; 139211e701dSPeter Maydell attrs.unspecified = 0; 140211e701dSPeter Maydell break; 141211e701dSPeter Maydell case MSCAllowNonSecure: 142211e701dSPeter Maydell attrs.secure = 0; 143211e701dSPeter Maydell attrs.unspecified = 0; 144211e701dSPeter Maydell break; 145211e701dSPeter Maydell } 146211e701dSPeter Maydell 147211e701dSPeter Maydell switch (size) { 148211e701dSPeter Maydell case 1: 149211e701dSPeter Maydell data = address_space_ldub(as, addr, attrs, &res); 150211e701dSPeter Maydell break; 151211e701dSPeter Maydell case 2: 152211e701dSPeter Maydell data = address_space_lduw_le(as, addr, attrs, &res); 153211e701dSPeter Maydell break; 154211e701dSPeter Maydell case 4: 155211e701dSPeter Maydell data = address_space_ldl_le(as, addr, attrs, &res); 156211e701dSPeter Maydell break; 157211e701dSPeter Maydell case 8: 158211e701dSPeter Maydell data = address_space_ldq_le(as, addr, attrs, &res); 159211e701dSPeter Maydell break; 160211e701dSPeter Maydell default: 161211e701dSPeter Maydell g_assert_not_reached(); 162211e701dSPeter Maydell } 163211e701dSPeter Maydell *pdata = data; 164211e701dSPeter Maydell return res; 165211e701dSPeter Maydell } 166211e701dSPeter Maydell 167211e701dSPeter Maydell static MemTxResult tz_msc_write(void *opaque, hwaddr addr, uint64_t val, 168211e701dSPeter Maydell unsigned size, MemTxAttrs attrs) 169211e701dSPeter Maydell { 170211e701dSPeter Maydell TZMSC *s = opaque; 171211e701dSPeter Maydell AddressSpace *as = &s->downstream_as; 172211e701dSPeter Maydell MemTxResult res; 173211e701dSPeter Maydell 174211e701dSPeter Maydell switch (tz_msc_check(s, addr)) { 175211e701dSPeter Maydell case MSCBlockAbort: 176211e701dSPeter Maydell return MEMTX_ERROR; 177211e701dSPeter Maydell case MSCBlockRAZWI: 178211e701dSPeter Maydell return MEMTX_OK; 179211e701dSPeter Maydell case MSCAllowSecure: 180211e701dSPeter Maydell attrs.secure = 1; 181211e701dSPeter Maydell attrs.unspecified = 0; 182211e701dSPeter Maydell break; 183211e701dSPeter Maydell case MSCAllowNonSecure: 184211e701dSPeter Maydell attrs.secure = 0; 185211e701dSPeter Maydell attrs.unspecified = 0; 186211e701dSPeter Maydell break; 187211e701dSPeter Maydell } 188211e701dSPeter Maydell 189211e701dSPeter Maydell switch (size) { 190211e701dSPeter Maydell case 1: 191211e701dSPeter Maydell address_space_stb(as, addr, val, attrs, &res); 192211e701dSPeter Maydell break; 193211e701dSPeter Maydell case 2: 194211e701dSPeter Maydell address_space_stw_le(as, addr, val, attrs, &res); 195211e701dSPeter Maydell break; 196211e701dSPeter Maydell case 4: 197211e701dSPeter Maydell address_space_stl_le(as, addr, val, attrs, &res); 198211e701dSPeter Maydell break; 199211e701dSPeter Maydell case 8: 200211e701dSPeter Maydell address_space_stq_le(as, addr, val, attrs, &res); 201211e701dSPeter Maydell break; 202211e701dSPeter Maydell default: 203211e701dSPeter Maydell g_assert_not_reached(); 204211e701dSPeter Maydell } 205211e701dSPeter Maydell return res; 206211e701dSPeter Maydell } 207211e701dSPeter Maydell 208211e701dSPeter Maydell static const MemoryRegionOps tz_msc_ops = { 209211e701dSPeter Maydell .read_with_attrs = tz_msc_read, 210211e701dSPeter Maydell .write_with_attrs = tz_msc_write, 211211e701dSPeter Maydell .endianness = DEVICE_LITTLE_ENDIAN, 212211e701dSPeter Maydell }; 213211e701dSPeter Maydell 214211e701dSPeter Maydell static void tz_msc_reset(DeviceState *dev) 215211e701dSPeter Maydell { 216211e701dSPeter Maydell TZMSC *s = TZ_MSC(dev); 217211e701dSPeter Maydell 218211e701dSPeter Maydell trace_tz_msc_reset(); 219211e701dSPeter Maydell s->cfg_sec_resp = false; 220211e701dSPeter Maydell s->cfg_nonsec = false; 221211e701dSPeter Maydell s->irq_clear = 0; 222211e701dSPeter Maydell s->irq_status = 0; 223211e701dSPeter Maydell } 224211e701dSPeter Maydell 225211e701dSPeter Maydell static void tz_msc_init(Object *obj) 226211e701dSPeter Maydell { 227211e701dSPeter Maydell DeviceState *dev = DEVICE(obj); 228211e701dSPeter Maydell TZMSC *s = TZ_MSC(obj); 229211e701dSPeter Maydell 230211e701dSPeter Maydell qdev_init_gpio_in_named(dev, tz_msc_cfg_nonsec, "cfg_nonsec", 1); 231211e701dSPeter Maydell qdev_init_gpio_in_named(dev, tz_msc_cfg_sec_resp, "cfg_sec_resp", 1); 232211e701dSPeter Maydell qdev_init_gpio_in_named(dev, tz_msc_irq_clear, "irq_clear", 1); 233211e701dSPeter Maydell qdev_init_gpio_out_named(dev, &s->irq, "irq", 1); 234211e701dSPeter Maydell } 235211e701dSPeter Maydell 236211e701dSPeter Maydell static void tz_msc_realize(DeviceState *dev, Error **errp) 237211e701dSPeter Maydell { 238211e701dSPeter Maydell Object *obj = OBJECT(dev); 239211e701dSPeter Maydell SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 240211e701dSPeter Maydell TZMSC *s = TZ_MSC(dev); 241211e701dSPeter Maydell const char *name = "tz-msc-downstream"; 242211e701dSPeter Maydell uint64_t size; 243211e701dSPeter Maydell 244211e701dSPeter Maydell /* 245211e701dSPeter Maydell * We can't create the upstream end of the port until realize, 246211e701dSPeter Maydell * as we don't know the size of the MR used as the downstream until then. 247211e701dSPeter Maydell * We insist on having a downstream, to avoid complicating the 248211e701dSPeter Maydell * code with handling the "don't know how big this is" case. It's easy 249211e701dSPeter Maydell * enough for the user to create an unimplemented_device as downstream 250211e701dSPeter Maydell * if they have nothing else to plug into this. 251211e701dSPeter Maydell */ 252211e701dSPeter Maydell if (!s->downstream) { 253211e701dSPeter Maydell error_setg(errp, "MSC 'downstream' link not set"); 254211e701dSPeter Maydell return; 255211e701dSPeter Maydell } 256211e701dSPeter Maydell if (!s->idau) { 257211e701dSPeter Maydell error_setg(errp, "MSC 'idau' link not set"); 258211e701dSPeter Maydell return; 259211e701dSPeter Maydell } 260211e701dSPeter Maydell 261211e701dSPeter Maydell size = memory_region_size(s->downstream); 262211e701dSPeter Maydell address_space_init(&s->downstream_as, s->downstream, name); 263211e701dSPeter Maydell memory_region_init_io(&s->upstream, obj, &tz_msc_ops, s, name, size); 264211e701dSPeter Maydell sysbus_init_mmio(sbd, &s->upstream); 265211e701dSPeter Maydell } 266211e701dSPeter Maydell 267211e701dSPeter Maydell static const VMStateDescription tz_msc_vmstate = { 268211e701dSPeter Maydell .name = "tz-msc", 269211e701dSPeter Maydell .version_id = 1, 270211e701dSPeter Maydell .minimum_version_id = 1, 271211e701dSPeter Maydell .fields = (VMStateField[]) { 272211e701dSPeter Maydell VMSTATE_BOOL(cfg_nonsec, TZMSC), 273211e701dSPeter Maydell VMSTATE_BOOL(cfg_sec_resp, TZMSC), 274211e701dSPeter Maydell VMSTATE_BOOL(irq_clear, TZMSC), 275211e701dSPeter Maydell VMSTATE_BOOL(irq_status, TZMSC), 276211e701dSPeter Maydell VMSTATE_END_OF_LIST() 277211e701dSPeter Maydell } 278211e701dSPeter Maydell }; 279211e701dSPeter Maydell 280211e701dSPeter Maydell static Property tz_msc_properties[] = { 281211e701dSPeter Maydell DEFINE_PROP_LINK("downstream", TZMSC, downstream, 282211e701dSPeter Maydell TYPE_MEMORY_REGION, MemoryRegion *), 283211e701dSPeter Maydell DEFINE_PROP_LINK("idau", TZMSC, idau, 284211e701dSPeter Maydell TYPE_IDAU_INTERFACE, IDAUInterface *), 285211e701dSPeter Maydell DEFINE_PROP_END_OF_LIST(), 286211e701dSPeter Maydell }; 287211e701dSPeter Maydell 288211e701dSPeter Maydell static void tz_msc_class_init(ObjectClass *klass, void *data) 289211e701dSPeter Maydell { 290211e701dSPeter Maydell DeviceClass *dc = DEVICE_CLASS(klass); 291211e701dSPeter Maydell 292211e701dSPeter Maydell dc->realize = tz_msc_realize; 293211e701dSPeter Maydell dc->vmsd = &tz_msc_vmstate; 294211e701dSPeter Maydell dc->reset = tz_msc_reset; 295211e701dSPeter Maydell dc->props = tz_msc_properties; 296211e701dSPeter Maydell } 297211e701dSPeter Maydell 298211e701dSPeter Maydell static const TypeInfo tz_msc_info = { 299211e701dSPeter Maydell .name = TYPE_TZ_MSC, 300211e701dSPeter Maydell .parent = TYPE_SYS_BUS_DEVICE, 301211e701dSPeter Maydell .instance_size = sizeof(TZMSC), 302211e701dSPeter Maydell .instance_init = tz_msc_init, 303211e701dSPeter Maydell .class_init = tz_msc_class_init, 304211e701dSPeter Maydell }; 305211e701dSPeter Maydell 306211e701dSPeter Maydell static void tz_msc_register_types(void) 307211e701dSPeter Maydell { 308211e701dSPeter Maydell type_register_static(&tz_msc_info); 309211e701dSPeter Maydell } 310211e701dSPeter Maydell 311211e701dSPeter Maydell type_init(tz_msc_register_types); 312