1 /* 2 * Status and system control registers for Xilinx Zynq Platform 3 * 4 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu> 5 * Copyright (c) 2012 PetaLogix Pty Ltd. 6 * Based on hw/arm_sysctl.c, written by Paul Brook 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 * 13 * You should have received a copy of the GNU General Public License along 14 * with this program; if not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu/timer.h" 19 #include "sysemu/runstate.h" 20 #include "hw/sysbus.h" 21 #include "migration/vmstate.h" 22 #include "qemu/log.h" 23 #include "qemu/module.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-clock.h" 26 #include "qom/object.h" 27 28 #ifndef ZYNQ_SLCR_ERR_DEBUG 29 #define ZYNQ_SLCR_ERR_DEBUG 0 30 #endif 31 32 #define DB_PRINT(...) do { \ 33 if (ZYNQ_SLCR_ERR_DEBUG) { \ 34 fprintf(stderr, ": %s: ", __func__); \ 35 fprintf(stderr, ## __VA_ARGS__); \ 36 } \ 37 } while (0) 38 39 #define XILINX_LOCK_KEY 0x767b 40 #define XILINX_UNLOCK_KEY 0xdf0d 41 42 REG32(SCL, 0x000) 43 REG32(LOCK, 0x004) 44 REG32(UNLOCK, 0x008) 45 REG32(LOCKSTA, 0x00c) 46 47 REG32(ARM_PLL_CTRL, 0x100) 48 REG32(DDR_PLL_CTRL, 0x104) 49 REG32(IO_PLL_CTRL, 0x108) 50 /* fields for [ARM|DDR|IO]_PLL_CTRL registers */ 51 FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1) 52 FIELD(xxx_PLL_CTRL, PLL_PWRDWN, 1, 1) 53 FIELD(xxx_PLL_CTRL, PLL_BYPASS_QUAL, 3, 1) 54 FIELD(xxx_PLL_CTRL, PLL_BYPASS_FORCE, 4, 1) 55 FIELD(xxx_PLL_CTRL, PLL_FPDIV, 12, 7) 56 REG32(PLL_STATUS, 0x10c) 57 REG32(ARM_PLL_CFG, 0x110) 58 REG32(DDR_PLL_CFG, 0x114) 59 REG32(IO_PLL_CFG, 0x118) 60 61 REG32(ARM_CLK_CTRL, 0x120) 62 REG32(DDR_CLK_CTRL, 0x124) 63 REG32(DCI_CLK_CTRL, 0x128) 64 REG32(APER_CLK_CTRL, 0x12c) 65 REG32(USB0_CLK_CTRL, 0x130) 66 REG32(USB1_CLK_CTRL, 0x134) 67 REG32(GEM0_RCLK_CTRL, 0x138) 68 REG32(GEM1_RCLK_CTRL, 0x13c) 69 REG32(GEM0_CLK_CTRL, 0x140) 70 REG32(GEM1_CLK_CTRL, 0x144) 71 REG32(SMC_CLK_CTRL, 0x148) 72 REG32(LQSPI_CLK_CTRL, 0x14c) 73 REG32(SDIO_CLK_CTRL, 0x150) 74 REG32(UART_CLK_CTRL, 0x154) 75 FIELD(UART_CLK_CTRL, CLKACT0, 0, 1) 76 FIELD(UART_CLK_CTRL, CLKACT1, 1, 1) 77 FIELD(UART_CLK_CTRL, SRCSEL, 4, 2) 78 FIELD(UART_CLK_CTRL, DIVISOR, 8, 6) 79 REG32(SPI_CLK_CTRL, 0x158) 80 REG32(CAN_CLK_CTRL, 0x15c) 81 REG32(CAN_MIOCLK_CTRL, 0x160) 82 REG32(DBG_CLK_CTRL, 0x164) 83 REG32(PCAP_CLK_CTRL, 0x168) 84 REG32(TOPSW_CLK_CTRL, 0x16c) 85 86 #define FPGA_CTRL_REGS(n, start) \ 87 REG32(FPGA ## n ## _CLK_CTRL, (start)) \ 88 REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\ 89 REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\ 90 REG32(FPGA ## n ## _THR_STA, (start) + 0xc) 91 FPGA_CTRL_REGS(0, 0x170) 92 FPGA_CTRL_REGS(1, 0x180) 93 FPGA_CTRL_REGS(2, 0x190) 94 FPGA_CTRL_REGS(3, 0x1a0) 95 96 REG32(BANDGAP_TRIP, 0x1b8) 97 REG32(PLL_PREDIVISOR, 0x1c0) 98 REG32(CLK_621_TRUE, 0x1c4) 99 100 REG32(PSS_RST_CTRL, 0x200) 101 FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1) 102 REG32(DDR_RST_CTRL, 0x204) 103 REG32(TOPSW_RESET_CTRL, 0x208) 104 REG32(DMAC_RST_CTRL, 0x20c) 105 REG32(USB_RST_CTRL, 0x210) 106 REG32(GEM_RST_CTRL, 0x214) 107 REG32(SDIO_RST_CTRL, 0x218) 108 REG32(SPI_RST_CTRL, 0x21c) 109 REG32(CAN_RST_CTRL, 0x220) 110 REG32(I2C_RST_CTRL, 0x224) 111 REG32(UART_RST_CTRL, 0x228) 112 REG32(GPIO_RST_CTRL, 0x22c) 113 REG32(LQSPI_RST_CTRL, 0x230) 114 REG32(SMC_RST_CTRL, 0x234) 115 REG32(OCM_RST_CTRL, 0x238) 116 REG32(FPGA_RST_CTRL, 0x240) 117 REG32(A9_CPU_RST_CTRL, 0x244) 118 119 REG32(RS_AWDT_CTRL, 0x24c) 120 REG32(RST_REASON, 0x250) 121 122 REG32(REBOOT_STATUS, 0x258) 123 REG32(BOOT_MODE, 0x25c) 124 125 REG32(APU_CTRL, 0x300) 126 REG32(WDT_CLK_SEL, 0x304) 127 128 REG32(TZ_DMA_NS, 0x440) 129 REG32(TZ_DMA_IRQ_NS, 0x444) 130 REG32(TZ_DMA_PERIPH_NS, 0x448) 131 132 REG32(PSS_IDCODE, 0x530) 133 134 REG32(DDR_URGENT, 0x600) 135 REG32(DDR_CAL_START, 0x60c) 136 REG32(DDR_REF_START, 0x614) 137 REG32(DDR_CMD_STA, 0x618) 138 REG32(DDR_URGENT_SEL, 0x61c) 139 REG32(DDR_DFI_STATUS, 0x620) 140 141 REG32(MIO, 0x700) 142 #define MIO_LENGTH 54 143 144 REG32(MIO_LOOPBACK, 0x804) 145 REG32(MIO_MST_TRI0, 0x808) 146 REG32(MIO_MST_TRI1, 0x80c) 147 148 REG32(SD0_WP_CD_SEL, 0x830) 149 REG32(SD1_WP_CD_SEL, 0x834) 150 151 REG32(LVL_SHFTR_EN, 0x900) 152 REG32(OCM_CFG, 0x910) 153 154 REG32(CPU_RAM, 0xa00) 155 156 REG32(IOU, 0xa30) 157 158 REG32(DMAC_RAM, 0xa50) 159 160 REG32(AFI0, 0xa60) 161 REG32(AFI1, 0xa6c) 162 REG32(AFI2, 0xa78) 163 REG32(AFI3, 0xa84) 164 #define AFI_LENGTH 3 165 166 REG32(OCM, 0xa90) 167 168 REG32(DEVCI_RAM, 0xaa0) 169 170 REG32(CSG_RAM, 0xab0) 171 172 REG32(GPIOB_CTRL, 0xb00) 173 REG32(GPIOB_CFG_CMOS18, 0xb04) 174 REG32(GPIOB_CFG_CMOS25, 0xb08) 175 REG32(GPIOB_CFG_CMOS33, 0xb0c) 176 REG32(GPIOB_CFG_HSTL, 0xb14) 177 REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) 178 179 REG32(DDRIOB, 0xb40) 180 #define DDRIOB_LENGTH 14 181 182 #define ZYNQ_SLCR_MMIO_SIZE 0x1000 183 #define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4) 184 185 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr" 186 OBJECT_DECLARE_SIMPLE_TYPE(ZynqSLCRState, ZYNQ_SLCR) 187 188 struct ZynqSLCRState { 189 SysBusDevice parent_obj; 190 191 MemoryRegion iomem; 192 193 uint32_t regs[ZYNQ_SLCR_NUM_REGS]; 194 195 Clock *ps_clk; 196 Clock *uart0_ref_clk; 197 Clock *uart1_ref_clk; 198 }; 199 200 /* 201 * return the output frequency of ARM/DDR/IO pll 202 * using input frequency and PLL_CTRL register 203 */ 204 static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg) 205 { 206 uint32_t mult = ((ctrl_reg & R_xxx_PLL_CTRL_PLL_FPDIV_MASK) >> 207 R_xxx_PLL_CTRL_PLL_FPDIV_SHIFT); 208 209 /* first, check if pll is bypassed */ 210 if (ctrl_reg & R_xxx_PLL_CTRL_PLL_BYPASS_FORCE_MASK) { 211 return input; 212 } 213 214 /* is pll disabled ? */ 215 if (ctrl_reg & (R_xxx_PLL_CTRL_PLL_RESET_MASK | 216 R_xxx_PLL_CTRL_PLL_PWRDWN_MASK)) { 217 return 0; 218 } 219 220 /* Consider zero feedback as maximum divide ratio possible */ 221 if (!mult) { 222 mult = 1 << R_xxx_PLL_CTRL_PLL_FPDIV_LENGTH; 223 } 224 225 /* frequency multiplier -> period division */ 226 return input / mult; 227 } 228 229 /* 230 * return the output period of a clock given: 231 * + the periods in an array corresponding to input mux selector 232 * + the register xxx_CLK_CTRL value 233 * + enable bit index in ctrl register 234 * 235 * This function makes the assumption that the ctrl_reg value is organized as 236 * follows: 237 * + bits[13:8] clock frequency divisor 238 * + bits[5:4] clock mux selector (index in array) 239 * + bits[index] clock enable 240 */ 241 static uint64_t zynq_slcr_compute_clock(const uint64_t periods[], 242 uint32_t ctrl_reg, 243 unsigned index) 244 { 245 uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */ 246 uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */ 247 248 /* first, check if clock is disabled */ 249 if (((ctrl_reg >> index) & 1u) == 0) { 250 return 0; 251 } 252 253 /* 254 * according to the Zynq technical ref. manual UG585 v1.12.2 in 255 * Clocks chapter, section 25.10.1 page 705: 256 * "The 6-bit divider provides a divide range of 1 to 63" 257 * We follow here what is implemented in linux kernel and consider 258 * the 0 value as a bypass (no division). 259 */ 260 /* frequency divisor -> period multiplication */ 261 return periods[srcsel] * (divisor ? divisor : 1u); 262 } 263 264 /* 265 * macro helper around zynq_slcr_compute_clock to avoid repeating 266 * the register name. 267 */ 268 #define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \ 269 zynq_slcr_compute_clock((plls), (state)->regs[reg], \ 270 reg ## _ ## enable_field ## _SHIFT) 271 272 /** 273 * Compute and set the ouputs clocks periods. 274 * But do not propagate them further. Connected clocks 275 * will not receive any updates (See zynq_slcr_compute_clocks()) 276 */ 277 static void zynq_slcr_compute_clocks(ZynqSLCRState *s) 278 { 279 uint64_t ps_clk = clock_get(s->ps_clk); 280 281 /* consider outputs clocks are disabled while in reset */ 282 if (device_is_in_reset(DEVICE(s))) { 283 ps_clk = 0; 284 } 285 286 uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]); 287 uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]); 288 uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]); 289 290 uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll}; 291 292 /* compute uartX reference clocks */ 293 clock_set(s->uart0_ref_clk, 294 ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); 295 clock_set(s->uart1_ref_clk, 296 ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); 297 } 298 299 /** 300 * Propagate the outputs clocks. 301 * zynq_slcr_compute_clocks() should have been called before 302 * to configure them. 303 */ 304 static void zynq_slcr_propagate_clocks(ZynqSLCRState *s) 305 { 306 clock_propagate(s->uart0_ref_clk); 307 clock_propagate(s->uart1_ref_clk); 308 } 309 310 static void zynq_slcr_ps_clk_callback(void *opaque, ClockEvent event) 311 { 312 ZynqSLCRState *s = (ZynqSLCRState *) opaque; 313 314 zynq_slcr_compute_clocks(s); 315 zynq_slcr_propagate_clocks(s); 316 } 317 318 static void zynq_slcr_reset_init(Object *obj, ResetType type) 319 { 320 ZynqSLCRState *s = ZYNQ_SLCR(obj); 321 int i; 322 323 DB_PRINT("RESET\n"); 324 325 s->regs[R_LOCKSTA] = 1; 326 /* 0x100 - 0x11C */ 327 s->regs[R_ARM_PLL_CTRL] = 0x0001A008; 328 s->regs[R_DDR_PLL_CTRL] = 0x0001A008; 329 s->regs[R_IO_PLL_CTRL] = 0x0001A008; 330 s->regs[R_PLL_STATUS] = 0x0000003F; 331 s->regs[R_ARM_PLL_CFG] = 0x00014000; 332 s->regs[R_DDR_PLL_CFG] = 0x00014000; 333 s->regs[R_IO_PLL_CFG] = 0x00014000; 334 335 /* 0x120 - 0x16C */ 336 s->regs[R_ARM_CLK_CTRL] = 0x1F000400; 337 s->regs[R_DDR_CLK_CTRL] = 0x18400003; 338 s->regs[R_DCI_CLK_CTRL] = 0x01E03201; 339 s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD; 340 s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941; 341 s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001; 342 s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01; 343 s->regs[R_SMC_CLK_CTRL] = 0x00003C01; 344 s->regs[R_LQSPI_CLK_CTRL] = 0x00002821; 345 s->regs[R_SDIO_CLK_CTRL] = 0x00001E03; 346 s->regs[R_UART_CLK_CTRL] = 0x00003F03; 347 s->regs[R_SPI_CLK_CTRL] = 0x00003F03; 348 s->regs[R_CAN_CLK_CTRL] = 0x00501903; 349 s->regs[R_DBG_CLK_CTRL] = 0x00000F03; 350 s->regs[R_PCAP_CLK_CTRL] = 0x00000F01; 351 352 /* 0x170 - 0x1AC */ 353 s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL] 354 = s->regs[R_FPGA2_CLK_CTRL] 355 = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800; 356 s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA] 357 = s->regs[R_FPGA2_THR_STA] 358 = s->regs[R_FPGA3_THR_STA] = 0x00010000; 359 360 /* 0x1B0 - 0x1D8 */ 361 s->regs[R_BANDGAP_TRIP] = 0x0000001F; 362 s->regs[R_PLL_PREDIVISOR] = 0x00000001; 363 s->regs[R_CLK_621_TRUE] = 0x00000001; 364 365 /* 0x200 - 0x25C */ 366 s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F; 367 s->regs[R_RST_REASON] = 0x00000040; 368 369 s->regs[R_BOOT_MODE] = 0x00000001; 370 371 /* 0x700 - 0x7D4 */ 372 for (i = 0; i < 54; i++) { 373 s->regs[R_MIO + i] = 0x00001601; 374 } 375 for (i = 2; i <= 8; i++) { 376 s->regs[R_MIO + i] = 0x00000601; 377 } 378 379 s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF; 380 381 s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3] 382 = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7] 383 = 0x00010101; 384 s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101; 385 s->regs[R_CPU_RAM + 6] = 0x00000001; 386 387 s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2] 388 = s->regs[R_IOU + 3] = 0x09090909; 389 s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909; 390 s->regs[R_IOU + 6] = 0x00000909; 391 392 s->regs[R_DMAC_RAM] = 0x00000009; 393 394 s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909; 395 s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909; 396 s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909; 397 s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909; 398 s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2] 399 = s->regs[R_AFI3 + 2] = 0x00000909; 400 401 s->regs[R_OCM + 0] = 0x01010101; 402 s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909; 403 404 s->regs[R_DEVCI_RAM] = 0x00000909; 405 s->regs[R_CSG_RAM] = 0x00000001; 406 407 s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2] 408 = s->regs[R_DDRIOB + 3] = 0x00000e00; 409 s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6] 410 = 0x00000e00; 411 s->regs[R_DDRIOB + 12] = 0x00000021; 412 } 413 414 static void zynq_slcr_reset_hold(Object *obj) 415 { 416 ZynqSLCRState *s = ZYNQ_SLCR(obj); 417 418 /* will disable all output clocks */ 419 zynq_slcr_compute_clocks(s); 420 zynq_slcr_propagate_clocks(s); 421 } 422 423 static void zynq_slcr_reset_exit(Object *obj) 424 { 425 ZynqSLCRState *s = ZYNQ_SLCR(obj); 426 427 /* will compute output clocks according to ps_clk and registers */ 428 zynq_slcr_compute_clocks(s); 429 zynq_slcr_propagate_clocks(s); 430 } 431 432 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) 433 { 434 switch (offset) { 435 case R_LOCK: 436 case R_UNLOCK: 437 case R_DDR_CAL_START: 438 case R_DDR_REF_START: 439 return !rnw; /* Write only */ 440 case R_LOCKSTA: 441 case R_FPGA0_THR_STA: 442 case R_FPGA1_THR_STA: 443 case R_FPGA2_THR_STA: 444 case R_FPGA3_THR_STA: 445 case R_BOOT_MODE: 446 case R_PSS_IDCODE: 447 case R_DDR_CMD_STA: 448 case R_DDR_DFI_STATUS: 449 case R_PLL_STATUS: 450 return rnw;/* read only */ 451 case R_SCL: 452 case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL: 453 case R_ARM_PLL_CFG ... R_IO_PLL_CFG: 454 case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL: 455 case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT: 456 case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT: 457 case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT: 458 case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT: 459 case R_BANDGAP_TRIP: 460 case R_PLL_PREDIVISOR: 461 case R_CLK_621_TRUE: 462 case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL: 463 case R_RS_AWDT_CTRL: 464 case R_RST_REASON: 465 case R_REBOOT_STATUS: 466 case R_APU_CTRL: 467 case R_WDT_CLK_SEL: 468 case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS: 469 case R_DDR_URGENT: 470 case R_DDR_URGENT_SEL: 471 case R_MIO ... R_MIO + MIO_LENGTH - 1: 472 case R_MIO_LOOPBACK ... R_MIO_MST_TRI1: 473 case R_SD0_WP_CD_SEL: 474 case R_SD1_WP_CD_SEL: 475 case R_LVL_SHFTR_EN: 476 case R_OCM_CFG: 477 case R_CPU_RAM: 478 case R_IOU: 479 case R_DMAC_RAM: 480 case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1: 481 case R_OCM: 482 case R_DEVCI_RAM: 483 case R_CSG_RAM: 484 case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33: 485 case R_GPIOB_CFG_HSTL: 486 case R_GPIOB_DRVR_BIAS_CTRL: 487 case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1: 488 return true; 489 default: 490 return false; 491 } 492 } 493 494 static uint64_t zynq_slcr_read(void *opaque, hwaddr offset, 495 unsigned size) 496 { 497 ZynqSLCRState *s = opaque; 498 offset /= 4; 499 uint32_t ret = s->regs[offset]; 500 501 if (!zynq_slcr_check_offset(offset, true)) { 502 qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to " 503 " addr %" HWADDR_PRIx "\n", offset * 4); 504 } 505 506 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret); 507 return ret; 508 } 509 510 static void zynq_slcr_write(void *opaque, hwaddr offset, 511 uint64_t val, unsigned size) 512 { 513 ZynqSLCRState *s = (ZynqSLCRState *)opaque; 514 offset /= 4; 515 516 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val); 517 518 if (!zynq_slcr_check_offset(offset, false)) { 519 qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to " 520 "addr %" HWADDR_PRIx "\n", offset * 4); 521 return; 522 } 523 524 switch (offset) { 525 case R_SCL: 526 s->regs[R_SCL] = val & 0x1; 527 return; 528 case R_LOCK: 529 if ((val & 0xFFFF) == XILINX_LOCK_KEY) { 530 DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, 531 (unsigned)val & 0xFFFF); 532 s->regs[R_LOCKSTA] = 1; 533 } else { 534 DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", 535 (int)offset, (unsigned)val & 0xFFFF); 536 } 537 return; 538 case R_UNLOCK: 539 if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) { 540 DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, 541 (unsigned)val & 0xFFFF); 542 s->regs[R_LOCKSTA] = 0; 543 } else { 544 DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", 545 (int)offset, (unsigned)val & 0xFFFF); 546 } 547 return; 548 } 549 550 if (s->regs[R_LOCKSTA]) { 551 qemu_log_mask(LOG_GUEST_ERROR, 552 "SCLR registers are locked. Unlock them first\n"); 553 return; 554 } 555 s->regs[offset] = val; 556 557 switch (offset) { 558 case R_PSS_RST_CTRL: 559 if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) { 560 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 561 } 562 break; 563 case R_IO_PLL_CTRL: 564 case R_ARM_PLL_CTRL: 565 case R_DDR_PLL_CTRL: 566 case R_UART_CLK_CTRL: 567 zynq_slcr_compute_clocks(s); 568 zynq_slcr_propagate_clocks(s); 569 break; 570 } 571 } 572 573 static const MemoryRegionOps slcr_ops = { 574 .read = zynq_slcr_read, 575 .write = zynq_slcr_write, 576 .endianness = DEVICE_NATIVE_ENDIAN, 577 }; 578 579 static const ClockPortInitArray zynq_slcr_clocks = { 580 QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback, ClockUpdate), 581 QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), 582 QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), 583 QDEV_CLOCK_END 584 }; 585 586 static void zynq_slcr_init(Object *obj) 587 { 588 ZynqSLCRState *s = ZYNQ_SLCR(obj); 589 590 memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", 591 ZYNQ_SLCR_MMIO_SIZE); 592 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 593 594 qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks); 595 } 596 597 static const VMStateDescription vmstate_zynq_slcr = { 598 .name = "zynq_slcr", 599 .version_id = 3, 600 .minimum_version_id = 2, 601 .fields = (VMStateField[]) { 602 VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS), 603 VMSTATE_CLOCK_V(ps_clk, ZynqSLCRState, 3), 604 VMSTATE_END_OF_LIST() 605 } 606 }; 607 608 static void zynq_slcr_class_init(ObjectClass *klass, void *data) 609 { 610 DeviceClass *dc = DEVICE_CLASS(klass); 611 ResettableClass *rc = RESETTABLE_CLASS(klass); 612 613 dc->vmsd = &vmstate_zynq_slcr; 614 rc->phases.enter = zynq_slcr_reset_init; 615 rc->phases.hold = zynq_slcr_reset_hold; 616 rc->phases.exit = zynq_slcr_reset_exit; 617 } 618 619 static const TypeInfo zynq_slcr_info = { 620 .class_init = zynq_slcr_class_init, 621 .name = TYPE_ZYNQ_SLCR, 622 .parent = TYPE_SYS_BUS_DEVICE, 623 .instance_size = sizeof(ZynqSLCRState), 624 .instance_init = zynq_slcr_init, 625 }; 626 627 static void zynq_slcr_register_types(void) 628 { 629 type_register_static(&zynq_slcr_info); 630 } 631 632 type_init(zynq_slcr_register_types) 633