129d08975SNiek Linnenbank /* 229d08975SNiek Linnenbank * Allwinner Sun8i Ethernet MAC emulation 329d08975SNiek Linnenbank * 429d08975SNiek Linnenbank * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 529d08975SNiek Linnenbank * 629d08975SNiek Linnenbank * This program is free software: you can redistribute it and/or modify 729d08975SNiek Linnenbank * it under the terms of the GNU General Public License as published by 829d08975SNiek Linnenbank * the Free Software Foundation, either version 2 of the License, or 929d08975SNiek Linnenbank * (at your option) any later version. 1029d08975SNiek Linnenbank * 1129d08975SNiek Linnenbank * This program is distributed in the hope that it will be useful, 1229d08975SNiek Linnenbank * but WITHOUT ANY WARRANTY; without even the implied warranty of 1329d08975SNiek Linnenbank * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1429d08975SNiek Linnenbank * GNU General Public License for more details. 1529d08975SNiek Linnenbank * 1629d08975SNiek Linnenbank * You should have received a copy of the GNU General Public License 1729d08975SNiek Linnenbank * along with this program. If not, see <http://www.gnu.org/licenses/>. 1829d08975SNiek Linnenbank */ 1929d08975SNiek Linnenbank 2029d08975SNiek Linnenbank #include "qemu/osdep.h" 2129d08975SNiek Linnenbank #include "qemu/units.h" 224757cb85SPhilippe Mathieu-Daudé #include "qapi/error.h" 2329d08975SNiek Linnenbank #include "hw/sysbus.h" 2429d08975SNiek Linnenbank #include "migration/vmstate.h" 2529d08975SNiek Linnenbank #include "net/net.h" 2629d08975SNiek Linnenbank #include "hw/irq.h" 2729d08975SNiek Linnenbank #include "hw/qdev-properties.h" 2829d08975SNiek Linnenbank #include "qemu/log.h" 2929d08975SNiek Linnenbank #include "trace.h" 3029d08975SNiek Linnenbank #include "net/checksum.h" 3129d08975SNiek Linnenbank #include "qemu/module.h" 3229d08975SNiek Linnenbank #include "exec/cpu-common.h" 334757cb85SPhilippe Mathieu-Daudé #include "sysemu/dma.h" 3429d08975SNiek Linnenbank #include "hw/net/allwinner-sun8i-emac.h" 3529d08975SNiek Linnenbank 3629d08975SNiek Linnenbank /* EMAC register offsets */ 3729d08975SNiek Linnenbank enum { 3829d08975SNiek Linnenbank REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */ 3929d08975SNiek Linnenbank REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */ 4029d08975SNiek Linnenbank REG_INT_STA = 0x0008, /* Interrupt Status */ 4129d08975SNiek Linnenbank REG_INT_EN = 0x000C, /* Interrupt Enable */ 4229d08975SNiek Linnenbank REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */ 4329d08975SNiek Linnenbank REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */ 4429d08975SNiek Linnenbank REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */ 4529d08975SNiek Linnenbank REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */ 4629d08975SNiek Linnenbank REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */ 4729d08975SNiek Linnenbank REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */ 4829d08975SNiek Linnenbank REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */ 4929d08975SNiek Linnenbank REG_FRM_FLT = 0x0038, /* Receive Frame Filter */ 5029d08975SNiek Linnenbank REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */ 5129d08975SNiek Linnenbank REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */ 5229d08975SNiek Linnenbank REG_MII_CMD = 0x0048, /* Management Interface Command */ 5329d08975SNiek Linnenbank REG_MII_DATA = 0x004C, /* Management Interface Data */ 5429d08975SNiek Linnenbank REG_ADDR_HIGH = 0x0050, /* MAC Address High */ 5529d08975SNiek Linnenbank REG_ADDR_LOW = 0x0054, /* MAC Address Low */ 5629d08975SNiek Linnenbank REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */ 5729d08975SNiek Linnenbank REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */ 5829d08975SNiek Linnenbank REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */ 5929d08975SNiek Linnenbank REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */ 6029d08975SNiek Linnenbank REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */ 6129d08975SNiek Linnenbank REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */ 6229d08975SNiek Linnenbank REG_RGMII_STA = 0x00D0, /* RGMII Status */ 6329d08975SNiek Linnenbank }; 6429d08975SNiek Linnenbank 6529d08975SNiek Linnenbank /* EMAC register flags */ 6629d08975SNiek Linnenbank enum { 6729d08975SNiek Linnenbank BASIC_CTL0_100Mbps = (0b11 << 2), 6829d08975SNiek Linnenbank BASIC_CTL0_FD = (1 << 0), 6929d08975SNiek Linnenbank BASIC_CTL1_SOFTRST = (1 << 0), 7029d08975SNiek Linnenbank }; 7129d08975SNiek Linnenbank 7229d08975SNiek Linnenbank enum { 7329d08975SNiek Linnenbank INT_STA_RGMII_LINK = (1 << 16), 7429d08975SNiek Linnenbank INT_STA_RX_EARLY = (1 << 13), 7529d08975SNiek Linnenbank INT_STA_RX_OVERFLOW = (1 << 12), 7629d08975SNiek Linnenbank INT_STA_RX_TIMEOUT = (1 << 11), 7729d08975SNiek Linnenbank INT_STA_RX_DMA_STOP = (1 << 10), 7829d08975SNiek Linnenbank INT_STA_RX_BUF_UA = (1 << 9), 7929d08975SNiek Linnenbank INT_STA_RX = (1 << 8), 8029d08975SNiek Linnenbank INT_STA_TX_EARLY = (1 << 5), 8129d08975SNiek Linnenbank INT_STA_TX_UNDERFLOW = (1 << 4), 8229d08975SNiek Linnenbank INT_STA_TX_TIMEOUT = (1 << 3), 8329d08975SNiek Linnenbank INT_STA_TX_BUF_UA = (1 << 2), 8429d08975SNiek Linnenbank INT_STA_TX_DMA_STOP = (1 << 1), 8529d08975SNiek Linnenbank INT_STA_TX = (1 << 0), 8629d08975SNiek Linnenbank }; 8729d08975SNiek Linnenbank 8829d08975SNiek Linnenbank enum { 8929d08975SNiek Linnenbank INT_EN_RX_EARLY = (1 << 13), 9029d08975SNiek Linnenbank INT_EN_RX_OVERFLOW = (1 << 12), 9129d08975SNiek Linnenbank INT_EN_RX_TIMEOUT = (1 << 11), 9229d08975SNiek Linnenbank INT_EN_RX_DMA_STOP = (1 << 10), 9329d08975SNiek Linnenbank INT_EN_RX_BUF_UA = (1 << 9), 9429d08975SNiek Linnenbank INT_EN_RX = (1 << 8), 9529d08975SNiek Linnenbank INT_EN_TX_EARLY = (1 << 5), 9629d08975SNiek Linnenbank INT_EN_TX_UNDERFLOW = (1 << 4), 9729d08975SNiek Linnenbank INT_EN_TX_TIMEOUT = (1 << 3), 9829d08975SNiek Linnenbank INT_EN_TX_BUF_UA = (1 << 2), 9929d08975SNiek Linnenbank INT_EN_TX_DMA_STOP = (1 << 1), 10029d08975SNiek Linnenbank INT_EN_TX = (1 << 0), 10129d08975SNiek Linnenbank }; 10229d08975SNiek Linnenbank 10329d08975SNiek Linnenbank enum { 10429d08975SNiek Linnenbank TX_CTL0_TX_EN = (1 << 31), 10529d08975SNiek Linnenbank TX_CTL1_TX_DMA_START = (1 << 31), 10629d08975SNiek Linnenbank TX_CTL1_TX_DMA_EN = (1 << 30), 10729d08975SNiek Linnenbank TX_CTL1_TX_FLUSH = (1 << 0), 10829d08975SNiek Linnenbank }; 10929d08975SNiek Linnenbank 11029d08975SNiek Linnenbank enum { 11129d08975SNiek Linnenbank RX_CTL0_RX_EN = (1 << 31), 11229d08975SNiek Linnenbank RX_CTL0_STRIP_FCS = (1 << 28), 11329d08975SNiek Linnenbank RX_CTL0_CRC_IPV4 = (1 << 27), 11429d08975SNiek Linnenbank }; 11529d08975SNiek Linnenbank 11629d08975SNiek Linnenbank enum { 11729d08975SNiek Linnenbank RX_CTL1_RX_DMA_START = (1 << 31), 11829d08975SNiek Linnenbank RX_CTL1_RX_DMA_EN = (1 << 30), 11929d08975SNiek Linnenbank RX_CTL1_RX_MD = (1 << 1), 12029d08975SNiek Linnenbank }; 12129d08975SNiek Linnenbank 12229d08975SNiek Linnenbank enum { 12329d08975SNiek Linnenbank RX_FRM_FLT_DIS_ADDR = (1 << 31), 12429d08975SNiek Linnenbank }; 12529d08975SNiek Linnenbank 12629d08975SNiek Linnenbank enum { 12729d08975SNiek Linnenbank MII_CMD_PHY_ADDR_SHIFT = (12), 12829d08975SNiek Linnenbank MII_CMD_PHY_ADDR_MASK = (0xf000), 12929d08975SNiek Linnenbank MII_CMD_PHY_REG_SHIFT = (4), 13029d08975SNiek Linnenbank MII_CMD_PHY_REG_MASK = (0xf0), 13129d08975SNiek Linnenbank MII_CMD_PHY_RW = (1 << 1), 13229d08975SNiek Linnenbank MII_CMD_PHY_BUSY = (1 << 0), 13329d08975SNiek Linnenbank }; 13429d08975SNiek Linnenbank 13529d08975SNiek Linnenbank enum { 13629d08975SNiek Linnenbank TX_DMA_STA_STOP = (0b000), 13729d08975SNiek Linnenbank TX_DMA_STA_RUN_FETCH = (0b001), 13829d08975SNiek Linnenbank TX_DMA_STA_WAIT_STA = (0b010), 13929d08975SNiek Linnenbank }; 14029d08975SNiek Linnenbank 14129d08975SNiek Linnenbank enum { 14229d08975SNiek Linnenbank RX_DMA_STA_STOP = (0b000), 14329d08975SNiek Linnenbank RX_DMA_STA_RUN_FETCH = (0b001), 14429d08975SNiek Linnenbank RX_DMA_STA_WAIT_FRM = (0b011), 14529d08975SNiek Linnenbank }; 14629d08975SNiek Linnenbank 14729d08975SNiek Linnenbank /* EMAC register reset values */ 14829d08975SNiek Linnenbank enum { 14929d08975SNiek Linnenbank REG_BASIC_CTL_1_RST = 0x08000000, 15029d08975SNiek Linnenbank }; 15129d08975SNiek Linnenbank 15229d08975SNiek Linnenbank /* EMAC constants */ 15329d08975SNiek Linnenbank enum { 15429d08975SNiek Linnenbank AW_SUN8I_EMAC_MIN_PKT_SZ = 64 15529d08975SNiek Linnenbank }; 15629d08975SNiek Linnenbank 15729d08975SNiek Linnenbank /* Transmit/receive frame descriptor */ 15829d08975SNiek Linnenbank typedef struct FrameDescriptor { 15929d08975SNiek Linnenbank uint32_t status; 16029d08975SNiek Linnenbank uint32_t status2; 16129d08975SNiek Linnenbank uint32_t addr; 16229d08975SNiek Linnenbank uint32_t next; 16329d08975SNiek Linnenbank } FrameDescriptor; 16429d08975SNiek Linnenbank 16529d08975SNiek Linnenbank /* Frame descriptor flags */ 16629d08975SNiek Linnenbank enum { 16729d08975SNiek Linnenbank DESC_STATUS_CTL = (1 << 31), 16829d08975SNiek Linnenbank DESC_STATUS2_BUF_SIZE_MASK = (0x7ff), 16929d08975SNiek Linnenbank }; 17029d08975SNiek Linnenbank 17129d08975SNiek Linnenbank /* Transmit frame descriptor flags */ 17229d08975SNiek Linnenbank enum { 17329d08975SNiek Linnenbank TX_DESC_STATUS_LENGTH_ERR = (1 << 14), 17429d08975SNiek Linnenbank TX_DESC_STATUS2_FIRST_DESC = (1 << 29), 17529d08975SNiek Linnenbank TX_DESC_STATUS2_LAST_DESC = (1 << 30), 17629d08975SNiek Linnenbank TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27), 17729d08975SNiek Linnenbank }; 17829d08975SNiek Linnenbank 17929d08975SNiek Linnenbank /* Receive frame descriptor flags */ 18029d08975SNiek Linnenbank enum { 18129d08975SNiek Linnenbank RX_DESC_STATUS_FIRST_DESC = (1 << 9), 18229d08975SNiek Linnenbank RX_DESC_STATUS_LAST_DESC = (1 << 8), 18329d08975SNiek Linnenbank RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000), 18429d08975SNiek Linnenbank RX_DESC_STATUS_FRM_LEN_SHIFT = (16), 18529d08975SNiek Linnenbank RX_DESC_STATUS_NO_BUF = (1 << 14), 18629d08975SNiek Linnenbank RX_DESC_STATUS_HEADER_ERR = (1 << 7), 18729d08975SNiek Linnenbank RX_DESC_STATUS_LENGTH_ERR = (1 << 4), 18829d08975SNiek Linnenbank RX_DESC_STATUS_CRC_ERR = (1 << 1), 18929d08975SNiek Linnenbank RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0), 19029d08975SNiek Linnenbank RX_DESC_STATUS2_RX_INT_CTL = (1 << 31), 19129d08975SNiek Linnenbank }; 19229d08975SNiek Linnenbank 19329d08975SNiek Linnenbank /* MII register offsets */ 19429d08975SNiek Linnenbank enum { 19529d08975SNiek Linnenbank MII_REG_CR = (0x0), /* Control */ 19629d08975SNiek Linnenbank MII_REG_ST = (0x1), /* Status */ 19729d08975SNiek Linnenbank MII_REG_ID_HIGH = (0x2), /* Identifier High */ 19829d08975SNiek Linnenbank MII_REG_ID_LOW = (0x3), /* Identifier Low */ 19929d08975SNiek Linnenbank MII_REG_ADV = (0x4), /* Advertised abilities */ 20029d08975SNiek Linnenbank MII_REG_LPA = (0x5), /* Link partner abilities */ 20129d08975SNiek Linnenbank }; 20229d08975SNiek Linnenbank 20329d08975SNiek Linnenbank /* MII register flags */ 20429d08975SNiek Linnenbank enum { 20529d08975SNiek Linnenbank MII_REG_CR_RESET = (1 << 15), 20629d08975SNiek Linnenbank MII_REG_CR_POWERDOWN = (1 << 11), 20729d08975SNiek Linnenbank MII_REG_CR_10Mbit = (0), 20829d08975SNiek Linnenbank MII_REG_CR_100Mbit = (1 << 13), 20929d08975SNiek Linnenbank MII_REG_CR_1000Mbit = (1 << 6), 21029d08975SNiek Linnenbank MII_REG_CR_AUTO_NEG = (1 << 12), 21129d08975SNiek Linnenbank MII_REG_CR_AUTO_NEG_RESTART = (1 << 9), 21229d08975SNiek Linnenbank MII_REG_CR_FULLDUPLEX = (1 << 8), 21329d08975SNiek Linnenbank }; 21429d08975SNiek Linnenbank 21529d08975SNiek Linnenbank enum { 21629d08975SNiek Linnenbank MII_REG_ST_100BASE_T4 = (1 << 15), 21729d08975SNiek Linnenbank MII_REG_ST_100BASE_X_FD = (1 << 14), 21829d08975SNiek Linnenbank MII_REG_ST_100BASE_X_HD = (1 << 13), 21929d08975SNiek Linnenbank MII_REG_ST_10_FD = (1 << 12), 22029d08975SNiek Linnenbank MII_REG_ST_10_HD = (1 << 11), 22129d08975SNiek Linnenbank MII_REG_ST_100BASE_T2_FD = (1 << 10), 22229d08975SNiek Linnenbank MII_REG_ST_100BASE_T2_HD = (1 << 9), 22329d08975SNiek Linnenbank MII_REG_ST_AUTONEG_COMPLETE = (1 << 5), 22429d08975SNiek Linnenbank MII_REG_ST_AUTONEG_AVAIL = (1 << 3), 22529d08975SNiek Linnenbank MII_REG_ST_LINK_UP = (1 << 2), 22629d08975SNiek Linnenbank }; 22729d08975SNiek Linnenbank 22829d08975SNiek Linnenbank enum { 22929d08975SNiek Linnenbank MII_REG_LPA_10_HD = (1 << 5), 23029d08975SNiek Linnenbank MII_REG_LPA_10_FD = (1 << 6), 23129d08975SNiek Linnenbank MII_REG_LPA_100_HD = (1 << 7), 23229d08975SNiek Linnenbank MII_REG_LPA_100_FD = (1 << 8), 23329d08975SNiek Linnenbank MII_REG_LPA_PAUSE = (1 << 10), 23429d08975SNiek Linnenbank MII_REG_LPA_ASYMPAUSE = (1 << 11), 23529d08975SNiek Linnenbank }; 23629d08975SNiek Linnenbank 23729d08975SNiek Linnenbank /* MII constants */ 23829d08975SNiek Linnenbank enum { 23929d08975SNiek Linnenbank MII_PHY_ID_HIGH = 0x0044, 24029d08975SNiek Linnenbank MII_PHY_ID_LOW = 0x1400, 24129d08975SNiek Linnenbank }; 24229d08975SNiek Linnenbank 24329d08975SNiek Linnenbank static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s, 24429d08975SNiek Linnenbank bool link_active) 24529d08975SNiek Linnenbank { 24629d08975SNiek Linnenbank if (link_active) { 24729d08975SNiek Linnenbank s->mii_st |= MII_REG_ST_LINK_UP; 24829d08975SNiek Linnenbank } else { 24929d08975SNiek Linnenbank s->mii_st &= ~MII_REG_ST_LINK_UP; 25029d08975SNiek Linnenbank } 25129d08975SNiek Linnenbank } 25229d08975SNiek Linnenbank 25329d08975SNiek Linnenbank static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s, 25429d08975SNiek Linnenbank bool link_active) 25529d08975SNiek Linnenbank { 25629d08975SNiek Linnenbank s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG | 25729d08975SNiek Linnenbank MII_REG_CR_FULLDUPLEX; 25829d08975SNiek Linnenbank s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD | 25929d08975SNiek Linnenbank MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD | 26029d08975SNiek Linnenbank MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD | 26129d08975SNiek Linnenbank MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL; 26229d08975SNiek Linnenbank s->mii_adv = 0; 26329d08975SNiek Linnenbank 26429d08975SNiek Linnenbank allwinner_sun8i_emac_mii_set_link(s, link_active); 26529d08975SNiek Linnenbank } 26629d08975SNiek Linnenbank 26729d08975SNiek Linnenbank static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s) 26829d08975SNiek Linnenbank { 26929d08975SNiek Linnenbank uint8_t addr, reg; 27029d08975SNiek Linnenbank 27129d08975SNiek Linnenbank addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT; 27229d08975SNiek Linnenbank reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT; 27329d08975SNiek Linnenbank 27429d08975SNiek Linnenbank if (addr != s->mii_phy_addr) { 27529d08975SNiek Linnenbank return; 27629d08975SNiek Linnenbank } 27729d08975SNiek Linnenbank 27829d08975SNiek Linnenbank /* Read or write a PHY register? */ 27929d08975SNiek Linnenbank if (s->mii_cmd & MII_CMD_PHY_RW) { 28029d08975SNiek Linnenbank trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data); 28129d08975SNiek Linnenbank 28229d08975SNiek Linnenbank switch (reg) { 28329d08975SNiek Linnenbank case MII_REG_CR: 28429d08975SNiek Linnenbank if (s->mii_data & MII_REG_CR_RESET) { 28529d08975SNiek Linnenbank allwinner_sun8i_emac_mii_reset(s, s->mii_st & 28629d08975SNiek Linnenbank MII_REG_ST_LINK_UP); 28729d08975SNiek Linnenbank } else { 28829d08975SNiek Linnenbank s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET | 28929d08975SNiek Linnenbank MII_REG_CR_AUTO_NEG_RESTART); 29029d08975SNiek Linnenbank } 29129d08975SNiek Linnenbank break; 29229d08975SNiek Linnenbank case MII_REG_ADV: 29329d08975SNiek Linnenbank s->mii_adv = s->mii_data; 29429d08975SNiek Linnenbank break; 29529d08975SNiek Linnenbank case MII_REG_ID_HIGH: 29629d08975SNiek Linnenbank case MII_REG_ID_LOW: 29729d08975SNiek Linnenbank case MII_REG_LPA: 29829d08975SNiek Linnenbank break; 29929d08975SNiek Linnenbank default: 30029d08975SNiek Linnenbank qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to " 30129d08975SNiek Linnenbank "unknown MII register 0x%x\n", reg); 30229d08975SNiek Linnenbank break; 30329d08975SNiek Linnenbank } 30429d08975SNiek Linnenbank } else { 30529d08975SNiek Linnenbank switch (reg) { 30629d08975SNiek Linnenbank case MII_REG_CR: 30729d08975SNiek Linnenbank s->mii_data = s->mii_cr; 30829d08975SNiek Linnenbank break; 30929d08975SNiek Linnenbank case MII_REG_ST: 31029d08975SNiek Linnenbank s->mii_data = s->mii_st; 31129d08975SNiek Linnenbank break; 31229d08975SNiek Linnenbank case MII_REG_ID_HIGH: 31329d08975SNiek Linnenbank s->mii_data = MII_PHY_ID_HIGH; 31429d08975SNiek Linnenbank break; 31529d08975SNiek Linnenbank case MII_REG_ID_LOW: 31629d08975SNiek Linnenbank s->mii_data = MII_PHY_ID_LOW; 31729d08975SNiek Linnenbank break; 31829d08975SNiek Linnenbank case MII_REG_ADV: 31929d08975SNiek Linnenbank s->mii_data = s->mii_adv; 32029d08975SNiek Linnenbank break; 32129d08975SNiek Linnenbank case MII_REG_LPA: 32229d08975SNiek Linnenbank s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD | 32329d08975SNiek Linnenbank MII_REG_LPA_100_HD | MII_REG_LPA_100_FD | 32429d08975SNiek Linnenbank MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE; 32529d08975SNiek Linnenbank break; 32629d08975SNiek Linnenbank default: 32729d08975SNiek Linnenbank qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to " 32829d08975SNiek Linnenbank "unknown MII register 0x%x\n", reg); 32929d08975SNiek Linnenbank s->mii_data = 0; 33029d08975SNiek Linnenbank break; 33129d08975SNiek Linnenbank } 33229d08975SNiek Linnenbank 33329d08975SNiek Linnenbank trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data); 33429d08975SNiek Linnenbank } 33529d08975SNiek Linnenbank } 33629d08975SNiek Linnenbank 33729d08975SNiek Linnenbank static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s) 33829d08975SNiek Linnenbank { 33929d08975SNiek Linnenbank qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0); 34029d08975SNiek Linnenbank } 34129d08975SNiek Linnenbank 342b6f03accSNiek Linnenbank static bool allwinner_sun8i_emac_desc_owned(FrameDescriptor *desc, 343b6f03accSNiek Linnenbank size_t min_buf_size) 34429d08975SNiek Linnenbank { 345b6f03accSNiek Linnenbank return (desc->status & DESC_STATUS_CTL) && (min_buf_size == 0 || 346b6f03accSNiek Linnenbank (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_buf_size); 34729d08975SNiek Linnenbank } 34829d08975SNiek Linnenbank 349b6f03accSNiek Linnenbank static void allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s, 350b6f03accSNiek Linnenbank FrameDescriptor *desc, 351b6f03accSNiek Linnenbank uint32_t phys_addr) 352b6f03accSNiek Linnenbank { 353a4ae17e5SPeter Maydell uint32_t desc_words[4]; 354a4ae17e5SPeter Maydell dma_memory_read(&s->dma_as, phys_addr, &desc_words, sizeof(desc_words), 355ba06fe8aSPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED); 356a4ae17e5SPeter Maydell desc->status = le32_to_cpu(desc_words[0]); 357a4ae17e5SPeter Maydell desc->status2 = le32_to_cpu(desc_words[1]); 358a4ae17e5SPeter Maydell desc->addr = le32_to_cpu(desc_words[2]); 359a4ae17e5SPeter Maydell desc->next = le32_to_cpu(desc_words[3]); 360b6f03accSNiek Linnenbank } 361b6f03accSNiek Linnenbank 362b6f03accSNiek Linnenbank static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s, 363b6f03accSNiek Linnenbank FrameDescriptor *desc) 364b6f03accSNiek Linnenbank { 365b6f03accSNiek Linnenbank const uint32_t nxt = desc->next; 366b6f03accSNiek Linnenbank allwinner_sun8i_emac_get_desc(s, desc, nxt); 367b6f03accSNiek Linnenbank return nxt; 368b6f03accSNiek Linnenbank } 369b6f03accSNiek Linnenbank 370b6f03accSNiek Linnenbank static uint32_t allwinner_sun8i_emac_find_desc(AwSun8iEmacState *s, 3714757cb85SPhilippe Mathieu-Daudé FrameDescriptor *desc, 37229d08975SNiek Linnenbank uint32_t start_addr, 37329d08975SNiek Linnenbank size_t min_size) 37429d08975SNiek Linnenbank { 37529d08975SNiek Linnenbank uint32_t desc_addr = start_addr; 37629d08975SNiek Linnenbank 37729d08975SNiek Linnenbank /* Note that the list is a cycle. Last entry points back to the head. */ 37829d08975SNiek Linnenbank while (desc_addr != 0) { 379b6f03accSNiek Linnenbank allwinner_sun8i_emac_get_desc(s, desc, desc_addr); 38029d08975SNiek Linnenbank 381b6f03accSNiek Linnenbank if (allwinner_sun8i_emac_desc_owned(desc, min_size)) { 38229d08975SNiek Linnenbank return desc_addr; 38329d08975SNiek Linnenbank } else if (desc->next == start_addr) { 38429d08975SNiek Linnenbank break; 38529d08975SNiek Linnenbank } else { 38629d08975SNiek Linnenbank desc_addr = desc->next; 38729d08975SNiek Linnenbank } 38829d08975SNiek Linnenbank } 38929d08975SNiek Linnenbank 39029d08975SNiek Linnenbank return 0; 39129d08975SNiek Linnenbank } 39229d08975SNiek Linnenbank 39329d08975SNiek Linnenbank static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s, 39429d08975SNiek Linnenbank FrameDescriptor *desc, 39529d08975SNiek Linnenbank size_t min_size) 39629d08975SNiek Linnenbank { 397b6f03accSNiek Linnenbank return allwinner_sun8i_emac_find_desc(s, desc, s->rx_desc_curr, min_size); 39829d08975SNiek Linnenbank } 39929d08975SNiek Linnenbank 40029d08975SNiek Linnenbank static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s, 401b6f03accSNiek Linnenbank FrameDescriptor *desc) 40229d08975SNiek Linnenbank { 403b6f03accSNiek Linnenbank allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_curr); 404b6f03accSNiek Linnenbank return s->tx_desc_curr; 40529d08975SNiek Linnenbank } 40629d08975SNiek Linnenbank 4074757cb85SPhilippe Mathieu-Daudé static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s, 408a4ae17e5SPeter Maydell const FrameDescriptor *desc, 40929d08975SNiek Linnenbank uint32_t phys_addr) 41029d08975SNiek Linnenbank { 411a4ae17e5SPeter Maydell uint32_t desc_words[4]; 412a4ae17e5SPeter Maydell desc_words[0] = cpu_to_le32(desc->status); 413a4ae17e5SPeter Maydell desc_words[1] = cpu_to_le32(desc->status2); 414a4ae17e5SPeter Maydell desc_words[2] = cpu_to_le32(desc->addr); 415a4ae17e5SPeter Maydell desc_words[3] = cpu_to_le32(desc->next); 416a4ae17e5SPeter Maydell dma_memory_write(&s->dma_as, phys_addr, &desc_words, sizeof(desc_words), 417ba06fe8aSPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED); 41829d08975SNiek Linnenbank } 41929d08975SNiek Linnenbank 420767cc9a9SPhilippe Mathieu-Daudé static bool allwinner_sun8i_emac_can_receive(NetClientState *nc) 42129d08975SNiek Linnenbank { 42229d08975SNiek Linnenbank AwSun8iEmacState *s = qemu_get_nic_opaque(nc); 42329d08975SNiek Linnenbank FrameDescriptor desc; 42429d08975SNiek Linnenbank 42529d08975SNiek Linnenbank return (s->rx_ctl0 & RX_CTL0_RX_EN) && 42629d08975SNiek Linnenbank (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0); 42729d08975SNiek Linnenbank } 42829d08975SNiek Linnenbank 42929d08975SNiek Linnenbank static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc, 43029d08975SNiek Linnenbank const uint8_t *buf, 43129d08975SNiek Linnenbank size_t size) 43229d08975SNiek Linnenbank { 43329d08975SNiek Linnenbank AwSun8iEmacState *s = qemu_get_nic_opaque(nc); 43429d08975SNiek Linnenbank FrameDescriptor desc; 43529d08975SNiek Linnenbank size_t bytes_left = size; 43629d08975SNiek Linnenbank size_t desc_bytes = 0; 43729d08975SNiek Linnenbank size_t pad_fcs_size = 4; 43829d08975SNiek Linnenbank size_t padding = 0; 43929d08975SNiek Linnenbank 44029d08975SNiek Linnenbank if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) { 44129d08975SNiek Linnenbank return -1; 44229d08975SNiek Linnenbank } 44329d08975SNiek Linnenbank 44429d08975SNiek Linnenbank s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc, 44529d08975SNiek Linnenbank AW_SUN8I_EMAC_MIN_PKT_SZ); 44629d08975SNiek Linnenbank if (!s->rx_desc_curr) { 44729d08975SNiek Linnenbank s->int_sta |= INT_STA_RX_BUF_UA; 44829d08975SNiek Linnenbank } 44929d08975SNiek Linnenbank 45029d08975SNiek Linnenbank /* Keep filling RX descriptors until the whole frame is written */ 45129d08975SNiek Linnenbank while (s->rx_desc_curr && bytes_left > 0) { 45229d08975SNiek Linnenbank desc.status &= ~DESC_STATUS_CTL; 45329d08975SNiek Linnenbank desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK; 45429d08975SNiek Linnenbank 45529d08975SNiek Linnenbank if (bytes_left == size) { 45629d08975SNiek Linnenbank desc.status |= RX_DESC_STATUS_FIRST_DESC; 45729d08975SNiek Linnenbank } 45829d08975SNiek Linnenbank 45929d08975SNiek Linnenbank if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) < 46029d08975SNiek Linnenbank (bytes_left + pad_fcs_size)) { 46129d08975SNiek Linnenbank desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; 46229d08975SNiek Linnenbank desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT; 46329d08975SNiek Linnenbank } else { 46429d08975SNiek Linnenbank padding = pad_fcs_size; 46529d08975SNiek Linnenbank if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) { 46629d08975SNiek Linnenbank padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left); 46729d08975SNiek Linnenbank } 46829d08975SNiek Linnenbank 46929d08975SNiek Linnenbank desc_bytes = (bytes_left); 47029d08975SNiek Linnenbank desc.status |= RX_DESC_STATUS_LAST_DESC; 47129d08975SNiek Linnenbank desc.status |= (bytes_left + padding) 47229d08975SNiek Linnenbank << RX_DESC_STATUS_FRM_LEN_SHIFT; 47329d08975SNiek Linnenbank } 47429d08975SNiek Linnenbank 475ba06fe8aSPhilippe Mathieu-Daudé dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes, 476ba06fe8aSPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED); 4774757cb85SPhilippe Mathieu-Daudé allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr); 47829d08975SNiek Linnenbank trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr, 47929d08975SNiek Linnenbank desc_bytes); 48029d08975SNiek Linnenbank 48129d08975SNiek Linnenbank /* Check if frame needs to raise the receive interrupt */ 48229d08975SNiek Linnenbank if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) { 48329d08975SNiek Linnenbank s->int_sta |= INT_STA_RX; 48429d08975SNiek Linnenbank } 48529d08975SNiek Linnenbank 48629d08975SNiek Linnenbank /* Increment variables */ 48729d08975SNiek Linnenbank buf += desc_bytes; 48829d08975SNiek Linnenbank bytes_left -= desc_bytes; 48929d08975SNiek Linnenbank 49029d08975SNiek Linnenbank /* Move to the next descriptor */ 491b6f03accSNiek Linnenbank s->rx_desc_curr = allwinner_sun8i_emac_find_desc(s, &desc, desc.next, 492b6f03accSNiek Linnenbank AW_SUN8I_EMAC_MIN_PKT_SZ); 49329d08975SNiek Linnenbank if (!s->rx_desc_curr) { 49429d08975SNiek Linnenbank /* Not enough buffer space available */ 49529d08975SNiek Linnenbank s->int_sta |= INT_STA_RX_BUF_UA; 49629d08975SNiek Linnenbank s->rx_desc_curr = s->rx_desc_head; 49729d08975SNiek Linnenbank break; 49829d08975SNiek Linnenbank } 49929d08975SNiek Linnenbank } 50029d08975SNiek Linnenbank 50129d08975SNiek Linnenbank /* Report receive DMA is finished */ 50229d08975SNiek Linnenbank s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START; 50329d08975SNiek Linnenbank allwinner_sun8i_emac_update_irq(s); 50429d08975SNiek Linnenbank 50529d08975SNiek Linnenbank return size; 50629d08975SNiek Linnenbank } 50729d08975SNiek Linnenbank 50829d08975SNiek Linnenbank static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s) 50929d08975SNiek Linnenbank { 51029d08975SNiek Linnenbank NetClientState *nc = qemu_get_queue(s->nic); 51129d08975SNiek Linnenbank FrameDescriptor desc; 51229d08975SNiek Linnenbank size_t bytes = 0; 51329d08975SNiek Linnenbank size_t packet_bytes = 0; 51429d08975SNiek Linnenbank size_t transmitted = 0; 51529d08975SNiek Linnenbank static uint8_t packet_buf[2048]; 51629d08975SNiek Linnenbank 517b6f03accSNiek Linnenbank s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc); 51829d08975SNiek Linnenbank 51929d08975SNiek Linnenbank /* Read all transmit descriptors */ 520b6f03accSNiek Linnenbank while (allwinner_sun8i_emac_desc_owned(&desc, 0)) { 52129d08975SNiek Linnenbank 52229d08975SNiek Linnenbank /* Read from physical memory into packet buffer */ 52329d08975SNiek Linnenbank bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; 52429d08975SNiek Linnenbank if (bytes + packet_bytes > sizeof(packet_buf)) { 52529d08975SNiek Linnenbank desc.status |= TX_DESC_STATUS_LENGTH_ERR; 52629d08975SNiek Linnenbank break; 52729d08975SNiek Linnenbank } 528ba06fe8aSPhilippe Mathieu-Daudé dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, 529ba06fe8aSPhilippe Mathieu-Daudé bytes, MEMTXATTRS_UNSPECIFIED); 53029d08975SNiek Linnenbank packet_bytes += bytes; 53129d08975SNiek Linnenbank desc.status &= ~DESC_STATUS_CTL; 5324757cb85SPhilippe Mathieu-Daudé allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr); 53329d08975SNiek Linnenbank 53429d08975SNiek Linnenbank /* After the last descriptor, send the packet */ 53529d08975SNiek Linnenbank if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) { 53629d08975SNiek Linnenbank if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) { 537f5746335SBin Meng net_checksum_calculate(packet_buf, packet_bytes, CSUM_ALL); 53829d08975SNiek Linnenbank } 53929d08975SNiek Linnenbank 54029d08975SNiek Linnenbank qemu_send_packet(nc, packet_buf, packet_bytes); 54129d08975SNiek Linnenbank trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr, 54229d08975SNiek Linnenbank bytes); 54329d08975SNiek Linnenbank 54429d08975SNiek Linnenbank packet_bytes = 0; 54529d08975SNiek Linnenbank transmitted++; 54629d08975SNiek Linnenbank } 547b6f03accSNiek Linnenbank s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc); 54829d08975SNiek Linnenbank } 54929d08975SNiek Linnenbank 55029d08975SNiek Linnenbank /* Raise transmit completed interrupt */ 55129d08975SNiek Linnenbank if (transmitted > 0) { 55229d08975SNiek Linnenbank s->int_sta |= INT_STA_TX; 55329d08975SNiek Linnenbank s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START; 55429d08975SNiek Linnenbank allwinner_sun8i_emac_update_irq(s); 55529d08975SNiek Linnenbank } 55629d08975SNiek Linnenbank } 55729d08975SNiek Linnenbank 55829d08975SNiek Linnenbank static void allwinner_sun8i_emac_reset(DeviceState *dev) 55929d08975SNiek Linnenbank { 56029d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(dev); 56129d08975SNiek Linnenbank NetClientState *nc = qemu_get_queue(s->nic); 56229d08975SNiek Linnenbank 56329d08975SNiek Linnenbank trace_allwinner_sun8i_emac_reset(); 56429d08975SNiek Linnenbank 56529d08975SNiek Linnenbank s->mii_cmd = 0; 56629d08975SNiek Linnenbank s->mii_data = 0; 56729d08975SNiek Linnenbank s->basic_ctl0 = 0; 56829d08975SNiek Linnenbank s->basic_ctl1 = REG_BASIC_CTL_1_RST; 56929d08975SNiek Linnenbank s->int_en = 0; 57029d08975SNiek Linnenbank s->int_sta = 0; 57129d08975SNiek Linnenbank s->frm_flt = 0; 57229d08975SNiek Linnenbank s->rx_ctl0 = 0; 57329d08975SNiek Linnenbank s->rx_ctl1 = RX_CTL1_RX_MD; 57429d08975SNiek Linnenbank s->rx_desc_head = 0; 57529d08975SNiek Linnenbank s->rx_desc_curr = 0; 57629d08975SNiek Linnenbank s->tx_ctl0 = 0; 57729d08975SNiek Linnenbank s->tx_ctl1 = 0; 57829d08975SNiek Linnenbank s->tx_desc_head = 0; 57929d08975SNiek Linnenbank s->tx_desc_curr = 0; 58029d08975SNiek Linnenbank s->tx_flowctl = 0; 58129d08975SNiek Linnenbank 58229d08975SNiek Linnenbank allwinner_sun8i_emac_mii_reset(s, !nc->link_down); 58329d08975SNiek Linnenbank } 58429d08975SNiek Linnenbank 58529d08975SNiek Linnenbank static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset, 58629d08975SNiek Linnenbank unsigned size) 58729d08975SNiek Linnenbank { 58829d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque); 58929d08975SNiek Linnenbank uint64_t value = 0; 59029d08975SNiek Linnenbank FrameDescriptor desc; 59129d08975SNiek Linnenbank 59229d08975SNiek Linnenbank switch (offset) { 59329d08975SNiek Linnenbank case REG_BASIC_CTL_0: /* Basic Control 0 */ 59429d08975SNiek Linnenbank value = s->basic_ctl0; 59529d08975SNiek Linnenbank break; 59629d08975SNiek Linnenbank case REG_BASIC_CTL_1: /* Basic Control 1 */ 59729d08975SNiek Linnenbank value = s->basic_ctl1; 59829d08975SNiek Linnenbank break; 59929d08975SNiek Linnenbank case REG_INT_STA: /* Interrupt Status */ 60029d08975SNiek Linnenbank value = s->int_sta; 60129d08975SNiek Linnenbank break; 602cba42d61SMichael Tokarev case REG_INT_EN: /* Interrupt Enable */ 60329d08975SNiek Linnenbank value = s->int_en; 60429d08975SNiek Linnenbank break; 60529d08975SNiek Linnenbank case REG_TX_CTL_0: /* Transmit Control 0 */ 60629d08975SNiek Linnenbank value = s->tx_ctl0; 60729d08975SNiek Linnenbank break; 60829d08975SNiek Linnenbank case REG_TX_CTL_1: /* Transmit Control 1 */ 60929d08975SNiek Linnenbank value = s->tx_ctl1; 61029d08975SNiek Linnenbank break; 61129d08975SNiek Linnenbank case REG_TX_FLOW_CTL: /* Transmit Flow Control */ 61229d08975SNiek Linnenbank value = s->tx_flowctl; 61329d08975SNiek Linnenbank break; 61429d08975SNiek Linnenbank case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ 61529d08975SNiek Linnenbank value = s->tx_desc_head; 61629d08975SNiek Linnenbank break; 61729d08975SNiek Linnenbank case REG_RX_CTL_0: /* Receive Control 0 */ 61829d08975SNiek Linnenbank value = s->rx_ctl0; 61929d08975SNiek Linnenbank break; 62029d08975SNiek Linnenbank case REG_RX_CTL_1: /* Receive Control 1 */ 62129d08975SNiek Linnenbank value = s->rx_ctl1; 62229d08975SNiek Linnenbank break; 62329d08975SNiek Linnenbank case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ 62429d08975SNiek Linnenbank value = s->rx_desc_head; 62529d08975SNiek Linnenbank break; 62629d08975SNiek Linnenbank case REG_FRM_FLT: /* Receive Frame Filter */ 62729d08975SNiek Linnenbank value = s->frm_flt; 62829d08975SNiek Linnenbank break; 62929d08975SNiek Linnenbank case REG_RX_HASH_0: /* Receive Hash Table 0 */ 63029d08975SNiek Linnenbank case REG_RX_HASH_1: /* Receive Hash Table 1 */ 63129d08975SNiek Linnenbank break; 63229d08975SNiek Linnenbank case REG_MII_CMD: /* Management Interface Command */ 63329d08975SNiek Linnenbank value = s->mii_cmd; 63429d08975SNiek Linnenbank break; 63529d08975SNiek Linnenbank case REG_MII_DATA: /* Management Interface Data */ 63629d08975SNiek Linnenbank value = s->mii_data; 63729d08975SNiek Linnenbank break; 63829d08975SNiek Linnenbank case REG_ADDR_HIGH: /* MAC Address High */ 639b88fb124SPeter Maydell value = lduw_le_p(s->conf.macaddr.a + 4); 64029d08975SNiek Linnenbank break; 64129d08975SNiek Linnenbank case REG_ADDR_LOW: /* MAC Address Low */ 642b88fb124SPeter Maydell value = ldl_le_p(s->conf.macaddr.a); 64329d08975SNiek Linnenbank break; 64429d08975SNiek Linnenbank case REG_TX_DMA_STA: /* Transmit DMA Status */ 64529d08975SNiek Linnenbank break; 64629d08975SNiek Linnenbank case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ 64729d08975SNiek Linnenbank value = s->tx_desc_curr; 64829d08975SNiek Linnenbank break; 64929d08975SNiek Linnenbank case REG_TX_CUR_BUF: /* Transmit Current Buffer */ 65029d08975SNiek Linnenbank if (s->tx_desc_curr != 0) { 651a4ae17e5SPeter Maydell allwinner_sun8i_emac_get_desc(s, &desc, s->tx_desc_curr); 65229d08975SNiek Linnenbank value = desc.addr; 65329d08975SNiek Linnenbank } else { 65429d08975SNiek Linnenbank value = 0; 65529d08975SNiek Linnenbank } 65629d08975SNiek Linnenbank break; 65729d08975SNiek Linnenbank case REG_RX_DMA_STA: /* Receive DMA Status */ 65829d08975SNiek Linnenbank break; 65929d08975SNiek Linnenbank case REG_RX_CUR_DESC: /* Receive Current Descriptor */ 66029d08975SNiek Linnenbank value = s->rx_desc_curr; 66129d08975SNiek Linnenbank break; 66229d08975SNiek Linnenbank case REG_RX_CUR_BUF: /* Receive Current Buffer */ 66329d08975SNiek Linnenbank if (s->rx_desc_curr != 0) { 664a4ae17e5SPeter Maydell allwinner_sun8i_emac_get_desc(s, &desc, s->rx_desc_curr); 66529d08975SNiek Linnenbank value = desc.addr; 66629d08975SNiek Linnenbank } else { 66729d08975SNiek Linnenbank value = 0; 66829d08975SNiek Linnenbank } 66929d08975SNiek Linnenbank break; 67029d08975SNiek Linnenbank case REG_RGMII_STA: /* RGMII Status */ 67129d08975SNiek Linnenbank break; 67229d08975SNiek Linnenbank default: 67329d08975SNiek Linnenbank qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown " 674883f2c59SPhilippe Mathieu-Daudé "EMAC register 0x" HWADDR_FMT_plx "\n", 67529d08975SNiek Linnenbank offset); 67629d08975SNiek Linnenbank } 67729d08975SNiek Linnenbank 67829d08975SNiek Linnenbank trace_allwinner_sun8i_emac_read(offset, value); 67929d08975SNiek Linnenbank return value; 68029d08975SNiek Linnenbank } 68129d08975SNiek Linnenbank 68229d08975SNiek Linnenbank static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset, 68329d08975SNiek Linnenbank uint64_t value, unsigned size) 68429d08975SNiek Linnenbank { 68529d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque); 68629d08975SNiek Linnenbank NetClientState *nc = qemu_get_queue(s->nic); 68729d08975SNiek Linnenbank 68829d08975SNiek Linnenbank trace_allwinner_sun8i_emac_write(offset, value); 68929d08975SNiek Linnenbank 69029d08975SNiek Linnenbank switch (offset) { 69129d08975SNiek Linnenbank case REG_BASIC_CTL_0: /* Basic Control 0 */ 69229d08975SNiek Linnenbank s->basic_ctl0 = value; 69329d08975SNiek Linnenbank break; 69429d08975SNiek Linnenbank case REG_BASIC_CTL_1: /* Basic Control 1 */ 69529d08975SNiek Linnenbank if (value & BASIC_CTL1_SOFTRST) { 69629d08975SNiek Linnenbank allwinner_sun8i_emac_reset(DEVICE(s)); 69729d08975SNiek Linnenbank value &= ~BASIC_CTL1_SOFTRST; 69829d08975SNiek Linnenbank } 69929d08975SNiek Linnenbank s->basic_ctl1 = value; 70029d08975SNiek Linnenbank if (allwinner_sun8i_emac_can_receive(nc)) { 70129d08975SNiek Linnenbank qemu_flush_queued_packets(nc); 70229d08975SNiek Linnenbank } 70329d08975SNiek Linnenbank break; 70429d08975SNiek Linnenbank case REG_INT_STA: /* Interrupt Status */ 70529d08975SNiek Linnenbank s->int_sta &= ~value; 70629d08975SNiek Linnenbank allwinner_sun8i_emac_update_irq(s); 70729d08975SNiek Linnenbank break; 70829d08975SNiek Linnenbank case REG_INT_EN: /* Interrupt Enable */ 70929d08975SNiek Linnenbank s->int_en = value; 71029d08975SNiek Linnenbank allwinner_sun8i_emac_update_irq(s); 71129d08975SNiek Linnenbank break; 71229d08975SNiek Linnenbank case REG_TX_CTL_0: /* Transmit Control 0 */ 71329d08975SNiek Linnenbank s->tx_ctl0 = value; 71429d08975SNiek Linnenbank break; 71529d08975SNiek Linnenbank case REG_TX_CTL_1: /* Transmit Control 1 */ 71629d08975SNiek Linnenbank s->tx_ctl1 = value; 71729d08975SNiek Linnenbank if (value & TX_CTL1_TX_DMA_EN) { 71829d08975SNiek Linnenbank allwinner_sun8i_emac_transmit(s); 71929d08975SNiek Linnenbank } 72029d08975SNiek Linnenbank break; 72129d08975SNiek Linnenbank case REG_TX_FLOW_CTL: /* Transmit Flow Control */ 72229d08975SNiek Linnenbank s->tx_flowctl = value; 72329d08975SNiek Linnenbank break; 72429d08975SNiek Linnenbank case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ 72529d08975SNiek Linnenbank s->tx_desc_head = value; 72629d08975SNiek Linnenbank s->tx_desc_curr = value; 72729d08975SNiek Linnenbank break; 72829d08975SNiek Linnenbank case REG_RX_CTL_0: /* Receive Control 0 */ 72929d08975SNiek Linnenbank s->rx_ctl0 = value; 73029d08975SNiek Linnenbank break; 73129d08975SNiek Linnenbank case REG_RX_CTL_1: /* Receive Control 1 */ 73229d08975SNiek Linnenbank s->rx_ctl1 = value | RX_CTL1_RX_MD; 73329d08975SNiek Linnenbank if ((value & RX_CTL1_RX_DMA_EN) && 73429d08975SNiek Linnenbank allwinner_sun8i_emac_can_receive(nc)) { 73529d08975SNiek Linnenbank qemu_flush_queued_packets(nc); 73629d08975SNiek Linnenbank } 73729d08975SNiek Linnenbank break; 73829d08975SNiek Linnenbank case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ 73929d08975SNiek Linnenbank s->rx_desc_head = value; 74029d08975SNiek Linnenbank s->rx_desc_curr = value; 74129d08975SNiek Linnenbank break; 74229d08975SNiek Linnenbank case REG_FRM_FLT: /* Receive Frame Filter */ 74329d08975SNiek Linnenbank s->frm_flt = value; 74429d08975SNiek Linnenbank break; 74529d08975SNiek Linnenbank case REG_RX_HASH_0: /* Receive Hash Table 0 */ 74629d08975SNiek Linnenbank case REG_RX_HASH_1: /* Receive Hash Table 1 */ 74729d08975SNiek Linnenbank break; 74829d08975SNiek Linnenbank case REG_MII_CMD: /* Management Interface Command */ 74929d08975SNiek Linnenbank s->mii_cmd = value & ~MII_CMD_PHY_BUSY; 75029d08975SNiek Linnenbank allwinner_sun8i_emac_mii_cmd(s); 75129d08975SNiek Linnenbank break; 75229d08975SNiek Linnenbank case REG_MII_DATA: /* Management Interface Data */ 75329d08975SNiek Linnenbank s->mii_data = value; 75429d08975SNiek Linnenbank break; 75529d08975SNiek Linnenbank case REG_ADDR_HIGH: /* MAC Address High */ 756b88fb124SPeter Maydell stw_le_p(s->conf.macaddr.a + 4, value); 75729d08975SNiek Linnenbank break; 75829d08975SNiek Linnenbank case REG_ADDR_LOW: /* MAC Address Low */ 759b88fb124SPeter Maydell stl_le_p(s->conf.macaddr.a, value); 76029d08975SNiek Linnenbank break; 76129d08975SNiek Linnenbank case REG_TX_DMA_STA: /* Transmit DMA Status */ 76229d08975SNiek Linnenbank case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ 76329d08975SNiek Linnenbank case REG_TX_CUR_BUF: /* Transmit Current Buffer */ 76429d08975SNiek Linnenbank case REG_RX_DMA_STA: /* Receive DMA Status */ 76529d08975SNiek Linnenbank case REG_RX_CUR_DESC: /* Receive Current Descriptor */ 76629d08975SNiek Linnenbank case REG_RX_CUR_BUF: /* Receive Current Buffer */ 76729d08975SNiek Linnenbank case REG_RGMII_STA: /* RGMII Status */ 76829d08975SNiek Linnenbank break; 76929d08975SNiek Linnenbank default: 77029d08975SNiek Linnenbank qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown " 771883f2c59SPhilippe Mathieu-Daudé "EMAC register 0x" HWADDR_FMT_plx "\n", 77229d08975SNiek Linnenbank offset); 77329d08975SNiek Linnenbank } 77429d08975SNiek Linnenbank } 77529d08975SNiek Linnenbank 77629d08975SNiek Linnenbank static void allwinner_sun8i_emac_set_link(NetClientState *nc) 77729d08975SNiek Linnenbank { 77829d08975SNiek Linnenbank AwSun8iEmacState *s = qemu_get_nic_opaque(nc); 77929d08975SNiek Linnenbank 78029d08975SNiek Linnenbank trace_allwinner_sun8i_emac_set_link(!nc->link_down); 78129d08975SNiek Linnenbank allwinner_sun8i_emac_mii_set_link(s, !nc->link_down); 78229d08975SNiek Linnenbank } 78329d08975SNiek Linnenbank 78429d08975SNiek Linnenbank static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = { 78529d08975SNiek Linnenbank .read = allwinner_sun8i_emac_read, 78629d08975SNiek Linnenbank .write = allwinner_sun8i_emac_write, 78729d08975SNiek Linnenbank .endianness = DEVICE_NATIVE_ENDIAN, 78829d08975SNiek Linnenbank .valid = { 78929d08975SNiek Linnenbank .min_access_size = 4, 79029d08975SNiek Linnenbank .max_access_size = 4, 79129d08975SNiek Linnenbank }, 79229d08975SNiek Linnenbank .impl.min_access_size = 4, 79329d08975SNiek Linnenbank }; 79429d08975SNiek Linnenbank 79529d08975SNiek Linnenbank static NetClientInfo net_allwinner_sun8i_emac_info = { 79629d08975SNiek Linnenbank .type = NET_CLIENT_DRIVER_NIC, 79729d08975SNiek Linnenbank .size = sizeof(NICState), 79829d08975SNiek Linnenbank .can_receive = allwinner_sun8i_emac_can_receive, 79929d08975SNiek Linnenbank .receive = allwinner_sun8i_emac_receive, 80029d08975SNiek Linnenbank .link_status_changed = allwinner_sun8i_emac_set_link, 80129d08975SNiek Linnenbank }; 80229d08975SNiek Linnenbank 80329d08975SNiek Linnenbank static void allwinner_sun8i_emac_init(Object *obj) 80429d08975SNiek Linnenbank { 80529d08975SNiek Linnenbank SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 80629d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(obj); 80729d08975SNiek Linnenbank 80829d08975SNiek Linnenbank memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops, 80929d08975SNiek Linnenbank s, TYPE_AW_SUN8I_EMAC, 64 * KiB); 81029d08975SNiek Linnenbank sysbus_init_mmio(sbd, &s->iomem); 81129d08975SNiek Linnenbank sysbus_init_irq(sbd, &s->irq); 81229d08975SNiek Linnenbank } 81329d08975SNiek Linnenbank 81429d08975SNiek Linnenbank static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp) 81529d08975SNiek Linnenbank { 81629d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(dev); 81729d08975SNiek Linnenbank 8184757cb85SPhilippe Mathieu-Daudé if (!s->dma_mr) { 8194757cb85SPhilippe Mathieu-Daudé error_setg(errp, TYPE_AW_SUN8I_EMAC " 'dma-memory' link not set"); 8204757cb85SPhilippe Mathieu-Daudé return; 8214757cb85SPhilippe Mathieu-Daudé } 8224757cb85SPhilippe Mathieu-Daudé 8234757cb85SPhilippe Mathieu-Daudé address_space_init(&s->dma_as, s->dma_mr, "emac-dma"); 8244757cb85SPhilippe Mathieu-Daudé 82529d08975SNiek Linnenbank qemu_macaddr_default_if_unset(&s->conf.macaddr); 82629d08975SNiek Linnenbank s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf, 827*7d0fefdfSAkihiko Odaki object_get_typename(OBJECT(dev)), dev->id, 828*7d0fefdfSAkihiko Odaki &dev->mem_reentrancy_guard, s); 82929d08975SNiek Linnenbank qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 83029d08975SNiek Linnenbank } 83129d08975SNiek Linnenbank 83229d08975SNiek Linnenbank static Property allwinner_sun8i_emac_properties[] = { 83329d08975SNiek Linnenbank DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf), 83429d08975SNiek Linnenbank DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0), 8354757cb85SPhilippe Mathieu-Daudé DEFINE_PROP_LINK("dma-memory", AwSun8iEmacState, dma_mr, 8364757cb85SPhilippe Mathieu-Daudé TYPE_MEMORY_REGION, MemoryRegion *), 83729d08975SNiek Linnenbank DEFINE_PROP_END_OF_LIST(), 83829d08975SNiek Linnenbank }; 83929d08975SNiek Linnenbank 84029d08975SNiek Linnenbank static int allwinner_sun8i_emac_post_load(void *opaque, int version_id) 84129d08975SNiek Linnenbank { 84229d08975SNiek Linnenbank AwSun8iEmacState *s = opaque; 84329d08975SNiek Linnenbank 84429d08975SNiek Linnenbank allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic)); 84529d08975SNiek Linnenbank 84629d08975SNiek Linnenbank return 0; 84729d08975SNiek Linnenbank } 84829d08975SNiek Linnenbank 84929d08975SNiek Linnenbank static const VMStateDescription vmstate_aw_emac = { 85029d08975SNiek Linnenbank .name = "allwinner-sun8i-emac", 85129d08975SNiek Linnenbank .version_id = 1, 85229d08975SNiek Linnenbank .minimum_version_id = 1, 85329d08975SNiek Linnenbank .post_load = allwinner_sun8i_emac_post_load, 85429d08975SNiek Linnenbank .fields = (VMStateField[]) { 85529d08975SNiek Linnenbank VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState), 85629d08975SNiek Linnenbank VMSTATE_UINT32(mii_cmd, AwSun8iEmacState), 85729d08975SNiek Linnenbank VMSTATE_UINT32(mii_data, AwSun8iEmacState), 85829d08975SNiek Linnenbank VMSTATE_UINT32(mii_cr, AwSun8iEmacState), 85929d08975SNiek Linnenbank VMSTATE_UINT32(mii_st, AwSun8iEmacState), 86029d08975SNiek Linnenbank VMSTATE_UINT32(mii_adv, AwSun8iEmacState), 86129d08975SNiek Linnenbank VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState), 86229d08975SNiek Linnenbank VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState), 86329d08975SNiek Linnenbank VMSTATE_UINT32(int_en, AwSun8iEmacState), 86429d08975SNiek Linnenbank VMSTATE_UINT32(int_sta, AwSun8iEmacState), 86529d08975SNiek Linnenbank VMSTATE_UINT32(frm_flt, AwSun8iEmacState), 86629d08975SNiek Linnenbank VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState), 86729d08975SNiek Linnenbank VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState), 86829d08975SNiek Linnenbank VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState), 86929d08975SNiek Linnenbank VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState), 87029d08975SNiek Linnenbank VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState), 87129d08975SNiek Linnenbank VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState), 87229d08975SNiek Linnenbank VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState), 87329d08975SNiek Linnenbank VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState), 87429d08975SNiek Linnenbank VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState), 87529d08975SNiek Linnenbank VMSTATE_END_OF_LIST() 87629d08975SNiek Linnenbank } 87729d08975SNiek Linnenbank }; 87829d08975SNiek Linnenbank 87929d08975SNiek Linnenbank static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data) 88029d08975SNiek Linnenbank { 88129d08975SNiek Linnenbank DeviceClass *dc = DEVICE_CLASS(klass); 88229d08975SNiek Linnenbank 88329d08975SNiek Linnenbank dc->realize = allwinner_sun8i_emac_realize; 88429d08975SNiek Linnenbank dc->reset = allwinner_sun8i_emac_reset; 88529d08975SNiek Linnenbank dc->vmsd = &vmstate_aw_emac; 88629d08975SNiek Linnenbank device_class_set_props(dc, allwinner_sun8i_emac_properties); 88729d08975SNiek Linnenbank } 88829d08975SNiek Linnenbank 88929d08975SNiek Linnenbank static const TypeInfo allwinner_sun8i_emac_info = { 89029d08975SNiek Linnenbank .name = TYPE_AW_SUN8I_EMAC, 89129d08975SNiek Linnenbank .parent = TYPE_SYS_BUS_DEVICE, 89229d08975SNiek Linnenbank .instance_size = sizeof(AwSun8iEmacState), 89329d08975SNiek Linnenbank .instance_init = allwinner_sun8i_emac_init, 89429d08975SNiek Linnenbank .class_init = allwinner_sun8i_emac_class_init, 89529d08975SNiek Linnenbank }; 89629d08975SNiek Linnenbank 89729d08975SNiek Linnenbank static void allwinner_sun8i_emac_register_types(void) 89829d08975SNiek Linnenbank { 89929d08975SNiek Linnenbank type_register_static(&allwinner_sun8i_emac_info); 90029d08975SNiek Linnenbank } 90129d08975SNiek Linnenbank 90229d08975SNiek Linnenbank type_init(allwinner_sun8i_emac_register_types) 903