129d08975SNiek Linnenbank /* 229d08975SNiek Linnenbank * Allwinner Sun8i Ethernet MAC emulation 329d08975SNiek Linnenbank * 429d08975SNiek Linnenbank * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 529d08975SNiek Linnenbank * 629d08975SNiek Linnenbank * This program is free software: you can redistribute it and/or modify 729d08975SNiek Linnenbank * it under the terms of the GNU General Public License as published by 829d08975SNiek Linnenbank * the Free Software Foundation, either version 2 of the License, or 929d08975SNiek Linnenbank * (at your option) any later version. 1029d08975SNiek Linnenbank * 1129d08975SNiek Linnenbank * This program is distributed in the hope that it will be useful, 1229d08975SNiek Linnenbank * but WITHOUT ANY WARRANTY; without even the implied warranty of 1329d08975SNiek Linnenbank * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1429d08975SNiek Linnenbank * GNU General Public License for more details. 1529d08975SNiek Linnenbank * 1629d08975SNiek Linnenbank * You should have received a copy of the GNU General Public License 1729d08975SNiek Linnenbank * along with this program. If not, see <http://www.gnu.org/licenses/>. 1829d08975SNiek Linnenbank */ 1929d08975SNiek Linnenbank 2029d08975SNiek Linnenbank #include "qemu/osdep.h" 2129d08975SNiek Linnenbank #include "qemu/units.h" 2229d08975SNiek Linnenbank #include "hw/sysbus.h" 2329d08975SNiek Linnenbank #include "migration/vmstate.h" 2429d08975SNiek Linnenbank #include "net/net.h" 2529d08975SNiek Linnenbank #include "hw/irq.h" 2629d08975SNiek Linnenbank #include "hw/qdev-properties.h" 2729d08975SNiek Linnenbank #include "qemu/log.h" 2829d08975SNiek Linnenbank #include "trace.h" 2929d08975SNiek Linnenbank #include "net/checksum.h" 3029d08975SNiek Linnenbank #include "qemu/module.h" 3129d08975SNiek Linnenbank #include "exec/cpu-common.h" 3229d08975SNiek Linnenbank #include "hw/net/allwinner-sun8i-emac.h" 3329d08975SNiek Linnenbank 3429d08975SNiek Linnenbank /* EMAC register offsets */ 3529d08975SNiek Linnenbank enum { 3629d08975SNiek Linnenbank REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */ 3729d08975SNiek Linnenbank REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */ 3829d08975SNiek Linnenbank REG_INT_STA = 0x0008, /* Interrupt Status */ 3929d08975SNiek Linnenbank REG_INT_EN = 0x000C, /* Interrupt Enable */ 4029d08975SNiek Linnenbank REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */ 4129d08975SNiek Linnenbank REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */ 4229d08975SNiek Linnenbank REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */ 4329d08975SNiek Linnenbank REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */ 4429d08975SNiek Linnenbank REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */ 4529d08975SNiek Linnenbank REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */ 4629d08975SNiek Linnenbank REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */ 4729d08975SNiek Linnenbank REG_FRM_FLT = 0x0038, /* Receive Frame Filter */ 4829d08975SNiek Linnenbank REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */ 4929d08975SNiek Linnenbank REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */ 5029d08975SNiek Linnenbank REG_MII_CMD = 0x0048, /* Management Interface Command */ 5129d08975SNiek Linnenbank REG_MII_DATA = 0x004C, /* Management Interface Data */ 5229d08975SNiek Linnenbank REG_ADDR_HIGH = 0x0050, /* MAC Address High */ 5329d08975SNiek Linnenbank REG_ADDR_LOW = 0x0054, /* MAC Address Low */ 5429d08975SNiek Linnenbank REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */ 5529d08975SNiek Linnenbank REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */ 5629d08975SNiek Linnenbank REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */ 5729d08975SNiek Linnenbank REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */ 5829d08975SNiek Linnenbank REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */ 5929d08975SNiek Linnenbank REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */ 6029d08975SNiek Linnenbank REG_RGMII_STA = 0x00D0, /* RGMII Status */ 6129d08975SNiek Linnenbank }; 6229d08975SNiek Linnenbank 6329d08975SNiek Linnenbank /* EMAC register flags */ 6429d08975SNiek Linnenbank enum { 6529d08975SNiek Linnenbank BASIC_CTL0_100Mbps = (0b11 << 2), 6629d08975SNiek Linnenbank BASIC_CTL0_FD = (1 << 0), 6729d08975SNiek Linnenbank BASIC_CTL1_SOFTRST = (1 << 0), 6829d08975SNiek Linnenbank }; 6929d08975SNiek Linnenbank 7029d08975SNiek Linnenbank enum { 7129d08975SNiek Linnenbank INT_STA_RGMII_LINK = (1 << 16), 7229d08975SNiek Linnenbank INT_STA_RX_EARLY = (1 << 13), 7329d08975SNiek Linnenbank INT_STA_RX_OVERFLOW = (1 << 12), 7429d08975SNiek Linnenbank INT_STA_RX_TIMEOUT = (1 << 11), 7529d08975SNiek Linnenbank INT_STA_RX_DMA_STOP = (1 << 10), 7629d08975SNiek Linnenbank INT_STA_RX_BUF_UA = (1 << 9), 7729d08975SNiek Linnenbank INT_STA_RX = (1 << 8), 7829d08975SNiek Linnenbank INT_STA_TX_EARLY = (1 << 5), 7929d08975SNiek Linnenbank INT_STA_TX_UNDERFLOW = (1 << 4), 8029d08975SNiek Linnenbank INT_STA_TX_TIMEOUT = (1 << 3), 8129d08975SNiek Linnenbank INT_STA_TX_BUF_UA = (1 << 2), 8229d08975SNiek Linnenbank INT_STA_TX_DMA_STOP = (1 << 1), 8329d08975SNiek Linnenbank INT_STA_TX = (1 << 0), 8429d08975SNiek Linnenbank }; 8529d08975SNiek Linnenbank 8629d08975SNiek Linnenbank enum { 8729d08975SNiek Linnenbank INT_EN_RX_EARLY = (1 << 13), 8829d08975SNiek Linnenbank INT_EN_RX_OVERFLOW = (1 << 12), 8929d08975SNiek Linnenbank INT_EN_RX_TIMEOUT = (1 << 11), 9029d08975SNiek Linnenbank INT_EN_RX_DMA_STOP = (1 << 10), 9129d08975SNiek Linnenbank INT_EN_RX_BUF_UA = (1 << 9), 9229d08975SNiek Linnenbank INT_EN_RX = (1 << 8), 9329d08975SNiek Linnenbank INT_EN_TX_EARLY = (1 << 5), 9429d08975SNiek Linnenbank INT_EN_TX_UNDERFLOW = (1 << 4), 9529d08975SNiek Linnenbank INT_EN_TX_TIMEOUT = (1 << 3), 9629d08975SNiek Linnenbank INT_EN_TX_BUF_UA = (1 << 2), 9729d08975SNiek Linnenbank INT_EN_TX_DMA_STOP = (1 << 1), 9829d08975SNiek Linnenbank INT_EN_TX = (1 << 0), 9929d08975SNiek Linnenbank }; 10029d08975SNiek Linnenbank 10129d08975SNiek Linnenbank enum { 10229d08975SNiek Linnenbank TX_CTL0_TX_EN = (1 << 31), 10329d08975SNiek Linnenbank TX_CTL1_TX_DMA_START = (1 << 31), 10429d08975SNiek Linnenbank TX_CTL1_TX_DMA_EN = (1 << 30), 10529d08975SNiek Linnenbank TX_CTL1_TX_FLUSH = (1 << 0), 10629d08975SNiek Linnenbank }; 10729d08975SNiek Linnenbank 10829d08975SNiek Linnenbank enum { 10929d08975SNiek Linnenbank RX_CTL0_RX_EN = (1 << 31), 11029d08975SNiek Linnenbank RX_CTL0_STRIP_FCS = (1 << 28), 11129d08975SNiek Linnenbank RX_CTL0_CRC_IPV4 = (1 << 27), 11229d08975SNiek Linnenbank }; 11329d08975SNiek Linnenbank 11429d08975SNiek Linnenbank enum { 11529d08975SNiek Linnenbank RX_CTL1_RX_DMA_START = (1 << 31), 11629d08975SNiek Linnenbank RX_CTL1_RX_DMA_EN = (1 << 30), 11729d08975SNiek Linnenbank RX_CTL1_RX_MD = (1 << 1), 11829d08975SNiek Linnenbank }; 11929d08975SNiek Linnenbank 12029d08975SNiek Linnenbank enum { 12129d08975SNiek Linnenbank RX_FRM_FLT_DIS_ADDR = (1 << 31), 12229d08975SNiek Linnenbank }; 12329d08975SNiek Linnenbank 12429d08975SNiek Linnenbank enum { 12529d08975SNiek Linnenbank MII_CMD_PHY_ADDR_SHIFT = (12), 12629d08975SNiek Linnenbank MII_CMD_PHY_ADDR_MASK = (0xf000), 12729d08975SNiek Linnenbank MII_CMD_PHY_REG_SHIFT = (4), 12829d08975SNiek Linnenbank MII_CMD_PHY_REG_MASK = (0xf0), 12929d08975SNiek Linnenbank MII_CMD_PHY_RW = (1 << 1), 13029d08975SNiek Linnenbank MII_CMD_PHY_BUSY = (1 << 0), 13129d08975SNiek Linnenbank }; 13229d08975SNiek Linnenbank 13329d08975SNiek Linnenbank enum { 13429d08975SNiek Linnenbank TX_DMA_STA_STOP = (0b000), 13529d08975SNiek Linnenbank TX_DMA_STA_RUN_FETCH = (0b001), 13629d08975SNiek Linnenbank TX_DMA_STA_WAIT_STA = (0b010), 13729d08975SNiek Linnenbank }; 13829d08975SNiek Linnenbank 13929d08975SNiek Linnenbank enum { 14029d08975SNiek Linnenbank RX_DMA_STA_STOP = (0b000), 14129d08975SNiek Linnenbank RX_DMA_STA_RUN_FETCH = (0b001), 14229d08975SNiek Linnenbank RX_DMA_STA_WAIT_FRM = (0b011), 14329d08975SNiek Linnenbank }; 14429d08975SNiek Linnenbank 14529d08975SNiek Linnenbank /* EMAC register reset values */ 14629d08975SNiek Linnenbank enum { 14729d08975SNiek Linnenbank REG_BASIC_CTL_1_RST = 0x08000000, 14829d08975SNiek Linnenbank }; 14929d08975SNiek Linnenbank 15029d08975SNiek Linnenbank /* EMAC constants */ 15129d08975SNiek Linnenbank enum { 15229d08975SNiek Linnenbank AW_SUN8I_EMAC_MIN_PKT_SZ = 64 15329d08975SNiek Linnenbank }; 15429d08975SNiek Linnenbank 15529d08975SNiek Linnenbank /* Transmit/receive frame descriptor */ 15629d08975SNiek Linnenbank typedef struct FrameDescriptor { 15729d08975SNiek Linnenbank uint32_t status; 15829d08975SNiek Linnenbank uint32_t status2; 15929d08975SNiek Linnenbank uint32_t addr; 16029d08975SNiek Linnenbank uint32_t next; 16129d08975SNiek Linnenbank } FrameDescriptor; 16229d08975SNiek Linnenbank 16329d08975SNiek Linnenbank /* Frame descriptor flags */ 16429d08975SNiek Linnenbank enum { 16529d08975SNiek Linnenbank DESC_STATUS_CTL = (1 << 31), 16629d08975SNiek Linnenbank DESC_STATUS2_BUF_SIZE_MASK = (0x7ff), 16729d08975SNiek Linnenbank }; 16829d08975SNiek Linnenbank 16929d08975SNiek Linnenbank /* Transmit frame descriptor flags */ 17029d08975SNiek Linnenbank enum { 17129d08975SNiek Linnenbank TX_DESC_STATUS_LENGTH_ERR = (1 << 14), 17229d08975SNiek Linnenbank TX_DESC_STATUS2_FIRST_DESC = (1 << 29), 17329d08975SNiek Linnenbank TX_DESC_STATUS2_LAST_DESC = (1 << 30), 17429d08975SNiek Linnenbank TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27), 17529d08975SNiek Linnenbank }; 17629d08975SNiek Linnenbank 17729d08975SNiek Linnenbank /* Receive frame descriptor flags */ 17829d08975SNiek Linnenbank enum { 17929d08975SNiek Linnenbank RX_DESC_STATUS_FIRST_DESC = (1 << 9), 18029d08975SNiek Linnenbank RX_DESC_STATUS_LAST_DESC = (1 << 8), 18129d08975SNiek Linnenbank RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000), 18229d08975SNiek Linnenbank RX_DESC_STATUS_FRM_LEN_SHIFT = (16), 18329d08975SNiek Linnenbank RX_DESC_STATUS_NO_BUF = (1 << 14), 18429d08975SNiek Linnenbank RX_DESC_STATUS_HEADER_ERR = (1 << 7), 18529d08975SNiek Linnenbank RX_DESC_STATUS_LENGTH_ERR = (1 << 4), 18629d08975SNiek Linnenbank RX_DESC_STATUS_CRC_ERR = (1 << 1), 18729d08975SNiek Linnenbank RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0), 18829d08975SNiek Linnenbank RX_DESC_STATUS2_RX_INT_CTL = (1 << 31), 18929d08975SNiek Linnenbank }; 19029d08975SNiek Linnenbank 19129d08975SNiek Linnenbank /* MII register offsets */ 19229d08975SNiek Linnenbank enum { 19329d08975SNiek Linnenbank MII_REG_CR = (0x0), /* Control */ 19429d08975SNiek Linnenbank MII_REG_ST = (0x1), /* Status */ 19529d08975SNiek Linnenbank MII_REG_ID_HIGH = (0x2), /* Identifier High */ 19629d08975SNiek Linnenbank MII_REG_ID_LOW = (0x3), /* Identifier Low */ 19729d08975SNiek Linnenbank MII_REG_ADV = (0x4), /* Advertised abilities */ 19829d08975SNiek Linnenbank MII_REG_LPA = (0x5), /* Link partner abilities */ 19929d08975SNiek Linnenbank }; 20029d08975SNiek Linnenbank 20129d08975SNiek Linnenbank /* MII register flags */ 20229d08975SNiek Linnenbank enum { 20329d08975SNiek Linnenbank MII_REG_CR_RESET = (1 << 15), 20429d08975SNiek Linnenbank MII_REG_CR_POWERDOWN = (1 << 11), 20529d08975SNiek Linnenbank MII_REG_CR_10Mbit = (0), 20629d08975SNiek Linnenbank MII_REG_CR_100Mbit = (1 << 13), 20729d08975SNiek Linnenbank MII_REG_CR_1000Mbit = (1 << 6), 20829d08975SNiek Linnenbank MII_REG_CR_AUTO_NEG = (1 << 12), 20929d08975SNiek Linnenbank MII_REG_CR_AUTO_NEG_RESTART = (1 << 9), 21029d08975SNiek Linnenbank MII_REG_CR_FULLDUPLEX = (1 << 8), 21129d08975SNiek Linnenbank }; 21229d08975SNiek Linnenbank 21329d08975SNiek Linnenbank enum { 21429d08975SNiek Linnenbank MII_REG_ST_100BASE_T4 = (1 << 15), 21529d08975SNiek Linnenbank MII_REG_ST_100BASE_X_FD = (1 << 14), 21629d08975SNiek Linnenbank MII_REG_ST_100BASE_X_HD = (1 << 13), 21729d08975SNiek Linnenbank MII_REG_ST_10_FD = (1 << 12), 21829d08975SNiek Linnenbank MII_REG_ST_10_HD = (1 << 11), 21929d08975SNiek Linnenbank MII_REG_ST_100BASE_T2_FD = (1 << 10), 22029d08975SNiek Linnenbank MII_REG_ST_100BASE_T2_HD = (1 << 9), 22129d08975SNiek Linnenbank MII_REG_ST_AUTONEG_COMPLETE = (1 << 5), 22229d08975SNiek Linnenbank MII_REG_ST_AUTONEG_AVAIL = (1 << 3), 22329d08975SNiek Linnenbank MII_REG_ST_LINK_UP = (1 << 2), 22429d08975SNiek Linnenbank }; 22529d08975SNiek Linnenbank 22629d08975SNiek Linnenbank enum { 22729d08975SNiek Linnenbank MII_REG_LPA_10_HD = (1 << 5), 22829d08975SNiek Linnenbank MII_REG_LPA_10_FD = (1 << 6), 22929d08975SNiek Linnenbank MII_REG_LPA_100_HD = (1 << 7), 23029d08975SNiek Linnenbank MII_REG_LPA_100_FD = (1 << 8), 23129d08975SNiek Linnenbank MII_REG_LPA_PAUSE = (1 << 10), 23229d08975SNiek Linnenbank MII_REG_LPA_ASYMPAUSE = (1 << 11), 23329d08975SNiek Linnenbank }; 23429d08975SNiek Linnenbank 23529d08975SNiek Linnenbank /* MII constants */ 23629d08975SNiek Linnenbank enum { 23729d08975SNiek Linnenbank MII_PHY_ID_HIGH = 0x0044, 23829d08975SNiek Linnenbank MII_PHY_ID_LOW = 0x1400, 23929d08975SNiek Linnenbank }; 24029d08975SNiek Linnenbank 24129d08975SNiek Linnenbank static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s, 24229d08975SNiek Linnenbank bool link_active) 24329d08975SNiek Linnenbank { 24429d08975SNiek Linnenbank if (link_active) { 24529d08975SNiek Linnenbank s->mii_st |= MII_REG_ST_LINK_UP; 24629d08975SNiek Linnenbank } else { 24729d08975SNiek Linnenbank s->mii_st &= ~MII_REG_ST_LINK_UP; 24829d08975SNiek Linnenbank } 24929d08975SNiek Linnenbank } 25029d08975SNiek Linnenbank 25129d08975SNiek Linnenbank static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s, 25229d08975SNiek Linnenbank bool link_active) 25329d08975SNiek Linnenbank { 25429d08975SNiek Linnenbank s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG | 25529d08975SNiek Linnenbank MII_REG_CR_FULLDUPLEX; 25629d08975SNiek Linnenbank s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD | 25729d08975SNiek Linnenbank MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD | 25829d08975SNiek Linnenbank MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD | 25929d08975SNiek Linnenbank MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL; 26029d08975SNiek Linnenbank s->mii_adv = 0; 26129d08975SNiek Linnenbank 26229d08975SNiek Linnenbank allwinner_sun8i_emac_mii_set_link(s, link_active); 26329d08975SNiek Linnenbank } 26429d08975SNiek Linnenbank 26529d08975SNiek Linnenbank static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s) 26629d08975SNiek Linnenbank { 26729d08975SNiek Linnenbank uint8_t addr, reg; 26829d08975SNiek Linnenbank 26929d08975SNiek Linnenbank addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT; 27029d08975SNiek Linnenbank reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT; 27129d08975SNiek Linnenbank 27229d08975SNiek Linnenbank if (addr != s->mii_phy_addr) { 27329d08975SNiek Linnenbank return; 27429d08975SNiek Linnenbank } 27529d08975SNiek Linnenbank 27629d08975SNiek Linnenbank /* Read or write a PHY register? */ 27729d08975SNiek Linnenbank if (s->mii_cmd & MII_CMD_PHY_RW) { 27829d08975SNiek Linnenbank trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data); 27929d08975SNiek Linnenbank 28029d08975SNiek Linnenbank switch (reg) { 28129d08975SNiek Linnenbank case MII_REG_CR: 28229d08975SNiek Linnenbank if (s->mii_data & MII_REG_CR_RESET) { 28329d08975SNiek Linnenbank allwinner_sun8i_emac_mii_reset(s, s->mii_st & 28429d08975SNiek Linnenbank MII_REG_ST_LINK_UP); 28529d08975SNiek Linnenbank } else { 28629d08975SNiek Linnenbank s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET | 28729d08975SNiek Linnenbank MII_REG_CR_AUTO_NEG_RESTART); 28829d08975SNiek Linnenbank } 28929d08975SNiek Linnenbank break; 29029d08975SNiek Linnenbank case MII_REG_ADV: 29129d08975SNiek Linnenbank s->mii_adv = s->mii_data; 29229d08975SNiek Linnenbank break; 29329d08975SNiek Linnenbank case MII_REG_ID_HIGH: 29429d08975SNiek Linnenbank case MII_REG_ID_LOW: 29529d08975SNiek Linnenbank case MII_REG_LPA: 29629d08975SNiek Linnenbank break; 29729d08975SNiek Linnenbank default: 29829d08975SNiek Linnenbank qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to " 29929d08975SNiek Linnenbank "unknown MII register 0x%x\n", reg); 30029d08975SNiek Linnenbank break; 30129d08975SNiek Linnenbank } 30229d08975SNiek Linnenbank } else { 30329d08975SNiek Linnenbank switch (reg) { 30429d08975SNiek Linnenbank case MII_REG_CR: 30529d08975SNiek Linnenbank s->mii_data = s->mii_cr; 30629d08975SNiek Linnenbank break; 30729d08975SNiek Linnenbank case MII_REG_ST: 30829d08975SNiek Linnenbank s->mii_data = s->mii_st; 30929d08975SNiek Linnenbank break; 31029d08975SNiek Linnenbank case MII_REG_ID_HIGH: 31129d08975SNiek Linnenbank s->mii_data = MII_PHY_ID_HIGH; 31229d08975SNiek Linnenbank break; 31329d08975SNiek Linnenbank case MII_REG_ID_LOW: 31429d08975SNiek Linnenbank s->mii_data = MII_PHY_ID_LOW; 31529d08975SNiek Linnenbank break; 31629d08975SNiek Linnenbank case MII_REG_ADV: 31729d08975SNiek Linnenbank s->mii_data = s->mii_adv; 31829d08975SNiek Linnenbank break; 31929d08975SNiek Linnenbank case MII_REG_LPA: 32029d08975SNiek Linnenbank s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD | 32129d08975SNiek Linnenbank MII_REG_LPA_100_HD | MII_REG_LPA_100_FD | 32229d08975SNiek Linnenbank MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE; 32329d08975SNiek Linnenbank break; 32429d08975SNiek Linnenbank default: 32529d08975SNiek Linnenbank qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to " 32629d08975SNiek Linnenbank "unknown MII register 0x%x\n", reg); 32729d08975SNiek Linnenbank s->mii_data = 0; 32829d08975SNiek Linnenbank break; 32929d08975SNiek Linnenbank } 33029d08975SNiek Linnenbank 33129d08975SNiek Linnenbank trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data); 33229d08975SNiek Linnenbank } 33329d08975SNiek Linnenbank } 33429d08975SNiek Linnenbank 33529d08975SNiek Linnenbank static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s) 33629d08975SNiek Linnenbank { 33729d08975SNiek Linnenbank qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0); 33829d08975SNiek Linnenbank } 33929d08975SNiek Linnenbank 34029d08975SNiek Linnenbank static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc, 34129d08975SNiek Linnenbank size_t min_size) 34229d08975SNiek Linnenbank { 34329d08975SNiek Linnenbank uint32_t paddr = desc->next; 34429d08975SNiek Linnenbank 34529d08975SNiek Linnenbank cpu_physical_memory_read(paddr, desc, sizeof(*desc)); 34629d08975SNiek Linnenbank 34729d08975SNiek Linnenbank if ((desc->status & DESC_STATUS_CTL) && 34829d08975SNiek Linnenbank (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { 34929d08975SNiek Linnenbank return paddr; 35029d08975SNiek Linnenbank } else { 35129d08975SNiek Linnenbank return 0; 35229d08975SNiek Linnenbank } 35329d08975SNiek Linnenbank } 35429d08975SNiek Linnenbank 35529d08975SNiek Linnenbank static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc, 35629d08975SNiek Linnenbank uint32_t start_addr, 35729d08975SNiek Linnenbank size_t min_size) 35829d08975SNiek Linnenbank { 35929d08975SNiek Linnenbank uint32_t desc_addr = start_addr; 36029d08975SNiek Linnenbank 36129d08975SNiek Linnenbank /* Note that the list is a cycle. Last entry points back to the head. */ 36229d08975SNiek Linnenbank while (desc_addr != 0) { 36329d08975SNiek Linnenbank cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); 36429d08975SNiek Linnenbank 36529d08975SNiek Linnenbank if ((desc->status & DESC_STATUS_CTL) && 36629d08975SNiek Linnenbank (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { 36729d08975SNiek Linnenbank return desc_addr; 36829d08975SNiek Linnenbank } else if (desc->next == start_addr) { 36929d08975SNiek Linnenbank break; 37029d08975SNiek Linnenbank } else { 37129d08975SNiek Linnenbank desc_addr = desc->next; 37229d08975SNiek Linnenbank } 37329d08975SNiek Linnenbank } 37429d08975SNiek Linnenbank 37529d08975SNiek Linnenbank return 0; 37629d08975SNiek Linnenbank } 37729d08975SNiek Linnenbank 37829d08975SNiek Linnenbank static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s, 37929d08975SNiek Linnenbank FrameDescriptor *desc, 38029d08975SNiek Linnenbank size_t min_size) 38129d08975SNiek Linnenbank { 38229d08975SNiek Linnenbank return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size); 38329d08975SNiek Linnenbank } 38429d08975SNiek Linnenbank 38529d08975SNiek Linnenbank static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s, 38629d08975SNiek Linnenbank FrameDescriptor *desc, 38729d08975SNiek Linnenbank size_t min_size) 38829d08975SNiek Linnenbank { 38929d08975SNiek Linnenbank return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size); 39029d08975SNiek Linnenbank } 39129d08975SNiek Linnenbank 39229d08975SNiek Linnenbank static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc, 39329d08975SNiek Linnenbank uint32_t phys_addr) 39429d08975SNiek Linnenbank { 39529d08975SNiek Linnenbank cpu_physical_memory_write(phys_addr, desc, sizeof(*desc)); 39629d08975SNiek Linnenbank } 39729d08975SNiek Linnenbank 398767cc9a9SPhilippe Mathieu-Daudé static bool allwinner_sun8i_emac_can_receive(NetClientState *nc) 39929d08975SNiek Linnenbank { 40029d08975SNiek Linnenbank AwSun8iEmacState *s = qemu_get_nic_opaque(nc); 40129d08975SNiek Linnenbank FrameDescriptor desc; 40229d08975SNiek Linnenbank 40329d08975SNiek Linnenbank return (s->rx_ctl0 & RX_CTL0_RX_EN) && 40429d08975SNiek Linnenbank (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0); 40529d08975SNiek Linnenbank } 40629d08975SNiek Linnenbank 40729d08975SNiek Linnenbank static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc, 40829d08975SNiek Linnenbank const uint8_t *buf, 40929d08975SNiek Linnenbank size_t size) 41029d08975SNiek Linnenbank { 41129d08975SNiek Linnenbank AwSun8iEmacState *s = qemu_get_nic_opaque(nc); 41229d08975SNiek Linnenbank FrameDescriptor desc; 41329d08975SNiek Linnenbank size_t bytes_left = size; 41429d08975SNiek Linnenbank size_t desc_bytes = 0; 41529d08975SNiek Linnenbank size_t pad_fcs_size = 4; 41629d08975SNiek Linnenbank size_t padding = 0; 41729d08975SNiek Linnenbank 41829d08975SNiek Linnenbank if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) { 41929d08975SNiek Linnenbank return -1; 42029d08975SNiek Linnenbank } 42129d08975SNiek Linnenbank 42229d08975SNiek Linnenbank s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc, 42329d08975SNiek Linnenbank AW_SUN8I_EMAC_MIN_PKT_SZ); 42429d08975SNiek Linnenbank if (!s->rx_desc_curr) { 42529d08975SNiek Linnenbank s->int_sta |= INT_STA_RX_BUF_UA; 42629d08975SNiek Linnenbank } 42729d08975SNiek Linnenbank 42829d08975SNiek Linnenbank /* Keep filling RX descriptors until the whole frame is written */ 42929d08975SNiek Linnenbank while (s->rx_desc_curr && bytes_left > 0) { 43029d08975SNiek Linnenbank desc.status &= ~DESC_STATUS_CTL; 43129d08975SNiek Linnenbank desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK; 43229d08975SNiek Linnenbank 43329d08975SNiek Linnenbank if (bytes_left == size) { 43429d08975SNiek Linnenbank desc.status |= RX_DESC_STATUS_FIRST_DESC; 43529d08975SNiek Linnenbank } 43629d08975SNiek Linnenbank 43729d08975SNiek Linnenbank if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) < 43829d08975SNiek Linnenbank (bytes_left + pad_fcs_size)) { 43929d08975SNiek Linnenbank desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; 44029d08975SNiek Linnenbank desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT; 44129d08975SNiek Linnenbank } else { 44229d08975SNiek Linnenbank padding = pad_fcs_size; 44329d08975SNiek Linnenbank if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) { 44429d08975SNiek Linnenbank padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left); 44529d08975SNiek Linnenbank } 44629d08975SNiek Linnenbank 44729d08975SNiek Linnenbank desc_bytes = (bytes_left); 44829d08975SNiek Linnenbank desc.status |= RX_DESC_STATUS_LAST_DESC; 44929d08975SNiek Linnenbank desc.status |= (bytes_left + padding) 45029d08975SNiek Linnenbank << RX_DESC_STATUS_FRM_LEN_SHIFT; 45129d08975SNiek Linnenbank } 45229d08975SNiek Linnenbank 45329d08975SNiek Linnenbank cpu_physical_memory_write(desc.addr, buf, desc_bytes); 45429d08975SNiek Linnenbank allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr); 45529d08975SNiek Linnenbank trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr, 45629d08975SNiek Linnenbank desc_bytes); 45729d08975SNiek Linnenbank 45829d08975SNiek Linnenbank /* Check if frame needs to raise the receive interrupt */ 45929d08975SNiek Linnenbank if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) { 46029d08975SNiek Linnenbank s->int_sta |= INT_STA_RX; 46129d08975SNiek Linnenbank } 46229d08975SNiek Linnenbank 46329d08975SNiek Linnenbank /* Increment variables */ 46429d08975SNiek Linnenbank buf += desc_bytes; 46529d08975SNiek Linnenbank bytes_left -= desc_bytes; 46629d08975SNiek Linnenbank 46729d08975SNiek Linnenbank /* Move to the next descriptor */ 46829d08975SNiek Linnenbank s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64); 46929d08975SNiek Linnenbank if (!s->rx_desc_curr) { 47029d08975SNiek Linnenbank /* Not enough buffer space available */ 47129d08975SNiek Linnenbank s->int_sta |= INT_STA_RX_BUF_UA; 47229d08975SNiek Linnenbank s->rx_desc_curr = s->rx_desc_head; 47329d08975SNiek Linnenbank break; 47429d08975SNiek Linnenbank } 47529d08975SNiek Linnenbank } 47629d08975SNiek Linnenbank 47729d08975SNiek Linnenbank /* Report receive DMA is finished */ 47829d08975SNiek Linnenbank s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START; 47929d08975SNiek Linnenbank allwinner_sun8i_emac_update_irq(s); 48029d08975SNiek Linnenbank 48129d08975SNiek Linnenbank return size; 48229d08975SNiek Linnenbank } 48329d08975SNiek Linnenbank 48429d08975SNiek Linnenbank static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s) 48529d08975SNiek Linnenbank { 48629d08975SNiek Linnenbank NetClientState *nc = qemu_get_queue(s->nic); 48729d08975SNiek Linnenbank FrameDescriptor desc; 48829d08975SNiek Linnenbank size_t bytes = 0; 48929d08975SNiek Linnenbank size_t packet_bytes = 0; 49029d08975SNiek Linnenbank size_t transmitted = 0; 49129d08975SNiek Linnenbank static uint8_t packet_buf[2048]; 49229d08975SNiek Linnenbank 49329d08975SNiek Linnenbank s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0); 49429d08975SNiek Linnenbank 49529d08975SNiek Linnenbank /* Read all transmit descriptors */ 49629d08975SNiek Linnenbank while (s->tx_desc_curr != 0) { 49729d08975SNiek Linnenbank 49829d08975SNiek Linnenbank /* Read from physical memory into packet buffer */ 49929d08975SNiek Linnenbank bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; 50029d08975SNiek Linnenbank if (bytes + packet_bytes > sizeof(packet_buf)) { 50129d08975SNiek Linnenbank desc.status |= TX_DESC_STATUS_LENGTH_ERR; 50229d08975SNiek Linnenbank break; 50329d08975SNiek Linnenbank } 50429d08975SNiek Linnenbank cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes); 50529d08975SNiek Linnenbank packet_bytes += bytes; 50629d08975SNiek Linnenbank desc.status &= ~DESC_STATUS_CTL; 50729d08975SNiek Linnenbank allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr); 50829d08975SNiek Linnenbank 50929d08975SNiek Linnenbank /* After the last descriptor, send the packet */ 51029d08975SNiek Linnenbank if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) { 51129d08975SNiek Linnenbank if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) { 51229d08975SNiek Linnenbank net_checksum_calculate(packet_buf, packet_bytes); 51329d08975SNiek Linnenbank } 51429d08975SNiek Linnenbank 51529d08975SNiek Linnenbank qemu_send_packet(nc, packet_buf, packet_bytes); 51629d08975SNiek Linnenbank trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr, 51729d08975SNiek Linnenbank bytes); 51829d08975SNiek Linnenbank 51929d08975SNiek Linnenbank packet_bytes = 0; 52029d08975SNiek Linnenbank transmitted++; 52129d08975SNiek Linnenbank } 52229d08975SNiek Linnenbank s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0); 52329d08975SNiek Linnenbank } 52429d08975SNiek Linnenbank 52529d08975SNiek Linnenbank /* Raise transmit completed interrupt */ 52629d08975SNiek Linnenbank if (transmitted > 0) { 52729d08975SNiek Linnenbank s->int_sta |= INT_STA_TX; 52829d08975SNiek Linnenbank s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START; 52929d08975SNiek Linnenbank allwinner_sun8i_emac_update_irq(s); 53029d08975SNiek Linnenbank } 53129d08975SNiek Linnenbank } 53229d08975SNiek Linnenbank 53329d08975SNiek Linnenbank static void allwinner_sun8i_emac_reset(DeviceState *dev) 53429d08975SNiek Linnenbank { 53529d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(dev); 53629d08975SNiek Linnenbank NetClientState *nc = qemu_get_queue(s->nic); 53729d08975SNiek Linnenbank 53829d08975SNiek Linnenbank trace_allwinner_sun8i_emac_reset(); 53929d08975SNiek Linnenbank 54029d08975SNiek Linnenbank s->mii_cmd = 0; 54129d08975SNiek Linnenbank s->mii_data = 0; 54229d08975SNiek Linnenbank s->basic_ctl0 = 0; 54329d08975SNiek Linnenbank s->basic_ctl1 = REG_BASIC_CTL_1_RST; 54429d08975SNiek Linnenbank s->int_en = 0; 54529d08975SNiek Linnenbank s->int_sta = 0; 54629d08975SNiek Linnenbank s->frm_flt = 0; 54729d08975SNiek Linnenbank s->rx_ctl0 = 0; 54829d08975SNiek Linnenbank s->rx_ctl1 = RX_CTL1_RX_MD; 54929d08975SNiek Linnenbank s->rx_desc_head = 0; 55029d08975SNiek Linnenbank s->rx_desc_curr = 0; 55129d08975SNiek Linnenbank s->tx_ctl0 = 0; 55229d08975SNiek Linnenbank s->tx_ctl1 = 0; 55329d08975SNiek Linnenbank s->tx_desc_head = 0; 55429d08975SNiek Linnenbank s->tx_desc_curr = 0; 55529d08975SNiek Linnenbank s->tx_flowctl = 0; 55629d08975SNiek Linnenbank 55729d08975SNiek Linnenbank allwinner_sun8i_emac_mii_reset(s, !nc->link_down); 55829d08975SNiek Linnenbank } 55929d08975SNiek Linnenbank 56029d08975SNiek Linnenbank static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset, 56129d08975SNiek Linnenbank unsigned size) 56229d08975SNiek Linnenbank { 56329d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque); 56429d08975SNiek Linnenbank uint64_t value = 0; 56529d08975SNiek Linnenbank FrameDescriptor desc; 56629d08975SNiek Linnenbank 56729d08975SNiek Linnenbank switch (offset) { 56829d08975SNiek Linnenbank case REG_BASIC_CTL_0: /* Basic Control 0 */ 56929d08975SNiek Linnenbank value = s->basic_ctl0; 57029d08975SNiek Linnenbank break; 57129d08975SNiek Linnenbank case REG_BASIC_CTL_1: /* Basic Control 1 */ 57229d08975SNiek Linnenbank value = s->basic_ctl1; 57329d08975SNiek Linnenbank break; 57429d08975SNiek Linnenbank case REG_INT_STA: /* Interrupt Status */ 57529d08975SNiek Linnenbank value = s->int_sta; 57629d08975SNiek Linnenbank break; 57729d08975SNiek Linnenbank case REG_INT_EN: /* Interupt Enable */ 57829d08975SNiek Linnenbank value = s->int_en; 57929d08975SNiek Linnenbank break; 58029d08975SNiek Linnenbank case REG_TX_CTL_0: /* Transmit Control 0 */ 58129d08975SNiek Linnenbank value = s->tx_ctl0; 58229d08975SNiek Linnenbank break; 58329d08975SNiek Linnenbank case REG_TX_CTL_1: /* Transmit Control 1 */ 58429d08975SNiek Linnenbank value = s->tx_ctl1; 58529d08975SNiek Linnenbank break; 58629d08975SNiek Linnenbank case REG_TX_FLOW_CTL: /* Transmit Flow Control */ 58729d08975SNiek Linnenbank value = s->tx_flowctl; 58829d08975SNiek Linnenbank break; 58929d08975SNiek Linnenbank case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ 59029d08975SNiek Linnenbank value = s->tx_desc_head; 59129d08975SNiek Linnenbank break; 59229d08975SNiek Linnenbank case REG_RX_CTL_0: /* Receive Control 0 */ 59329d08975SNiek Linnenbank value = s->rx_ctl0; 59429d08975SNiek Linnenbank break; 59529d08975SNiek Linnenbank case REG_RX_CTL_1: /* Receive Control 1 */ 59629d08975SNiek Linnenbank value = s->rx_ctl1; 59729d08975SNiek Linnenbank break; 59829d08975SNiek Linnenbank case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ 59929d08975SNiek Linnenbank value = s->rx_desc_head; 60029d08975SNiek Linnenbank break; 60129d08975SNiek Linnenbank case REG_FRM_FLT: /* Receive Frame Filter */ 60229d08975SNiek Linnenbank value = s->frm_flt; 60329d08975SNiek Linnenbank break; 60429d08975SNiek Linnenbank case REG_RX_HASH_0: /* Receive Hash Table 0 */ 60529d08975SNiek Linnenbank case REG_RX_HASH_1: /* Receive Hash Table 1 */ 60629d08975SNiek Linnenbank break; 60729d08975SNiek Linnenbank case REG_MII_CMD: /* Management Interface Command */ 60829d08975SNiek Linnenbank value = s->mii_cmd; 60929d08975SNiek Linnenbank break; 61029d08975SNiek Linnenbank case REG_MII_DATA: /* Management Interface Data */ 61129d08975SNiek Linnenbank value = s->mii_data; 61229d08975SNiek Linnenbank break; 61329d08975SNiek Linnenbank case REG_ADDR_HIGH: /* MAC Address High */ 614*b88fb124SPeter Maydell value = lduw_le_p(s->conf.macaddr.a + 4); 61529d08975SNiek Linnenbank break; 61629d08975SNiek Linnenbank case REG_ADDR_LOW: /* MAC Address Low */ 617*b88fb124SPeter Maydell value = ldl_le_p(s->conf.macaddr.a); 61829d08975SNiek Linnenbank break; 61929d08975SNiek Linnenbank case REG_TX_DMA_STA: /* Transmit DMA Status */ 62029d08975SNiek Linnenbank break; 62129d08975SNiek Linnenbank case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ 62229d08975SNiek Linnenbank value = s->tx_desc_curr; 62329d08975SNiek Linnenbank break; 62429d08975SNiek Linnenbank case REG_TX_CUR_BUF: /* Transmit Current Buffer */ 62529d08975SNiek Linnenbank if (s->tx_desc_curr != 0) { 62629d08975SNiek Linnenbank cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc)); 62729d08975SNiek Linnenbank value = desc.addr; 62829d08975SNiek Linnenbank } else { 62929d08975SNiek Linnenbank value = 0; 63029d08975SNiek Linnenbank } 63129d08975SNiek Linnenbank break; 63229d08975SNiek Linnenbank case REG_RX_DMA_STA: /* Receive DMA Status */ 63329d08975SNiek Linnenbank break; 63429d08975SNiek Linnenbank case REG_RX_CUR_DESC: /* Receive Current Descriptor */ 63529d08975SNiek Linnenbank value = s->rx_desc_curr; 63629d08975SNiek Linnenbank break; 63729d08975SNiek Linnenbank case REG_RX_CUR_BUF: /* Receive Current Buffer */ 63829d08975SNiek Linnenbank if (s->rx_desc_curr != 0) { 63929d08975SNiek Linnenbank cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc)); 64029d08975SNiek Linnenbank value = desc.addr; 64129d08975SNiek Linnenbank } else { 64229d08975SNiek Linnenbank value = 0; 64329d08975SNiek Linnenbank } 64429d08975SNiek Linnenbank break; 64529d08975SNiek Linnenbank case REG_RGMII_STA: /* RGMII Status */ 64629d08975SNiek Linnenbank break; 64729d08975SNiek Linnenbank default: 64829d08975SNiek Linnenbank qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown " 64929d08975SNiek Linnenbank "EMAC register 0x" TARGET_FMT_plx "\n", 65029d08975SNiek Linnenbank offset); 65129d08975SNiek Linnenbank } 65229d08975SNiek Linnenbank 65329d08975SNiek Linnenbank trace_allwinner_sun8i_emac_read(offset, value); 65429d08975SNiek Linnenbank return value; 65529d08975SNiek Linnenbank } 65629d08975SNiek Linnenbank 65729d08975SNiek Linnenbank static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset, 65829d08975SNiek Linnenbank uint64_t value, unsigned size) 65929d08975SNiek Linnenbank { 66029d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque); 66129d08975SNiek Linnenbank NetClientState *nc = qemu_get_queue(s->nic); 66229d08975SNiek Linnenbank 66329d08975SNiek Linnenbank trace_allwinner_sun8i_emac_write(offset, value); 66429d08975SNiek Linnenbank 66529d08975SNiek Linnenbank switch (offset) { 66629d08975SNiek Linnenbank case REG_BASIC_CTL_0: /* Basic Control 0 */ 66729d08975SNiek Linnenbank s->basic_ctl0 = value; 66829d08975SNiek Linnenbank break; 66929d08975SNiek Linnenbank case REG_BASIC_CTL_1: /* Basic Control 1 */ 67029d08975SNiek Linnenbank if (value & BASIC_CTL1_SOFTRST) { 67129d08975SNiek Linnenbank allwinner_sun8i_emac_reset(DEVICE(s)); 67229d08975SNiek Linnenbank value &= ~BASIC_CTL1_SOFTRST; 67329d08975SNiek Linnenbank } 67429d08975SNiek Linnenbank s->basic_ctl1 = value; 67529d08975SNiek Linnenbank if (allwinner_sun8i_emac_can_receive(nc)) { 67629d08975SNiek Linnenbank qemu_flush_queued_packets(nc); 67729d08975SNiek Linnenbank } 67829d08975SNiek Linnenbank break; 67929d08975SNiek Linnenbank case REG_INT_STA: /* Interrupt Status */ 68029d08975SNiek Linnenbank s->int_sta &= ~value; 68129d08975SNiek Linnenbank allwinner_sun8i_emac_update_irq(s); 68229d08975SNiek Linnenbank break; 68329d08975SNiek Linnenbank case REG_INT_EN: /* Interrupt Enable */ 68429d08975SNiek Linnenbank s->int_en = value; 68529d08975SNiek Linnenbank allwinner_sun8i_emac_update_irq(s); 68629d08975SNiek Linnenbank break; 68729d08975SNiek Linnenbank case REG_TX_CTL_0: /* Transmit Control 0 */ 68829d08975SNiek Linnenbank s->tx_ctl0 = value; 68929d08975SNiek Linnenbank break; 69029d08975SNiek Linnenbank case REG_TX_CTL_1: /* Transmit Control 1 */ 69129d08975SNiek Linnenbank s->tx_ctl1 = value; 69229d08975SNiek Linnenbank if (value & TX_CTL1_TX_DMA_EN) { 69329d08975SNiek Linnenbank allwinner_sun8i_emac_transmit(s); 69429d08975SNiek Linnenbank } 69529d08975SNiek Linnenbank break; 69629d08975SNiek Linnenbank case REG_TX_FLOW_CTL: /* Transmit Flow Control */ 69729d08975SNiek Linnenbank s->tx_flowctl = value; 69829d08975SNiek Linnenbank break; 69929d08975SNiek Linnenbank case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ 70029d08975SNiek Linnenbank s->tx_desc_head = value; 70129d08975SNiek Linnenbank s->tx_desc_curr = value; 70229d08975SNiek Linnenbank break; 70329d08975SNiek Linnenbank case REG_RX_CTL_0: /* Receive Control 0 */ 70429d08975SNiek Linnenbank s->rx_ctl0 = value; 70529d08975SNiek Linnenbank break; 70629d08975SNiek Linnenbank case REG_RX_CTL_1: /* Receive Control 1 */ 70729d08975SNiek Linnenbank s->rx_ctl1 = value | RX_CTL1_RX_MD; 70829d08975SNiek Linnenbank if ((value & RX_CTL1_RX_DMA_EN) && 70929d08975SNiek Linnenbank allwinner_sun8i_emac_can_receive(nc)) { 71029d08975SNiek Linnenbank qemu_flush_queued_packets(nc); 71129d08975SNiek Linnenbank } 71229d08975SNiek Linnenbank break; 71329d08975SNiek Linnenbank case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ 71429d08975SNiek Linnenbank s->rx_desc_head = value; 71529d08975SNiek Linnenbank s->rx_desc_curr = value; 71629d08975SNiek Linnenbank break; 71729d08975SNiek Linnenbank case REG_FRM_FLT: /* Receive Frame Filter */ 71829d08975SNiek Linnenbank s->frm_flt = value; 71929d08975SNiek Linnenbank break; 72029d08975SNiek Linnenbank case REG_RX_HASH_0: /* Receive Hash Table 0 */ 72129d08975SNiek Linnenbank case REG_RX_HASH_1: /* Receive Hash Table 1 */ 72229d08975SNiek Linnenbank break; 72329d08975SNiek Linnenbank case REG_MII_CMD: /* Management Interface Command */ 72429d08975SNiek Linnenbank s->mii_cmd = value & ~MII_CMD_PHY_BUSY; 72529d08975SNiek Linnenbank allwinner_sun8i_emac_mii_cmd(s); 72629d08975SNiek Linnenbank break; 72729d08975SNiek Linnenbank case REG_MII_DATA: /* Management Interface Data */ 72829d08975SNiek Linnenbank s->mii_data = value; 72929d08975SNiek Linnenbank break; 73029d08975SNiek Linnenbank case REG_ADDR_HIGH: /* MAC Address High */ 731*b88fb124SPeter Maydell stw_le_p(s->conf.macaddr.a + 4, value); 73229d08975SNiek Linnenbank break; 73329d08975SNiek Linnenbank case REG_ADDR_LOW: /* MAC Address Low */ 734*b88fb124SPeter Maydell stl_le_p(s->conf.macaddr.a, value); 73529d08975SNiek Linnenbank break; 73629d08975SNiek Linnenbank case REG_TX_DMA_STA: /* Transmit DMA Status */ 73729d08975SNiek Linnenbank case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ 73829d08975SNiek Linnenbank case REG_TX_CUR_BUF: /* Transmit Current Buffer */ 73929d08975SNiek Linnenbank case REG_RX_DMA_STA: /* Receive DMA Status */ 74029d08975SNiek Linnenbank case REG_RX_CUR_DESC: /* Receive Current Descriptor */ 74129d08975SNiek Linnenbank case REG_RX_CUR_BUF: /* Receive Current Buffer */ 74229d08975SNiek Linnenbank case REG_RGMII_STA: /* RGMII Status */ 74329d08975SNiek Linnenbank break; 74429d08975SNiek Linnenbank default: 74529d08975SNiek Linnenbank qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown " 74629d08975SNiek Linnenbank "EMAC register 0x" TARGET_FMT_plx "\n", 74729d08975SNiek Linnenbank offset); 74829d08975SNiek Linnenbank } 74929d08975SNiek Linnenbank } 75029d08975SNiek Linnenbank 75129d08975SNiek Linnenbank static void allwinner_sun8i_emac_set_link(NetClientState *nc) 75229d08975SNiek Linnenbank { 75329d08975SNiek Linnenbank AwSun8iEmacState *s = qemu_get_nic_opaque(nc); 75429d08975SNiek Linnenbank 75529d08975SNiek Linnenbank trace_allwinner_sun8i_emac_set_link(!nc->link_down); 75629d08975SNiek Linnenbank allwinner_sun8i_emac_mii_set_link(s, !nc->link_down); 75729d08975SNiek Linnenbank } 75829d08975SNiek Linnenbank 75929d08975SNiek Linnenbank static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = { 76029d08975SNiek Linnenbank .read = allwinner_sun8i_emac_read, 76129d08975SNiek Linnenbank .write = allwinner_sun8i_emac_write, 76229d08975SNiek Linnenbank .endianness = DEVICE_NATIVE_ENDIAN, 76329d08975SNiek Linnenbank .valid = { 76429d08975SNiek Linnenbank .min_access_size = 4, 76529d08975SNiek Linnenbank .max_access_size = 4, 76629d08975SNiek Linnenbank }, 76729d08975SNiek Linnenbank .impl.min_access_size = 4, 76829d08975SNiek Linnenbank }; 76929d08975SNiek Linnenbank 77029d08975SNiek Linnenbank static NetClientInfo net_allwinner_sun8i_emac_info = { 77129d08975SNiek Linnenbank .type = NET_CLIENT_DRIVER_NIC, 77229d08975SNiek Linnenbank .size = sizeof(NICState), 77329d08975SNiek Linnenbank .can_receive = allwinner_sun8i_emac_can_receive, 77429d08975SNiek Linnenbank .receive = allwinner_sun8i_emac_receive, 77529d08975SNiek Linnenbank .link_status_changed = allwinner_sun8i_emac_set_link, 77629d08975SNiek Linnenbank }; 77729d08975SNiek Linnenbank 77829d08975SNiek Linnenbank static void allwinner_sun8i_emac_init(Object *obj) 77929d08975SNiek Linnenbank { 78029d08975SNiek Linnenbank SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 78129d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(obj); 78229d08975SNiek Linnenbank 78329d08975SNiek Linnenbank memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops, 78429d08975SNiek Linnenbank s, TYPE_AW_SUN8I_EMAC, 64 * KiB); 78529d08975SNiek Linnenbank sysbus_init_mmio(sbd, &s->iomem); 78629d08975SNiek Linnenbank sysbus_init_irq(sbd, &s->irq); 78729d08975SNiek Linnenbank } 78829d08975SNiek Linnenbank 78929d08975SNiek Linnenbank static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp) 79029d08975SNiek Linnenbank { 79129d08975SNiek Linnenbank AwSun8iEmacState *s = AW_SUN8I_EMAC(dev); 79229d08975SNiek Linnenbank 79329d08975SNiek Linnenbank qemu_macaddr_default_if_unset(&s->conf.macaddr); 79429d08975SNiek Linnenbank s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf, 79529d08975SNiek Linnenbank object_get_typename(OBJECT(dev)), dev->id, s); 79629d08975SNiek Linnenbank qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 79729d08975SNiek Linnenbank } 79829d08975SNiek Linnenbank 79929d08975SNiek Linnenbank static Property allwinner_sun8i_emac_properties[] = { 80029d08975SNiek Linnenbank DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf), 80129d08975SNiek Linnenbank DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0), 80229d08975SNiek Linnenbank DEFINE_PROP_END_OF_LIST(), 80329d08975SNiek Linnenbank }; 80429d08975SNiek Linnenbank 80529d08975SNiek Linnenbank static int allwinner_sun8i_emac_post_load(void *opaque, int version_id) 80629d08975SNiek Linnenbank { 80729d08975SNiek Linnenbank AwSun8iEmacState *s = opaque; 80829d08975SNiek Linnenbank 80929d08975SNiek Linnenbank allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic)); 81029d08975SNiek Linnenbank 81129d08975SNiek Linnenbank return 0; 81229d08975SNiek Linnenbank } 81329d08975SNiek Linnenbank 81429d08975SNiek Linnenbank static const VMStateDescription vmstate_aw_emac = { 81529d08975SNiek Linnenbank .name = "allwinner-sun8i-emac", 81629d08975SNiek Linnenbank .version_id = 1, 81729d08975SNiek Linnenbank .minimum_version_id = 1, 81829d08975SNiek Linnenbank .post_load = allwinner_sun8i_emac_post_load, 81929d08975SNiek Linnenbank .fields = (VMStateField[]) { 82029d08975SNiek Linnenbank VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState), 82129d08975SNiek Linnenbank VMSTATE_UINT32(mii_cmd, AwSun8iEmacState), 82229d08975SNiek Linnenbank VMSTATE_UINT32(mii_data, AwSun8iEmacState), 82329d08975SNiek Linnenbank VMSTATE_UINT32(mii_cr, AwSun8iEmacState), 82429d08975SNiek Linnenbank VMSTATE_UINT32(mii_st, AwSun8iEmacState), 82529d08975SNiek Linnenbank VMSTATE_UINT32(mii_adv, AwSun8iEmacState), 82629d08975SNiek Linnenbank VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState), 82729d08975SNiek Linnenbank VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState), 82829d08975SNiek Linnenbank VMSTATE_UINT32(int_en, AwSun8iEmacState), 82929d08975SNiek Linnenbank VMSTATE_UINT32(int_sta, AwSun8iEmacState), 83029d08975SNiek Linnenbank VMSTATE_UINT32(frm_flt, AwSun8iEmacState), 83129d08975SNiek Linnenbank VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState), 83229d08975SNiek Linnenbank VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState), 83329d08975SNiek Linnenbank VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState), 83429d08975SNiek Linnenbank VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState), 83529d08975SNiek Linnenbank VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState), 83629d08975SNiek Linnenbank VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState), 83729d08975SNiek Linnenbank VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState), 83829d08975SNiek Linnenbank VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState), 83929d08975SNiek Linnenbank VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState), 84029d08975SNiek Linnenbank VMSTATE_END_OF_LIST() 84129d08975SNiek Linnenbank } 84229d08975SNiek Linnenbank }; 84329d08975SNiek Linnenbank 84429d08975SNiek Linnenbank static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data) 84529d08975SNiek Linnenbank { 84629d08975SNiek Linnenbank DeviceClass *dc = DEVICE_CLASS(klass); 84729d08975SNiek Linnenbank 84829d08975SNiek Linnenbank dc->realize = allwinner_sun8i_emac_realize; 84929d08975SNiek Linnenbank dc->reset = allwinner_sun8i_emac_reset; 85029d08975SNiek Linnenbank dc->vmsd = &vmstate_aw_emac; 85129d08975SNiek Linnenbank device_class_set_props(dc, allwinner_sun8i_emac_properties); 85229d08975SNiek Linnenbank } 85329d08975SNiek Linnenbank 85429d08975SNiek Linnenbank static const TypeInfo allwinner_sun8i_emac_info = { 85529d08975SNiek Linnenbank .name = TYPE_AW_SUN8I_EMAC, 85629d08975SNiek Linnenbank .parent = TYPE_SYS_BUS_DEVICE, 85729d08975SNiek Linnenbank .instance_size = sizeof(AwSun8iEmacState), 85829d08975SNiek Linnenbank .instance_init = allwinner_sun8i_emac_init, 85929d08975SNiek Linnenbank .class_init = allwinner_sun8i_emac_class_init, 86029d08975SNiek Linnenbank }; 86129d08975SNiek Linnenbank 86229d08975SNiek Linnenbank static void allwinner_sun8i_emac_register_types(void) 86329d08975SNiek Linnenbank { 86429d08975SNiek Linnenbank type_register_static(&allwinner_sun8i_emac_info); 86529d08975SNiek Linnenbank } 86629d08975SNiek Linnenbank 86729d08975SNiek Linnenbank type_init(allwinner_sun8i_emac_register_types) 868