1 /* 2 * MIOe-3680 PCI CAN device (SJA1000 based) emulation 3 * 4 * Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com) 5 * 6 * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by 7 * Jin Yang and Pavel Pisa 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/event_notifier.h" 30 #include "qemu/module.h" 31 #include "qemu/thread.h" 32 #include "qemu/sockets.h" 33 #include "qapi/error.h" 34 #include "chardev/char.h" 35 #include "hw/hw.h" 36 #include "hw/irq.h" 37 #include "hw/pci/pci.h" 38 #include "net/can_emu.h" 39 40 #include "can_sja1000.h" 41 42 #define TYPE_CAN_PCI_DEV "mioe3680_pci" 43 44 #define MIOe3680_PCI_DEV(obj) \ 45 OBJECT_CHECK(Mioe3680PCIState, (obj), TYPE_CAN_PCI_DEV) 46 47 /* the PCI device and vendor IDs */ 48 #ifndef MIOe3680_PCI_VENDOR_ID1 49 #define MIOe3680_PCI_VENDOR_ID1 0x13fe 50 #endif 51 52 #ifndef MIOe3680_PCI_DEVICE_ID1 53 #define MIOe3680_PCI_DEVICE_ID1 0xc302 54 #endif 55 56 #define MIOe3680_PCI_SJA_COUNT 2 57 #define MIOe3680_PCI_SJA_RANGE 0x400 58 59 #define MIOe3680_PCI_BYTES_PER_SJA 0x80 60 61 typedef struct Mioe3680PCIState { 62 /*< private >*/ 63 PCIDevice dev; 64 /*< public >*/ 65 MemoryRegion sja_io[MIOe3680_PCI_SJA_COUNT]; 66 67 CanSJA1000State sja_state[MIOe3680_PCI_SJA_COUNT]; 68 qemu_irq irq; 69 70 char *model; /* The model that support, only SJA1000 now. */ 71 CanBusState *canbus[MIOe3680_PCI_SJA_COUNT]; 72 } Mioe3680PCIState; 73 74 static void mioe3680_pci_reset(DeviceState *dev) 75 { 76 Mioe3680PCIState *d = MIOe3680_PCI_DEV(dev); 77 int i; 78 79 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 80 can_sja_hardware_reset(&d->sja_state[i]); 81 } 82 } 83 84 static uint64_t mioe3680_pci_sja1_io_read(void *opaque, hwaddr addr, 85 unsigned size) 86 { 87 Mioe3680PCIState *d = opaque; 88 CanSJA1000State *s = &d->sja_state[0]; 89 90 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 91 return 0; 92 } 93 94 return can_sja_mem_read(s, addr >> 2, size); 95 } 96 97 static void mioe3680_pci_sja1_io_write(void *opaque, hwaddr addr, uint64_t data, 98 unsigned size) 99 { 100 Mioe3680PCIState *d = opaque; 101 CanSJA1000State *s = &d->sja_state[0]; 102 103 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 104 return; 105 } 106 107 can_sja_mem_write(s, addr >> 2, data, size); 108 } 109 110 static uint64_t mioe3680_pci_sja2_io_read(void *opaque, hwaddr addr, 111 unsigned size) 112 { 113 Mioe3680PCIState *d = opaque; 114 CanSJA1000State *s = &d->sja_state[1]; 115 116 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 117 return 0; 118 } 119 120 return can_sja_mem_read(s, addr >> 2, size); 121 } 122 123 static void mioe3680_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t data, 124 unsigned size) 125 { 126 Mioe3680PCIState *d = opaque; 127 CanSJA1000State *s = &d->sja_state[1]; 128 129 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 130 return; 131 } 132 133 can_sja_mem_write(s, addr >> 2, data, size); 134 } 135 136 static const MemoryRegionOps mioe3680_pci_sja1_io_ops = { 137 .read = mioe3680_pci_sja1_io_read, 138 .write = mioe3680_pci_sja1_io_write, 139 .endianness = DEVICE_LITTLE_ENDIAN, 140 .impl = { 141 .max_access_size = 1, 142 }, 143 }; 144 145 static const MemoryRegionOps mioe3680_pci_sja2_io_ops = { 146 .read = mioe3680_pci_sja2_io_read, 147 .write = mioe3680_pci_sja2_io_write, 148 .endianness = DEVICE_LITTLE_ENDIAN, 149 .impl = { 150 .max_access_size = 1, 151 }, 152 }; 153 154 static void mioe3680_pci_realize(PCIDevice *pci_dev, Error **errp) 155 { 156 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); 157 uint8_t *pci_conf; 158 int i; 159 160 pci_conf = pci_dev->config; 161 pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 162 163 d->irq = pci_allocate_irq(&d->dev); 164 165 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 166 can_sja_init(&d->sja_state[i], d->irq); 167 } 168 169 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 170 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) { 171 error_setg(errp, "can_sja_connect_to_bus failed"); 172 return; 173 } 174 } 175 176 memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_ops, 177 d, "mioe3680_pci-sja1", MIOe3680_PCI_SJA_RANGE); 178 memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_ops, 179 d, "mioe3680_pci-sja2", MIOe3680_PCI_SJA_RANGE); 180 181 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 182 pci_register_bar(&d->dev, /*BAR*/ i, PCI_BASE_ADDRESS_SPACE_IO, 183 &d->sja_io[i]); 184 } 185 } 186 187 static void mioe3680_pci_exit(PCIDevice *pci_dev) 188 { 189 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); 190 int i; 191 192 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 193 can_sja_disconnect(&d->sja_state[i]); 194 } 195 196 qemu_free_irq(d->irq); 197 } 198 199 static const VMStateDescription vmstate_mioe3680_pci = { 200 .name = "mioe3680_pci", 201 .version_id = 1, 202 .minimum_version_id = 1, 203 .minimum_version_id_old = 1, 204 .fields = (VMStateField[]) { 205 VMSTATE_PCI_DEVICE(dev, Mioe3680PCIState), 206 VMSTATE_STRUCT(sja_state[0], Mioe3680PCIState, 0, vmstate_can_sja, 207 CanSJA1000State), 208 VMSTATE_STRUCT(sja_state[1], Mioe3680PCIState, 0, vmstate_can_sja, 209 CanSJA1000State), 210 VMSTATE_END_OF_LIST() 211 } 212 }; 213 214 static void mioe3680_pci_instance_init(Object *obj) 215 { 216 Mioe3680PCIState *d = MIOe3680_PCI_DEV(obj); 217 218 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 219 (Object **)&d->canbus[0], 220 qdev_prop_allow_set_link_before_realize, 221 0, &error_abort); 222 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 223 (Object **)&d->canbus[1], 224 qdev_prop_allow_set_link_before_realize, 225 0, &error_abort); 226 } 227 228 static void mioe3680_pci_class_init(ObjectClass *klass, void *data) 229 { 230 DeviceClass *dc = DEVICE_CLASS(klass); 231 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 232 233 k->realize = mioe3680_pci_realize; 234 k->exit = mioe3680_pci_exit; 235 k->vendor_id = MIOe3680_PCI_VENDOR_ID1; 236 k->device_id = MIOe3680_PCI_DEVICE_ID1; 237 k->revision = 0x00; 238 k->class_id = 0x000c09; 239 k->subsystem_vendor_id = MIOe3680_PCI_VENDOR_ID1; 240 k->subsystem_id = MIOe3680_PCI_DEVICE_ID1; 241 dc->desc = "Mioe3680 PCICANx"; 242 dc->vmsd = &vmstate_mioe3680_pci; 243 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 244 dc->reset = mioe3680_pci_reset; 245 } 246 247 static const TypeInfo mioe3680_pci_info = { 248 .name = TYPE_CAN_PCI_DEV, 249 .parent = TYPE_PCI_DEVICE, 250 .instance_size = sizeof(Mioe3680PCIState), 251 .class_init = mioe3680_pci_class_init, 252 .instance_init = mioe3680_pci_instance_init, 253 .interfaces = (InterfaceInfo[]) { 254 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 255 { }, 256 }, 257 }; 258 259 static void mioe3680_pci_register_types(void) 260 { 261 type_register_static(&mioe3680_pci_info); 262 } 263 264 type_init(mioe3680_pci_register_types) 265