1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 31 //#define DEBUG_SONIC 32 33 #define SONIC_PROM_SIZE 0x1000 34 35 #ifdef DEBUG_SONIC 36 #define DPRINTF(fmt, ...) \ 37 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 38 static const char* reg_names[] = { 39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 47 #else 48 #define DPRINTF(fmt, ...) do {} while (0) 49 #endif 50 51 #define SONIC_ERROR(fmt, ...) \ 52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 53 54 #define SONIC_CR 0x00 55 #define SONIC_DCR 0x01 56 #define SONIC_RCR 0x02 57 #define SONIC_TCR 0x03 58 #define SONIC_IMR 0x04 59 #define SONIC_ISR 0x05 60 #define SONIC_UTDA 0x06 61 #define SONIC_CTDA 0x07 62 #define SONIC_TPS 0x08 63 #define SONIC_TFC 0x09 64 #define SONIC_TSA0 0x0a 65 #define SONIC_TSA1 0x0b 66 #define SONIC_TFS 0x0c 67 #define SONIC_URDA 0x0d 68 #define SONIC_CRDA 0x0e 69 #define SONIC_CRBA0 0x0f 70 #define SONIC_CRBA1 0x10 71 #define SONIC_RBWC0 0x11 72 #define SONIC_RBWC1 0x12 73 #define SONIC_EOBC 0x13 74 #define SONIC_URRA 0x14 75 #define SONIC_RSA 0x15 76 #define SONIC_REA 0x16 77 #define SONIC_RRP 0x17 78 #define SONIC_RWP 0x18 79 #define SONIC_TRBA0 0x19 80 #define SONIC_TRBA1 0x1a 81 #define SONIC_LLFA 0x1f 82 #define SONIC_TTDA 0x20 83 #define SONIC_CEP 0x21 84 #define SONIC_CAP2 0x22 85 #define SONIC_CAP1 0x23 86 #define SONIC_CAP0 0x24 87 #define SONIC_CE 0x25 88 #define SONIC_CDP 0x26 89 #define SONIC_CDC 0x27 90 #define SONIC_SR 0x28 91 #define SONIC_WT0 0x29 92 #define SONIC_WT1 0x2a 93 #define SONIC_RSC 0x2b 94 #define SONIC_CRCT 0x2c 95 #define SONIC_FAET 0x2d 96 #define SONIC_MPT 0x2e 97 #define SONIC_MDT 0x2f 98 #define SONIC_DCR2 0x3f 99 100 #define SONIC_CR_HTX 0x0001 101 #define SONIC_CR_TXP 0x0002 102 #define SONIC_CR_RXDIS 0x0004 103 #define SONIC_CR_RXEN 0x0008 104 #define SONIC_CR_STP 0x0010 105 #define SONIC_CR_ST 0x0020 106 #define SONIC_CR_RST 0x0080 107 #define SONIC_CR_RRRA 0x0100 108 #define SONIC_CR_LCAM 0x0200 109 #define SONIC_CR_MASK 0x03bf 110 111 #define SONIC_DCR_DW 0x0020 112 #define SONIC_DCR_LBR 0x2000 113 #define SONIC_DCR_EXBUS 0x8000 114 115 #define SONIC_RCR_PRX 0x0001 116 #define SONIC_RCR_LBK 0x0002 117 #define SONIC_RCR_FAER 0x0004 118 #define SONIC_RCR_CRCR 0x0008 119 #define SONIC_RCR_CRS 0x0020 120 #define SONIC_RCR_LPKT 0x0040 121 #define SONIC_RCR_BC 0x0080 122 #define SONIC_RCR_MC 0x0100 123 #define SONIC_RCR_LB0 0x0200 124 #define SONIC_RCR_LB1 0x0400 125 #define SONIC_RCR_AMC 0x0800 126 #define SONIC_RCR_PRO 0x1000 127 #define SONIC_RCR_BRD 0x2000 128 #define SONIC_RCR_RNT 0x4000 129 130 #define SONIC_TCR_PTX 0x0001 131 #define SONIC_TCR_BCM 0x0002 132 #define SONIC_TCR_FU 0x0004 133 #define SONIC_TCR_EXC 0x0040 134 #define SONIC_TCR_CRSL 0x0080 135 #define SONIC_TCR_NCRS 0x0100 136 #define SONIC_TCR_EXD 0x0400 137 #define SONIC_TCR_CRCI 0x2000 138 #define SONIC_TCR_PINT 0x8000 139 140 #define SONIC_ISR_RBE 0x0020 141 #define SONIC_ISR_RDE 0x0040 142 #define SONIC_ISR_TC 0x0080 143 #define SONIC_ISR_TXDN 0x0200 144 #define SONIC_ISR_PKTRX 0x0400 145 #define SONIC_ISR_PINT 0x0800 146 #define SONIC_ISR_LCD 0x1000 147 148 #define TYPE_DP8393X "dp8393x" 149 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 150 151 typedef struct dp8393xState { 152 SysBusDevice parent_obj; 153 154 /* Hardware */ 155 uint8_t it_shift; 156 bool big_endian; 157 qemu_irq irq; 158 #ifdef DEBUG_SONIC 159 int irq_level; 160 #endif 161 QEMUTimer *watchdog; 162 int64_t wt_last_update; 163 NICConf conf; 164 NICState *nic; 165 MemoryRegion mmio; 166 MemoryRegion prom; 167 168 /* Registers */ 169 uint8_t cam[16][6]; 170 uint16_t regs[0x40]; 171 172 /* Temporaries */ 173 uint8_t tx_buffer[0x10000]; 174 uint16_t data[12]; 175 int loopback_packet; 176 177 /* Memory access */ 178 MemoryRegion *dma_mr; 179 AddressSpace as; 180 } dp8393xState; 181 182 /* Accessor functions for values which are formed by 183 * concatenating two 16 bit device registers. By putting these 184 * in their own functions with a uint32_t return type we avoid the 185 * pitfall of implicit sign extension where ((x << 16) | y) is a 186 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 187 */ 188 static uint32_t dp8393x_cdp(dp8393xState *s) 189 { 190 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 191 } 192 193 static uint32_t dp8393x_crba(dp8393xState *s) 194 { 195 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 196 } 197 198 static uint32_t dp8393x_crda(dp8393xState *s) 199 { 200 return (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]; 201 } 202 203 static uint32_t dp8393x_rbwc(dp8393xState *s) 204 { 205 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 206 } 207 208 static uint32_t dp8393x_rrp(dp8393xState *s) 209 { 210 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 211 } 212 213 static uint32_t dp8393x_tsa(dp8393xState *s) 214 { 215 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 216 } 217 218 static uint32_t dp8393x_ttda(dp8393xState *s) 219 { 220 return (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]; 221 } 222 223 static uint32_t dp8393x_wt(dp8393xState *s) 224 { 225 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 226 } 227 228 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 229 { 230 uint16_t val; 231 232 if (s->big_endian) { 233 val = be16_to_cpu(s->data[offset * width + width - 1]); 234 } else { 235 val = le16_to_cpu(s->data[offset * width]); 236 } 237 return val; 238 } 239 240 static void dp8393x_put(dp8393xState *s, int width, int offset, 241 uint16_t val) 242 { 243 if (s->big_endian) { 244 s->data[offset * width + width - 1] = cpu_to_be16(val); 245 } else { 246 s->data[offset * width] = cpu_to_le16(val); 247 } 248 } 249 250 static void dp8393x_update_irq(dp8393xState *s) 251 { 252 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 253 254 #ifdef DEBUG_SONIC 255 if (level != s->irq_level) { 256 s->irq_level = level; 257 if (level) { 258 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 259 } else { 260 DPRINTF("lower irq\n"); 261 } 262 } 263 #endif 264 265 qemu_set_irq(s->irq, level); 266 } 267 268 static void dp8393x_do_load_cam(dp8393xState *s) 269 { 270 int width, size; 271 uint16_t index = 0; 272 273 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 274 size = sizeof(uint16_t) * 4 * width; 275 276 while (s->regs[SONIC_CDC] & 0x1f) { 277 /* Fill current entry */ 278 address_space_rw(&s->as, dp8393x_cdp(s), 279 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 280 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 281 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 282 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 283 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 284 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 285 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 286 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 287 s->cam[index][0], s->cam[index][1], s->cam[index][2], 288 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 289 /* Move to next entry */ 290 s->regs[SONIC_CDC]--; 291 s->regs[SONIC_CDP] += size; 292 index++; 293 } 294 295 /* Read CAM enable */ 296 address_space_rw(&s->as, dp8393x_cdp(s), 297 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 298 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 299 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 300 301 /* Done */ 302 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 303 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 304 dp8393x_update_irq(s); 305 } 306 307 static void dp8393x_do_read_rra(dp8393xState *s) 308 { 309 int width, size; 310 311 /* Read memory */ 312 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 313 size = sizeof(uint16_t) * 4 * width; 314 address_space_rw(&s->as, dp8393x_rrp(s), 315 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 316 317 /* Update SONIC registers */ 318 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 319 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 320 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 321 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 322 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 323 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 324 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 325 326 /* Go to next entry */ 327 s->regs[SONIC_RRP] += size; 328 329 /* Handle wrap */ 330 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 331 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 332 } 333 334 /* Check resource exhaustion */ 335 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 336 { 337 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 338 dp8393x_update_irq(s); 339 } 340 341 /* Done */ 342 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 343 } 344 345 static void dp8393x_do_software_reset(dp8393xState *s) 346 { 347 timer_del(s->watchdog); 348 349 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 350 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 351 } 352 353 static void dp8393x_set_next_tick(dp8393xState *s) 354 { 355 uint32_t ticks; 356 int64_t delay; 357 358 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 359 timer_del(s->watchdog); 360 return; 361 } 362 363 ticks = dp8393x_wt(s); 364 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 365 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 366 timer_mod(s->watchdog, s->wt_last_update + delay); 367 } 368 369 static void dp8393x_update_wt_regs(dp8393xState *s) 370 { 371 int64_t elapsed; 372 uint32_t val; 373 374 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 375 timer_del(s->watchdog); 376 return; 377 } 378 379 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 380 val = dp8393x_wt(s); 381 val -= elapsed / 5000000; 382 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 383 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 384 dp8393x_set_next_tick(s); 385 386 } 387 388 static void dp8393x_do_start_timer(dp8393xState *s) 389 { 390 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 391 dp8393x_set_next_tick(s); 392 } 393 394 static void dp8393x_do_stop_timer(dp8393xState *s) 395 { 396 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 397 dp8393x_update_wt_regs(s); 398 } 399 400 static int dp8393x_can_receive(NetClientState *nc); 401 402 static void dp8393x_do_receiver_enable(dp8393xState *s) 403 { 404 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 405 if (dp8393x_can_receive(s->nic->ncs)) { 406 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 407 } 408 } 409 410 static void dp8393x_do_receiver_disable(dp8393xState *s) 411 { 412 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 413 } 414 415 static void dp8393x_do_transmit_packets(dp8393xState *s) 416 { 417 NetClientState *nc = qemu_get_queue(s->nic); 418 int width, size; 419 int tx_len, len; 420 uint16_t i; 421 422 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 423 424 while (1) { 425 /* Read memory */ 426 size = sizeof(uint16_t) * 6 * width; 427 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 428 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 429 address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 430 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 431 tx_len = 0; 432 433 /* Update registers */ 434 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 435 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 436 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 437 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 438 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 439 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 440 441 /* Handle programmable interrupt */ 442 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 443 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 444 } else { 445 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 446 } 447 448 for (i = 0; i < s->regs[SONIC_TFC]; ) { 449 /* Append fragment */ 450 len = s->regs[SONIC_TFS]; 451 if (tx_len + len > sizeof(s->tx_buffer)) { 452 len = sizeof(s->tx_buffer) - tx_len; 453 } 454 address_space_rw(&s->as, dp8393x_tsa(s), 455 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0); 456 tx_len += len; 457 458 i++; 459 if (i != s->regs[SONIC_TFC]) { 460 /* Read next fragment details */ 461 size = sizeof(uint16_t) * 3 * width; 462 address_space_rw(&s->as, 463 dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width, 464 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 465 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 466 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 467 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 468 } 469 } 470 471 /* Handle Ethernet checksum */ 472 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 473 /* Don't append FCS there, to look like slirp packets 474 * which don't have one */ 475 } else { 476 /* Remove existing FCS */ 477 tx_len -= 4; 478 } 479 480 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 481 /* Loopback */ 482 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 483 if (nc->info->can_receive(nc)) { 484 s->loopback_packet = 1; 485 nc->info->receive(nc, s->tx_buffer, tx_len); 486 } 487 } else { 488 /* Transmit packet */ 489 qemu_send_packet(nc, s->tx_buffer, tx_len); 490 } 491 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 492 493 /* Write status */ 494 dp8393x_put(s, width, 0, 495 s->regs[SONIC_TCR] & 0x0fff); /* status */ 496 size = sizeof(uint16_t) * width; 497 address_space_rw(&s->as, 498 dp8393x_ttda(s), 499 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); 500 501 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 502 /* Read footer of packet */ 503 size = sizeof(uint16_t) * width; 504 address_space_rw(&s->as, 505 dp8393x_ttda(s) + 506 sizeof(uint16_t) * 507 (4 + 3 * s->regs[SONIC_TFC]) * width, 508 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 509 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; 510 if (dp8393x_get(s, width, 0) & 0x1) { 511 /* EOL detected */ 512 break; 513 } 514 } 515 } 516 517 /* Done */ 518 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 519 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 520 dp8393x_update_irq(s); 521 } 522 523 static void dp8393x_do_halt_transmission(dp8393xState *s) 524 { 525 /* Nothing to do */ 526 } 527 528 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 529 { 530 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 531 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 532 return; 533 } 534 535 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 536 537 if (command & SONIC_CR_HTX) 538 dp8393x_do_halt_transmission(s); 539 if (command & SONIC_CR_TXP) 540 dp8393x_do_transmit_packets(s); 541 if (command & SONIC_CR_RXDIS) 542 dp8393x_do_receiver_disable(s); 543 if (command & SONIC_CR_RXEN) 544 dp8393x_do_receiver_enable(s); 545 if (command & SONIC_CR_STP) 546 dp8393x_do_stop_timer(s); 547 if (command & SONIC_CR_ST) 548 dp8393x_do_start_timer(s); 549 if (command & SONIC_CR_RST) 550 dp8393x_do_software_reset(s); 551 if (command & SONIC_CR_RRRA) 552 dp8393x_do_read_rra(s); 553 if (command & SONIC_CR_LCAM) 554 dp8393x_do_load_cam(s); 555 } 556 557 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 558 { 559 dp8393xState *s = opaque; 560 int reg = addr >> s->it_shift; 561 uint16_t val = 0; 562 563 switch (reg) { 564 /* Update data before reading it */ 565 case SONIC_WT0: 566 case SONIC_WT1: 567 dp8393x_update_wt_regs(s); 568 val = s->regs[reg]; 569 break; 570 /* Accept read to some registers only when in reset mode */ 571 case SONIC_CAP2: 572 case SONIC_CAP1: 573 case SONIC_CAP0: 574 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 575 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 576 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 577 } 578 break; 579 /* All other registers have no special contrainst */ 580 default: 581 val = s->regs[reg]; 582 } 583 584 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 585 586 return val; 587 } 588 589 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 590 unsigned int size) 591 { 592 dp8393xState *s = opaque; 593 int reg = addr >> s->it_shift; 594 595 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]); 596 597 switch (reg) { 598 /* Command register */ 599 case SONIC_CR: 600 dp8393x_do_command(s, data); 601 break; 602 /* Prevent write to read-only registers */ 603 case SONIC_CAP2: 604 case SONIC_CAP1: 605 case SONIC_CAP0: 606 case SONIC_SR: 607 case SONIC_MDT: 608 DPRINTF("writing to reg %d invalid\n", reg); 609 break; 610 /* Accept write to some registers only when in reset mode */ 611 case SONIC_DCR: 612 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 613 s->regs[reg] = data & 0xbfff; 614 } else { 615 DPRINTF("writing to DCR invalid\n"); 616 } 617 break; 618 case SONIC_DCR2: 619 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 620 s->regs[reg] = data & 0xf017; 621 } else { 622 DPRINTF("writing to DCR2 invalid\n"); 623 } 624 break; 625 /* 12 lower bytes are Read Only */ 626 case SONIC_TCR: 627 s->regs[reg] = data & 0xf000; 628 break; 629 /* 9 lower bytes are Read Only */ 630 case SONIC_RCR: 631 s->regs[reg] = data & 0xffe0; 632 break; 633 /* Ignore most significant bit */ 634 case SONIC_IMR: 635 s->regs[reg] = data & 0x7fff; 636 dp8393x_update_irq(s); 637 break; 638 /* Clear bits by writing 1 to them */ 639 case SONIC_ISR: 640 data &= s->regs[reg]; 641 s->regs[reg] &= ~data; 642 if (data & SONIC_ISR_RBE) { 643 dp8393x_do_read_rra(s); 644 } 645 dp8393x_update_irq(s); 646 if (dp8393x_can_receive(s->nic->ncs)) { 647 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 648 } 649 break; 650 /* Ignore least significant bit */ 651 case SONIC_RSA: 652 case SONIC_REA: 653 case SONIC_RRP: 654 case SONIC_RWP: 655 s->regs[reg] = data & 0xfffe; 656 break; 657 /* Invert written value for some registers */ 658 case SONIC_CRCT: 659 case SONIC_FAET: 660 case SONIC_MPT: 661 s->regs[reg] = data ^ 0xffff; 662 break; 663 /* All other registers have no special contrainst */ 664 default: 665 s->regs[reg] = data; 666 } 667 668 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 669 dp8393x_set_next_tick(s); 670 } 671 } 672 673 static const MemoryRegionOps dp8393x_ops = { 674 .read = dp8393x_read, 675 .write = dp8393x_write, 676 .impl.min_access_size = 2, 677 .impl.max_access_size = 2, 678 .endianness = DEVICE_NATIVE_ENDIAN, 679 }; 680 681 static void dp8393x_watchdog(void *opaque) 682 { 683 dp8393xState *s = opaque; 684 685 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 686 return; 687 } 688 689 s->regs[SONIC_WT1] = 0xffff; 690 s->regs[SONIC_WT0] = 0xffff; 691 dp8393x_set_next_tick(s); 692 693 /* Signal underflow */ 694 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 695 dp8393x_update_irq(s); 696 } 697 698 static int dp8393x_can_receive(NetClientState *nc) 699 { 700 dp8393xState *s = qemu_get_nic_opaque(nc); 701 702 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 703 return 0; 704 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 705 return 0; 706 return 1; 707 } 708 709 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 710 int size) 711 { 712 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 713 int i; 714 715 /* Check promiscuous mode */ 716 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 717 return 0; 718 } 719 720 /* Check multicast packets */ 721 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 722 return SONIC_RCR_MC; 723 } 724 725 /* Check broadcast */ 726 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 727 return SONIC_RCR_BC; 728 } 729 730 /* Check CAM */ 731 for (i = 0; i < 16; i++) { 732 if (s->regs[SONIC_CE] & (1 << i)) { 733 /* Entry enabled */ 734 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 735 return 0; 736 } 737 } 738 } 739 740 return -1; 741 } 742 743 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 744 size_t size) 745 { 746 dp8393xState *s = qemu_get_nic_opaque(nc); 747 int packet_type; 748 uint32_t available, address; 749 int width, rx_len = size; 750 uint32_t checksum; 751 752 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 753 754 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 755 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 756 757 packet_type = dp8393x_receive_filter(s, buf, size); 758 if (packet_type < 0) { 759 DPRINTF("packet not for netcard\n"); 760 return -1; 761 } 762 763 /* XXX: Check byte ordering */ 764 765 /* Check for EOL */ 766 if (s->regs[SONIC_LLFA] & 0x1) { 767 /* Are we still in resource exhaustion? */ 768 size = sizeof(uint16_t) * 1 * width; 769 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 770 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 771 (uint8_t *)s->data, size, 0); 772 if (dp8393x_get(s, width, 0) & 0x1) { 773 /* Still EOL ; stop reception */ 774 return -1; 775 } else { 776 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 777 } 778 } 779 780 /* Save current position */ 781 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 782 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 783 784 /* Calculate the ethernet checksum */ 785 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 786 787 /* Put packet into RBA */ 788 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); 789 address = dp8393x_crba(s); 790 address_space_rw(&s->as, address, 791 MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1); 792 address += rx_len; 793 address_space_rw(&s->as, address, 794 MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); 795 rx_len += 4; 796 s->regs[SONIC_CRBA1] = address >> 16; 797 s->regs[SONIC_CRBA0] = address & 0xffff; 798 available = dp8393x_rbwc(s); 799 available -= rx_len / 2; 800 s->regs[SONIC_RBWC1] = available >> 16; 801 s->regs[SONIC_RBWC0] = available & 0xffff; 802 803 /* Update status */ 804 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 805 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 806 } 807 s->regs[SONIC_RCR] |= packet_type; 808 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 809 if (s->loopback_packet) { 810 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 811 s->loopback_packet = 0; 812 } 813 814 /* Write status to memory */ 815 DPRINTF("Write status at %08x\n", dp8393x_crda(s)); 816 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 817 dp8393x_put(s, width, 1, rx_len); /* byte count */ 818 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 819 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 820 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 821 size = sizeof(uint16_t) * 5 * width; 822 address_space_rw(&s->as, dp8393x_crda(s), 823 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); 824 825 /* Move to next descriptor */ 826 size = sizeof(uint16_t) * width; 827 address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 828 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 829 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 830 if (s->regs[SONIC_LLFA] & 0x1) { 831 /* EOL detected */ 832 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 833 } else { 834 /* Clear in_use, but it is always 16bit wide */ 835 int offset = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 836 if (s->big_endian && width == 2) { 837 /* we need to adjust the offset of the 16bit field */ 838 offset += sizeof(uint16_t); 839 } 840 s->data[0] = 0; 841 address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED, 842 (uint8_t *)s->data, sizeof(uint16_t), 1); 843 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 844 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 845 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 846 847 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 848 /* Read next RRA */ 849 dp8393x_do_read_rra(s); 850 } 851 } 852 853 /* Done */ 854 dp8393x_update_irq(s); 855 856 return size; 857 } 858 859 static void dp8393x_reset(DeviceState *dev) 860 { 861 dp8393xState *s = DP8393X(dev); 862 timer_del(s->watchdog); 863 864 memset(s->regs, 0, sizeof(s->regs)); 865 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 866 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 867 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 868 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 869 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 870 s->regs[SONIC_IMR] = 0; 871 s->regs[SONIC_ISR] = 0; 872 s->regs[SONIC_DCR2] = 0; 873 s->regs[SONIC_EOBC] = 0x02F8; 874 s->regs[SONIC_RSC] = 0; 875 s->regs[SONIC_CE] = 0; 876 s->regs[SONIC_RSC] = 0; 877 878 /* Network cable is connected */ 879 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 880 881 dp8393x_update_irq(s); 882 } 883 884 static NetClientInfo net_dp83932_info = { 885 .type = NET_CLIENT_DRIVER_NIC, 886 .size = sizeof(NICState), 887 .can_receive = dp8393x_can_receive, 888 .receive = dp8393x_receive, 889 }; 890 891 static void dp8393x_instance_init(Object *obj) 892 { 893 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 894 dp8393xState *s = DP8393X(obj); 895 896 sysbus_init_mmio(sbd, &s->mmio); 897 sysbus_init_mmio(sbd, &s->prom); 898 sysbus_init_irq(sbd, &s->irq); 899 } 900 901 static void dp8393x_realize(DeviceState *dev, Error **errp) 902 { 903 dp8393xState *s = DP8393X(dev); 904 int i, checksum; 905 uint8_t *prom; 906 Error *local_err = NULL; 907 908 address_space_init(&s->as, s->dma_mr, "dp8393x"); 909 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 910 "dp8393x-regs", 0x40 << s->it_shift); 911 912 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 913 object_get_typename(OBJECT(dev)), dev->id, s); 914 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 915 916 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 917 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 918 919 memory_region_init_ram(&s->prom, OBJECT(dev), 920 "dp8393x-prom", SONIC_PROM_SIZE, &local_err); 921 if (local_err) { 922 error_propagate(errp, local_err); 923 return; 924 } 925 memory_region_set_readonly(&s->prom, true); 926 prom = memory_region_get_ram_ptr(&s->prom); 927 checksum = 0; 928 for (i = 0; i < 6; i++) { 929 prom[i] = s->conf.macaddr.a[i]; 930 checksum += prom[i]; 931 if (checksum > 0xff) { 932 checksum = (checksum + 1) & 0xff; 933 } 934 } 935 prom[7] = 0xff - checksum; 936 } 937 938 static const VMStateDescription vmstate_dp8393x = { 939 .name = "dp8393x", 940 .version_id = 0, 941 .minimum_version_id = 0, 942 .fields = (VMStateField []) { 943 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 944 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 945 VMSTATE_END_OF_LIST() 946 } 947 }; 948 949 static Property dp8393x_properties[] = { 950 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 951 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 952 TYPE_MEMORY_REGION, MemoryRegion *), 953 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 954 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 955 DEFINE_PROP_END_OF_LIST(), 956 }; 957 958 static void dp8393x_class_init(ObjectClass *klass, void *data) 959 { 960 DeviceClass *dc = DEVICE_CLASS(klass); 961 962 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 963 dc->realize = dp8393x_realize; 964 dc->reset = dp8393x_reset; 965 dc->vmsd = &vmstate_dp8393x; 966 device_class_set_props(dc, dp8393x_properties); 967 } 968 969 static const TypeInfo dp8393x_info = { 970 .name = TYPE_DP8393X, 971 .parent = TYPE_SYS_BUS_DEVICE, 972 .instance_size = sizeof(dp8393xState), 973 .instance_init = dp8393x_instance_init, 974 .class_init = dp8393x_class_init, 975 }; 976 977 static void dp8393x_register_types(void) 978 { 979 type_register_static(&dp8393x_info); 980 } 981 982 type_init(dp8393x_register_types) 983