1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "hw/sysbus.h" 21 #include "hw/devices.h" 22 #include "net/net.h" 23 #include "qemu/timer.h" 24 #include <zlib.h> 25 26 //#define DEBUG_SONIC 27 28 #define SONIC_PROM_SIZE 0x1000 29 30 #ifdef DEBUG_SONIC 31 #define DPRINTF(fmt, ...) \ 32 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 33 static const char* reg_names[] = { 34 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 35 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 36 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 37 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 38 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 39 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 40 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 41 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 42 #else 43 #define DPRINTF(fmt, ...) do {} while (0) 44 #endif 45 46 #define SONIC_ERROR(fmt, ...) \ 47 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 48 49 #define SONIC_CR 0x00 50 #define SONIC_DCR 0x01 51 #define SONIC_RCR 0x02 52 #define SONIC_TCR 0x03 53 #define SONIC_IMR 0x04 54 #define SONIC_ISR 0x05 55 #define SONIC_UTDA 0x06 56 #define SONIC_CTDA 0x07 57 #define SONIC_TPS 0x08 58 #define SONIC_TFC 0x09 59 #define SONIC_TSA0 0x0a 60 #define SONIC_TSA1 0x0b 61 #define SONIC_TFS 0x0c 62 #define SONIC_URDA 0x0d 63 #define SONIC_CRDA 0x0e 64 #define SONIC_CRBA0 0x0f 65 #define SONIC_CRBA1 0x10 66 #define SONIC_RBWC0 0x11 67 #define SONIC_RBWC1 0x12 68 #define SONIC_EOBC 0x13 69 #define SONIC_URRA 0x14 70 #define SONIC_RSA 0x15 71 #define SONIC_REA 0x16 72 #define SONIC_RRP 0x17 73 #define SONIC_RWP 0x18 74 #define SONIC_TRBA0 0x19 75 #define SONIC_TRBA1 0x1a 76 #define SONIC_LLFA 0x1f 77 #define SONIC_TTDA 0x20 78 #define SONIC_CEP 0x21 79 #define SONIC_CAP2 0x22 80 #define SONIC_CAP1 0x23 81 #define SONIC_CAP0 0x24 82 #define SONIC_CE 0x25 83 #define SONIC_CDP 0x26 84 #define SONIC_CDC 0x27 85 #define SONIC_SR 0x28 86 #define SONIC_WT0 0x29 87 #define SONIC_WT1 0x2a 88 #define SONIC_RSC 0x2b 89 #define SONIC_CRCT 0x2c 90 #define SONIC_FAET 0x2d 91 #define SONIC_MPT 0x2e 92 #define SONIC_MDT 0x2f 93 #define SONIC_DCR2 0x3f 94 95 #define SONIC_CR_HTX 0x0001 96 #define SONIC_CR_TXP 0x0002 97 #define SONIC_CR_RXDIS 0x0004 98 #define SONIC_CR_RXEN 0x0008 99 #define SONIC_CR_STP 0x0010 100 #define SONIC_CR_ST 0x0020 101 #define SONIC_CR_RST 0x0080 102 #define SONIC_CR_RRRA 0x0100 103 #define SONIC_CR_LCAM 0x0200 104 #define SONIC_CR_MASK 0x03bf 105 106 #define SONIC_DCR_DW 0x0020 107 #define SONIC_DCR_LBR 0x2000 108 #define SONIC_DCR_EXBUS 0x8000 109 110 #define SONIC_RCR_PRX 0x0001 111 #define SONIC_RCR_LBK 0x0002 112 #define SONIC_RCR_FAER 0x0004 113 #define SONIC_RCR_CRCR 0x0008 114 #define SONIC_RCR_CRS 0x0020 115 #define SONIC_RCR_LPKT 0x0040 116 #define SONIC_RCR_BC 0x0080 117 #define SONIC_RCR_MC 0x0100 118 #define SONIC_RCR_LB0 0x0200 119 #define SONIC_RCR_LB1 0x0400 120 #define SONIC_RCR_AMC 0x0800 121 #define SONIC_RCR_PRO 0x1000 122 #define SONIC_RCR_BRD 0x2000 123 #define SONIC_RCR_RNT 0x4000 124 125 #define SONIC_TCR_PTX 0x0001 126 #define SONIC_TCR_BCM 0x0002 127 #define SONIC_TCR_FU 0x0004 128 #define SONIC_TCR_EXC 0x0040 129 #define SONIC_TCR_CRSL 0x0080 130 #define SONIC_TCR_NCRS 0x0100 131 #define SONIC_TCR_EXD 0x0400 132 #define SONIC_TCR_CRCI 0x2000 133 #define SONIC_TCR_PINT 0x8000 134 135 #define SONIC_ISR_RBE 0x0020 136 #define SONIC_ISR_RDE 0x0040 137 #define SONIC_ISR_TC 0x0080 138 #define SONIC_ISR_TXDN 0x0200 139 #define SONIC_ISR_PKTRX 0x0400 140 #define SONIC_ISR_PINT 0x0800 141 #define SONIC_ISR_LCD 0x1000 142 143 #define TYPE_DP8393X "dp8393x" 144 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 145 146 typedef struct dp8393xState { 147 SysBusDevice parent_obj; 148 149 /* Hardware */ 150 uint8_t it_shift; 151 qemu_irq irq; 152 #ifdef DEBUG_SONIC 153 int irq_level; 154 #endif 155 QEMUTimer *watchdog; 156 int64_t wt_last_update; 157 NICConf conf; 158 NICState *nic; 159 MemoryRegion mmio; 160 MemoryRegion prom; 161 162 /* Registers */ 163 uint8_t cam[16][6]; 164 uint16_t regs[0x40]; 165 166 /* Temporaries */ 167 uint8_t tx_buffer[0x10000]; 168 int loopback_packet; 169 170 /* Memory access */ 171 void *dma_mr; 172 AddressSpace as; 173 } dp8393xState; 174 175 static void dp8393x_update_irq(dp8393xState *s) 176 { 177 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 178 179 #ifdef DEBUG_SONIC 180 if (level != s->irq_level) { 181 s->irq_level = level; 182 if (level) { 183 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 184 } else { 185 DPRINTF("lower irq\n"); 186 } 187 } 188 #endif 189 190 qemu_set_irq(s->irq, level); 191 } 192 193 static void dp8393x_do_load_cam(dp8393xState *s) 194 { 195 uint16_t data[8]; 196 int width, size; 197 uint16_t index = 0; 198 199 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 200 size = sizeof(uint16_t) * 4 * width; 201 202 while (s->regs[SONIC_CDC] & 0x1f) { 203 /* Fill current entry */ 204 address_space_rw(&s->as, 205 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP], 206 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 207 s->cam[index][0] = data[1 * width] & 0xff; 208 s->cam[index][1] = data[1 * width] >> 8; 209 s->cam[index][2] = data[2 * width] & 0xff; 210 s->cam[index][3] = data[2 * width] >> 8; 211 s->cam[index][4] = data[3 * width] & 0xff; 212 s->cam[index][5] = data[3 * width] >> 8; 213 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 214 s->cam[index][0], s->cam[index][1], s->cam[index][2], 215 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 216 /* Move to next entry */ 217 s->regs[SONIC_CDC]--; 218 s->regs[SONIC_CDP] += size; 219 index++; 220 } 221 222 /* Read CAM enable */ 223 address_space_rw(&s->as, 224 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP], 225 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 226 s->regs[SONIC_CE] = data[0 * width]; 227 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 228 229 /* Done */ 230 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 231 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 232 dp8393x_update_irq(s); 233 } 234 235 static void dp8393x_do_read_rra(dp8393xState *s) 236 { 237 uint16_t data[8]; 238 int width, size; 239 240 /* Read memory */ 241 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 242 size = sizeof(uint16_t) * 4 * width; 243 address_space_rw(&s->as, 244 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP], 245 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 246 247 /* Update SONIC registers */ 248 s->regs[SONIC_CRBA0] = data[0 * width]; 249 s->regs[SONIC_CRBA1] = data[1 * width]; 250 s->regs[SONIC_RBWC0] = data[2 * width]; 251 s->regs[SONIC_RBWC1] = data[3 * width]; 252 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 253 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 254 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 255 256 /* Go to next entry */ 257 s->regs[SONIC_RRP] += size; 258 259 /* Handle wrap */ 260 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 261 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 262 } 263 264 /* Check resource exhaustion */ 265 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 266 { 267 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 268 dp8393x_update_irq(s); 269 } 270 271 /* Done */ 272 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 273 } 274 275 static void dp8393x_do_software_reset(dp8393xState *s) 276 { 277 timer_del(s->watchdog); 278 279 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 280 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 281 } 282 283 static void dp8393x_set_next_tick(dp8393xState *s) 284 { 285 uint32_t ticks; 286 int64_t delay; 287 288 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 289 timer_del(s->watchdog); 290 return; 291 } 292 293 ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 294 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 295 delay = get_ticks_per_sec() * ticks / 5000000; 296 timer_mod(s->watchdog, s->wt_last_update + delay); 297 } 298 299 static void dp8393x_update_wt_regs(dp8393xState *s) 300 { 301 int64_t elapsed; 302 uint32_t val; 303 304 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 305 timer_del(s->watchdog); 306 return; 307 } 308 309 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 310 val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 311 val -= elapsed / 5000000; 312 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 313 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 314 dp8393x_set_next_tick(s); 315 316 } 317 318 static void dp8393x_do_start_timer(dp8393xState *s) 319 { 320 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 321 dp8393x_set_next_tick(s); 322 } 323 324 static void dp8393x_do_stop_timer(dp8393xState *s) 325 { 326 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 327 dp8393x_update_wt_regs(s); 328 } 329 330 static void dp8393x_do_receiver_enable(dp8393xState *s) 331 { 332 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 333 } 334 335 static void dp8393x_do_receiver_disable(dp8393xState *s) 336 { 337 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 338 } 339 340 static void dp8393x_do_transmit_packets(dp8393xState *s) 341 { 342 NetClientState *nc = qemu_get_queue(s->nic); 343 uint16_t data[12]; 344 int width, size; 345 int tx_len, len; 346 uint16_t i; 347 348 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 349 350 while (1) { 351 /* Read memory */ 352 DPRINTF("Transmit packet at %08x\n", 353 (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_CTDA]); 354 size = sizeof(uint16_t) * 6 * width; 355 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 356 address_space_rw(&s->as, 357 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * width, 358 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 359 tx_len = 0; 360 361 /* Update registers */ 362 s->regs[SONIC_TCR] = data[0 * width] & 0xf000; 363 s->regs[SONIC_TPS] = data[1 * width]; 364 s->regs[SONIC_TFC] = data[2 * width]; 365 s->regs[SONIC_TSA0] = data[3 * width]; 366 s->regs[SONIC_TSA1] = data[4 * width]; 367 s->regs[SONIC_TFS] = data[5 * width]; 368 369 /* Handle programmable interrupt */ 370 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 371 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 372 } else { 373 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 374 } 375 376 for (i = 0; i < s->regs[SONIC_TFC]; ) { 377 /* Append fragment */ 378 len = s->regs[SONIC_TFS]; 379 if (tx_len + len > sizeof(s->tx_buffer)) { 380 len = sizeof(s->tx_buffer) - tx_len; 381 } 382 address_space_rw(&s->as, 383 (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0], 384 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0); 385 tx_len += len; 386 387 i++; 388 if (i != s->regs[SONIC_TFC]) { 389 /* Read next fragment details */ 390 size = sizeof(uint16_t) * 3 * width; 391 address_space_rw(&s->as, 392 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * i) * width, 393 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 394 s->regs[SONIC_TSA0] = data[0 * width]; 395 s->regs[SONIC_TSA1] = data[1 * width]; 396 s->regs[SONIC_TFS] = data[2 * width]; 397 } 398 } 399 400 /* Handle Ethernet checksum */ 401 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 402 /* Don't append FCS there, to look like slirp packets 403 * which don't have one */ 404 } else { 405 /* Remove existing FCS */ 406 tx_len -= 4; 407 } 408 409 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 410 /* Loopback */ 411 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 412 if (nc->info->can_receive(nc)) { 413 s->loopback_packet = 1; 414 nc->info->receive(nc, s->tx_buffer, tx_len); 415 } 416 } else { 417 /* Transmit packet */ 418 qemu_send_packet(nc, s->tx_buffer, tx_len); 419 } 420 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 421 422 /* Write status */ 423 data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */ 424 size = sizeof(uint16_t) * width; 425 address_space_rw(&s->as, 426 (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA], 427 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 428 429 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 430 /* Read footer of packet */ 431 size = sizeof(uint16_t) * width; 432 address_space_rw(&s->as, 433 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width, 434 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 435 s->regs[SONIC_CTDA] = data[0 * width] & ~0x1; 436 if (data[0 * width] & 0x1) { 437 /* EOL detected */ 438 break; 439 } 440 } 441 } 442 443 /* Done */ 444 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 445 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 446 dp8393x_update_irq(s); 447 } 448 449 static void dp8393x_do_halt_transmission(dp8393xState *s) 450 { 451 /* Nothing to do */ 452 } 453 454 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 455 { 456 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 457 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 458 return; 459 } 460 461 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 462 463 if (command & SONIC_CR_HTX) 464 dp8393x_do_halt_transmission(s); 465 if (command & SONIC_CR_TXP) 466 dp8393x_do_transmit_packets(s); 467 if (command & SONIC_CR_RXDIS) 468 dp8393x_do_receiver_disable(s); 469 if (command & SONIC_CR_RXEN) 470 dp8393x_do_receiver_enable(s); 471 if (command & SONIC_CR_STP) 472 dp8393x_do_stop_timer(s); 473 if (command & SONIC_CR_ST) 474 dp8393x_do_start_timer(s); 475 if (command & SONIC_CR_RST) 476 dp8393x_do_software_reset(s); 477 if (command & SONIC_CR_RRRA) 478 dp8393x_do_read_rra(s); 479 if (command & SONIC_CR_LCAM) 480 dp8393x_do_load_cam(s); 481 } 482 483 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 484 { 485 dp8393xState *s = opaque; 486 int reg = addr >> s->it_shift; 487 uint16_t val = 0; 488 489 switch (reg) { 490 /* Update data before reading it */ 491 case SONIC_WT0: 492 case SONIC_WT1: 493 dp8393x_update_wt_regs(s); 494 val = s->regs[reg]; 495 break; 496 /* Accept read to some registers only when in reset mode */ 497 case SONIC_CAP2: 498 case SONIC_CAP1: 499 case SONIC_CAP0: 500 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 501 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 502 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 503 } 504 break; 505 /* All other registers have no special contrainst */ 506 default: 507 val = s->regs[reg]; 508 } 509 510 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 511 512 return val; 513 } 514 515 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 516 unsigned int size) 517 { 518 dp8393xState *s = opaque; 519 int reg = addr >> s->it_shift; 520 521 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]); 522 523 switch (reg) { 524 /* Command register */ 525 case SONIC_CR: 526 dp8393x_do_command(s, data); 527 break; 528 /* Prevent write to read-only registers */ 529 case SONIC_CAP2: 530 case SONIC_CAP1: 531 case SONIC_CAP0: 532 case SONIC_SR: 533 case SONIC_MDT: 534 DPRINTF("writing to reg %d invalid\n", reg); 535 break; 536 /* Accept write to some registers only when in reset mode */ 537 case SONIC_DCR: 538 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 539 s->regs[reg] = data & 0xbfff; 540 } else { 541 DPRINTF("writing to DCR invalid\n"); 542 } 543 break; 544 case SONIC_DCR2: 545 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 546 s->regs[reg] = data & 0xf017; 547 } else { 548 DPRINTF("writing to DCR2 invalid\n"); 549 } 550 break; 551 /* 12 lower bytes are Read Only */ 552 case SONIC_TCR: 553 s->regs[reg] = data & 0xf000; 554 break; 555 /* 9 lower bytes are Read Only */ 556 case SONIC_RCR: 557 s->regs[reg] = data & 0xffe0; 558 break; 559 /* Ignore most significant bit */ 560 case SONIC_IMR: 561 s->regs[reg] = data & 0x7fff; 562 dp8393x_update_irq(s); 563 break; 564 /* Clear bits by writing 1 to them */ 565 case SONIC_ISR: 566 data &= s->regs[reg]; 567 s->regs[reg] &= ~data; 568 if (data & SONIC_ISR_RBE) { 569 dp8393x_do_read_rra(s); 570 } 571 dp8393x_update_irq(s); 572 break; 573 /* Ignore least significant bit */ 574 case SONIC_RSA: 575 case SONIC_REA: 576 case SONIC_RRP: 577 case SONIC_RWP: 578 s->regs[reg] = data & 0xfffe; 579 break; 580 /* Invert written value for some registers */ 581 case SONIC_CRCT: 582 case SONIC_FAET: 583 case SONIC_MPT: 584 s->regs[reg] = data ^ 0xffff; 585 break; 586 /* All other registers have no special contrainst */ 587 default: 588 s->regs[reg] = data; 589 } 590 591 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 592 dp8393x_set_next_tick(s); 593 } 594 } 595 596 static const MemoryRegionOps dp8393x_ops = { 597 .read = dp8393x_read, 598 .write = dp8393x_write, 599 .impl.min_access_size = 2, 600 .impl.max_access_size = 2, 601 .endianness = DEVICE_NATIVE_ENDIAN, 602 }; 603 604 static void dp8393x_watchdog(void *opaque) 605 { 606 dp8393xState *s = opaque; 607 608 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 609 return; 610 } 611 612 s->regs[SONIC_WT1] = 0xffff; 613 s->regs[SONIC_WT0] = 0xffff; 614 dp8393x_set_next_tick(s); 615 616 /* Signal underflow */ 617 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 618 dp8393x_update_irq(s); 619 } 620 621 static int dp8393x_can_receive(NetClientState *nc) 622 { 623 dp8393xState *s = qemu_get_nic_opaque(nc); 624 625 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 626 return 0; 627 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 628 return 0; 629 return 1; 630 } 631 632 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 633 int size) 634 { 635 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 636 int i; 637 638 /* Check for runt packet (remember that checksum is not there) */ 639 if (size < 64 - 4) { 640 return (s->regs[SONIC_RCR] & SONIC_RCR_RNT) ? 0 : -1; 641 } 642 643 /* Check promiscuous mode */ 644 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 645 return 0; 646 } 647 648 /* Check multicast packets */ 649 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 650 return SONIC_RCR_MC; 651 } 652 653 /* Check broadcast */ 654 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 655 return SONIC_RCR_BC; 656 } 657 658 /* Check CAM */ 659 for (i = 0; i < 16; i++) { 660 if (s->regs[SONIC_CE] & (1 << i)) { 661 /* Entry enabled */ 662 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 663 return 0; 664 } 665 } 666 } 667 668 return -1; 669 } 670 671 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 672 size_t size) 673 { 674 dp8393xState *s = qemu_get_nic_opaque(nc); 675 uint16_t data[10]; 676 int packet_type; 677 uint32_t available, address; 678 int width, rx_len = size; 679 uint32_t checksum; 680 681 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 682 683 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 684 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 685 686 packet_type = dp8393x_receive_filter(s, buf, size); 687 if (packet_type < 0) { 688 DPRINTF("packet not for netcard\n"); 689 return -1; 690 } 691 692 /* XXX: Check byte ordering */ 693 694 /* Check for EOL */ 695 if (s->regs[SONIC_LLFA] & 0x1) { 696 /* Are we still in resource exhaustion? */ 697 size = sizeof(uint16_t) * 1 * width; 698 address = ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width; 699 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 700 (uint8_t *)data, size, 0); 701 if (data[0 * width] & 0x1) { 702 /* Still EOL ; stop reception */ 703 return -1; 704 } else { 705 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 706 } 707 } 708 709 /* Save current position */ 710 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 711 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 712 713 /* Calculate the ethernet checksum */ 714 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 715 716 /* Put packet into RBA */ 717 DPRINTF("Receive packet at %08x\n", (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]); 718 address = (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 719 address_space_rw(&s->as, address, 720 MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1); 721 address += rx_len; 722 address_space_rw(&s->as, address, 723 MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); 724 rx_len += 4; 725 s->regs[SONIC_CRBA1] = address >> 16; 726 s->regs[SONIC_CRBA0] = address & 0xffff; 727 available = (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 728 available -= rx_len / 2; 729 s->regs[SONIC_RBWC1] = available >> 16; 730 s->regs[SONIC_RBWC0] = available & 0xffff; 731 732 /* Update status */ 733 if (((s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]) < s->regs[SONIC_EOBC]) { 734 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 735 } 736 s->regs[SONIC_RCR] |= packet_type; 737 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 738 if (s->loopback_packet) { 739 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 740 s->loopback_packet = 0; 741 } 742 743 /* Write status to memory */ 744 DPRINTF("Write status at %08x\n", (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]); 745 data[0 * width] = s->regs[SONIC_RCR]; /* status */ 746 data[1 * width] = rx_len; /* byte count */ 747 data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */ 748 data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */ 749 data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */ 750 size = sizeof(uint16_t) * 5 * width; 751 address_space_rw(&s->as, (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA], 752 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 753 754 /* Move to next descriptor */ 755 size = sizeof(uint16_t) * width; 756 address_space_rw(&s->as, 757 ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width, 758 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 759 s->regs[SONIC_LLFA] = data[0 * width]; 760 if (s->regs[SONIC_LLFA] & 0x1) { 761 /* EOL detected */ 762 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 763 } else { 764 data[0 * width] = 0; /* in_use */ 765 address_space_rw(&s->as, 766 ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 6 * width, 767 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1); 768 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 769 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 770 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 771 772 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 773 /* Read next RRA */ 774 dp8393x_do_read_rra(s); 775 } 776 } 777 778 /* Done */ 779 dp8393x_update_irq(s); 780 781 return size; 782 } 783 784 static void dp8393x_reset(DeviceState *dev) 785 { 786 dp8393xState *s = DP8393X(dev); 787 timer_del(s->watchdog); 788 789 memset(s->regs, 0, sizeof(s->regs)); 790 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 791 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 792 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 793 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 794 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 795 s->regs[SONIC_IMR] = 0; 796 s->regs[SONIC_ISR] = 0; 797 s->regs[SONIC_DCR2] = 0; 798 s->regs[SONIC_EOBC] = 0x02F8; 799 s->regs[SONIC_RSC] = 0; 800 s->regs[SONIC_CE] = 0; 801 s->regs[SONIC_RSC] = 0; 802 803 /* Network cable is connected */ 804 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 805 806 dp8393x_update_irq(s); 807 } 808 809 static NetClientInfo net_dp83932_info = { 810 .type = NET_CLIENT_OPTIONS_KIND_NIC, 811 .size = sizeof(NICState), 812 .can_receive = dp8393x_can_receive, 813 .receive = dp8393x_receive, 814 }; 815 816 static void dp8393x_instance_init(Object *obj) 817 { 818 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 819 dp8393xState *s = DP8393X(obj); 820 821 sysbus_init_mmio(sbd, &s->mmio); 822 sysbus_init_mmio(sbd, &s->prom); 823 sysbus_init_irq(sbd, &s->irq); 824 } 825 826 static void dp8393x_realize(DeviceState *dev, Error **errp) 827 { 828 dp8393xState *s = DP8393X(dev); 829 int i, checksum; 830 uint8_t *prom; 831 832 address_space_init(&s->as, s->dma_mr, "dp8393x"); 833 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 834 "dp8393x-regs", 0x40 << s->it_shift); 835 836 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 837 object_get_typename(OBJECT(dev)), dev->id, s); 838 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 839 840 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 841 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 842 843 memory_region_init_rom_device(&s->prom, OBJECT(dev), NULL, NULL, 844 "dp8393x-prom", SONIC_PROM_SIZE, NULL); 845 prom = memory_region_get_ram_ptr(&s->prom); 846 checksum = 0; 847 for (i = 0; i < 6; i++) { 848 prom[i] = s->conf.macaddr.a[i]; 849 checksum += prom[i]; 850 if (checksum > 0xff) { 851 checksum = (checksum + 1) & 0xff; 852 } 853 } 854 prom[7] = 0xff - checksum; 855 } 856 857 static const VMStateDescription vmstate_dp8393x = { 858 .name = "dp8393x", 859 .version_id = 0, 860 .minimum_version_id = 0, 861 .fields = (VMStateField []) { 862 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 863 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 864 VMSTATE_END_OF_LIST() 865 } 866 }; 867 868 static Property dp8393x_properties[] = { 869 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 870 DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr), 871 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 872 DEFINE_PROP_END_OF_LIST(), 873 }; 874 875 static void dp8393x_class_init(ObjectClass *klass, void *data) 876 { 877 DeviceClass *dc = DEVICE_CLASS(klass); 878 879 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 880 dc->realize = dp8393x_realize; 881 dc->reset = dp8393x_reset; 882 dc->vmsd = &vmstate_dp8393x; 883 dc->props = dp8393x_properties; 884 } 885 886 static const TypeInfo dp8393x_info = { 887 .name = TYPE_DP8393X, 888 .parent = TYPE_SYS_BUS_DEVICE, 889 .instance_size = sizeof(dp8393xState), 890 .instance_init = dp8393x_instance_init, 891 .class_init = dp8393x_class_init, 892 }; 893 894 static void dp8393x_register_types(void) 895 { 896 type_register_static(&dp8393x_info); 897 } 898 899 type_init(dp8393x_register_types) 900