1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 31 //#define DEBUG_SONIC 32 33 #define SONIC_PROM_SIZE 0x1000 34 35 #ifdef DEBUG_SONIC 36 #define DPRINTF(fmt, ...) \ 37 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 38 static const char* reg_names[] = { 39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 47 #else 48 #define DPRINTF(fmt, ...) do {} while (0) 49 #endif 50 51 #define SONIC_ERROR(fmt, ...) \ 52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 53 54 #define SONIC_CR 0x00 55 #define SONIC_DCR 0x01 56 #define SONIC_RCR 0x02 57 #define SONIC_TCR 0x03 58 #define SONIC_IMR 0x04 59 #define SONIC_ISR 0x05 60 #define SONIC_UTDA 0x06 61 #define SONIC_CTDA 0x07 62 #define SONIC_TPS 0x08 63 #define SONIC_TFC 0x09 64 #define SONIC_TSA0 0x0a 65 #define SONIC_TSA1 0x0b 66 #define SONIC_TFS 0x0c 67 #define SONIC_URDA 0x0d 68 #define SONIC_CRDA 0x0e 69 #define SONIC_CRBA0 0x0f 70 #define SONIC_CRBA1 0x10 71 #define SONIC_RBWC0 0x11 72 #define SONIC_RBWC1 0x12 73 #define SONIC_EOBC 0x13 74 #define SONIC_URRA 0x14 75 #define SONIC_RSA 0x15 76 #define SONIC_REA 0x16 77 #define SONIC_RRP 0x17 78 #define SONIC_RWP 0x18 79 #define SONIC_TRBA0 0x19 80 #define SONIC_TRBA1 0x1a 81 #define SONIC_LLFA 0x1f 82 #define SONIC_TTDA 0x20 83 #define SONIC_CEP 0x21 84 #define SONIC_CAP2 0x22 85 #define SONIC_CAP1 0x23 86 #define SONIC_CAP0 0x24 87 #define SONIC_CE 0x25 88 #define SONIC_CDP 0x26 89 #define SONIC_CDC 0x27 90 #define SONIC_SR 0x28 91 #define SONIC_WT0 0x29 92 #define SONIC_WT1 0x2a 93 #define SONIC_RSC 0x2b 94 #define SONIC_CRCT 0x2c 95 #define SONIC_FAET 0x2d 96 #define SONIC_MPT 0x2e 97 #define SONIC_MDT 0x2f 98 #define SONIC_DCR2 0x3f 99 100 #define SONIC_CR_HTX 0x0001 101 #define SONIC_CR_TXP 0x0002 102 #define SONIC_CR_RXDIS 0x0004 103 #define SONIC_CR_RXEN 0x0008 104 #define SONIC_CR_STP 0x0010 105 #define SONIC_CR_ST 0x0020 106 #define SONIC_CR_RST 0x0080 107 #define SONIC_CR_RRRA 0x0100 108 #define SONIC_CR_LCAM 0x0200 109 #define SONIC_CR_MASK 0x03bf 110 111 #define SONIC_DCR_DW 0x0020 112 #define SONIC_DCR_LBR 0x2000 113 #define SONIC_DCR_EXBUS 0x8000 114 115 #define SONIC_RCR_PRX 0x0001 116 #define SONIC_RCR_LBK 0x0002 117 #define SONIC_RCR_FAER 0x0004 118 #define SONIC_RCR_CRCR 0x0008 119 #define SONIC_RCR_CRS 0x0020 120 #define SONIC_RCR_LPKT 0x0040 121 #define SONIC_RCR_BC 0x0080 122 #define SONIC_RCR_MC 0x0100 123 #define SONIC_RCR_LB0 0x0200 124 #define SONIC_RCR_LB1 0x0400 125 #define SONIC_RCR_AMC 0x0800 126 #define SONIC_RCR_PRO 0x1000 127 #define SONIC_RCR_BRD 0x2000 128 #define SONIC_RCR_RNT 0x4000 129 130 #define SONIC_TCR_PTX 0x0001 131 #define SONIC_TCR_BCM 0x0002 132 #define SONIC_TCR_FU 0x0004 133 #define SONIC_TCR_EXC 0x0040 134 #define SONIC_TCR_CRSL 0x0080 135 #define SONIC_TCR_NCRS 0x0100 136 #define SONIC_TCR_EXD 0x0400 137 #define SONIC_TCR_CRCI 0x2000 138 #define SONIC_TCR_PINT 0x8000 139 140 #define SONIC_ISR_RBE 0x0020 141 #define SONIC_ISR_RDE 0x0040 142 #define SONIC_ISR_TC 0x0080 143 #define SONIC_ISR_TXDN 0x0200 144 #define SONIC_ISR_PKTRX 0x0400 145 #define SONIC_ISR_PINT 0x0800 146 #define SONIC_ISR_LCD 0x1000 147 148 #define TYPE_DP8393X "dp8393x" 149 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 150 151 typedef struct dp8393xState { 152 SysBusDevice parent_obj; 153 154 /* Hardware */ 155 uint8_t it_shift; 156 bool big_endian; 157 qemu_irq irq; 158 #ifdef DEBUG_SONIC 159 int irq_level; 160 #endif 161 QEMUTimer *watchdog; 162 int64_t wt_last_update; 163 NICConf conf; 164 NICState *nic; 165 MemoryRegion mmio; 166 MemoryRegion prom; 167 168 /* Registers */ 169 uint8_t cam[16][6]; 170 uint16_t regs[0x40]; 171 172 /* Temporaries */ 173 uint8_t tx_buffer[0x10000]; 174 uint16_t data[12]; 175 int loopback_packet; 176 177 /* Memory access */ 178 MemoryRegion *dma_mr; 179 AddressSpace as; 180 } dp8393xState; 181 182 /* Accessor functions for values which are formed by 183 * concatenating two 16 bit device registers. By putting these 184 * in their own functions with a uint32_t return type we avoid the 185 * pitfall of implicit sign extension where ((x << 16) | y) is a 186 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 187 */ 188 static uint32_t dp8393x_cdp(dp8393xState *s) 189 { 190 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 191 } 192 193 static uint32_t dp8393x_crba(dp8393xState *s) 194 { 195 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 196 } 197 198 static uint32_t dp8393x_crda(dp8393xState *s) 199 { 200 return (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]; 201 } 202 203 static uint32_t dp8393x_rbwc(dp8393xState *s) 204 { 205 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 206 } 207 208 static uint32_t dp8393x_rrp(dp8393xState *s) 209 { 210 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 211 } 212 213 static uint32_t dp8393x_tsa(dp8393xState *s) 214 { 215 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 216 } 217 218 static uint32_t dp8393x_ttda(dp8393xState *s) 219 { 220 return (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]; 221 } 222 223 static uint32_t dp8393x_wt(dp8393xState *s) 224 { 225 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 226 } 227 228 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 229 { 230 uint16_t val; 231 232 if (s->big_endian) { 233 val = be16_to_cpu(s->data[offset * width + width - 1]); 234 } else { 235 val = le16_to_cpu(s->data[offset * width]); 236 } 237 return val; 238 } 239 240 static void dp8393x_put(dp8393xState *s, int width, int offset, 241 uint16_t val) 242 { 243 if (s->big_endian) { 244 s->data[offset * width + width - 1] = cpu_to_be16(val); 245 } else { 246 s->data[offset * width] = cpu_to_le16(val); 247 } 248 } 249 250 static void dp8393x_update_irq(dp8393xState *s) 251 { 252 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 253 254 #ifdef DEBUG_SONIC 255 if (level != s->irq_level) { 256 s->irq_level = level; 257 if (level) { 258 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 259 } else { 260 DPRINTF("lower irq\n"); 261 } 262 } 263 #endif 264 265 qemu_set_irq(s->irq, level); 266 } 267 268 static void dp8393x_do_load_cam(dp8393xState *s) 269 { 270 int width, size; 271 uint16_t index = 0; 272 273 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 274 size = sizeof(uint16_t) * 4 * width; 275 276 while (s->regs[SONIC_CDC] & 0x1f) { 277 /* Fill current entry */ 278 address_space_read(&s->as, dp8393x_cdp(s), 279 MEMTXATTRS_UNSPECIFIED, s->data, size); 280 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 281 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 282 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 283 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 284 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 285 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 286 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 287 s->cam[index][0], s->cam[index][1], s->cam[index][2], 288 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 289 /* Move to next entry */ 290 s->regs[SONIC_CDC]--; 291 s->regs[SONIC_CDP] += size; 292 index++; 293 } 294 295 /* Read CAM enable */ 296 address_space_read(&s->as, dp8393x_cdp(s), 297 MEMTXATTRS_UNSPECIFIED, s->data, size); 298 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 299 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 300 301 /* Done */ 302 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 303 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 304 dp8393x_update_irq(s); 305 } 306 307 static void dp8393x_do_read_rra(dp8393xState *s) 308 { 309 int width, size; 310 311 /* Read memory */ 312 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 313 size = sizeof(uint16_t) * 4 * width; 314 address_space_read(&s->as, dp8393x_rrp(s), 315 MEMTXATTRS_UNSPECIFIED, s->data, size); 316 317 /* Update SONIC registers */ 318 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 319 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 320 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 321 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 322 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 323 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 324 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 325 326 /* Go to next entry */ 327 s->regs[SONIC_RRP] += size; 328 329 /* Handle wrap */ 330 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 331 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 332 } 333 334 /* Check resource exhaustion */ 335 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 336 { 337 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 338 dp8393x_update_irq(s); 339 } 340 341 /* Done */ 342 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 343 } 344 345 static void dp8393x_do_software_reset(dp8393xState *s) 346 { 347 timer_del(s->watchdog); 348 349 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 350 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 351 } 352 353 static void dp8393x_set_next_tick(dp8393xState *s) 354 { 355 uint32_t ticks; 356 int64_t delay; 357 358 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 359 timer_del(s->watchdog); 360 return; 361 } 362 363 ticks = dp8393x_wt(s); 364 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 365 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 366 timer_mod(s->watchdog, s->wt_last_update + delay); 367 } 368 369 static void dp8393x_update_wt_regs(dp8393xState *s) 370 { 371 int64_t elapsed; 372 uint32_t val; 373 374 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 375 timer_del(s->watchdog); 376 return; 377 } 378 379 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 380 val = dp8393x_wt(s); 381 val -= elapsed / 5000000; 382 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 383 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 384 dp8393x_set_next_tick(s); 385 386 } 387 388 static void dp8393x_do_start_timer(dp8393xState *s) 389 { 390 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 391 dp8393x_set_next_tick(s); 392 } 393 394 static void dp8393x_do_stop_timer(dp8393xState *s) 395 { 396 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 397 dp8393x_update_wt_regs(s); 398 } 399 400 static int dp8393x_can_receive(NetClientState *nc); 401 402 static void dp8393x_do_receiver_enable(dp8393xState *s) 403 { 404 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 405 if (dp8393x_can_receive(s->nic->ncs)) { 406 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 407 } 408 } 409 410 static void dp8393x_do_receiver_disable(dp8393xState *s) 411 { 412 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 413 } 414 415 static void dp8393x_do_transmit_packets(dp8393xState *s) 416 { 417 NetClientState *nc = qemu_get_queue(s->nic); 418 int width, size; 419 int tx_len, len; 420 uint16_t i; 421 422 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 423 424 while (1) { 425 /* Read memory */ 426 size = sizeof(uint16_t) * 6 * width; 427 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 428 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 429 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 430 MEMTXATTRS_UNSPECIFIED, s->data, size); 431 tx_len = 0; 432 433 /* Update registers */ 434 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 435 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 436 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 437 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 438 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 439 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 440 441 /* Handle programmable interrupt */ 442 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 443 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 444 } else { 445 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 446 } 447 448 for (i = 0; i < s->regs[SONIC_TFC]; ) { 449 /* Append fragment */ 450 len = s->regs[SONIC_TFS]; 451 if (tx_len + len > sizeof(s->tx_buffer)) { 452 len = sizeof(s->tx_buffer) - tx_len; 453 } 454 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, 455 &s->tx_buffer[tx_len], len); 456 tx_len += len; 457 458 i++; 459 if (i != s->regs[SONIC_TFC]) { 460 /* Read next fragment details */ 461 size = sizeof(uint16_t) * 3 * width; 462 address_space_read(&s->as, 463 dp8393x_ttda(s) 464 + sizeof(uint16_t) * width * (4 + 3 * i), 465 MEMTXATTRS_UNSPECIFIED, s->data, 466 size); 467 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 468 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 469 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 470 } 471 } 472 473 /* Handle Ethernet checksum */ 474 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 475 /* Don't append FCS there, to look like slirp packets 476 * which don't have one */ 477 } else { 478 /* Remove existing FCS */ 479 tx_len -= 4; 480 } 481 482 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 483 /* Loopback */ 484 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 485 if (nc->info->can_receive(nc)) { 486 s->loopback_packet = 1; 487 nc->info->receive(nc, s->tx_buffer, tx_len); 488 } 489 } else { 490 /* Transmit packet */ 491 qemu_send_packet(nc, s->tx_buffer, tx_len); 492 } 493 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 494 495 /* Write status */ 496 dp8393x_put(s, width, 0, 497 s->regs[SONIC_TCR] & 0x0fff); /* status */ 498 size = sizeof(uint16_t) * width; 499 address_space_write(&s->as, dp8393x_ttda(s), 500 MEMTXATTRS_UNSPECIFIED, s->data, size); 501 502 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 503 /* Read footer of packet */ 504 size = sizeof(uint16_t) * width; 505 address_space_read(&s->as, 506 dp8393x_ttda(s) 507 + sizeof(uint16_t) * width 508 * (4 + 3 * s->regs[SONIC_TFC]), 509 MEMTXATTRS_UNSPECIFIED, s->data, 510 size); 511 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; 512 if (dp8393x_get(s, width, 0) & 0x1) { 513 /* EOL detected */ 514 break; 515 } 516 } 517 } 518 519 /* Done */ 520 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 521 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 522 dp8393x_update_irq(s); 523 } 524 525 static void dp8393x_do_halt_transmission(dp8393xState *s) 526 { 527 /* Nothing to do */ 528 } 529 530 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 531 { 532 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 533 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 534 return; 535 } 536 537 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 538 539 if (command & SONIC_CR_HTX) 540 dp8393x_do_halt_transmission(s); 541 if (command & SONIC_CR_TXP) 542 dp8393x_do_transmit_packets(s); 543 if (command & SONIC_CR_RXDIS) 544 dp8393x_do_receiver_disable(s); 545 if (command & SONIC_CR_RXEN) 546 dp8393x_do_receiver_enable(s); 547 if (command & SONIC_CR_STP) 548 dp8393x_do_stop_timer(s); 549 if (command & SONIC_CR_ST) 550 dp8393x_do_start_timer(s); 551 if (command & SONIC_CR_RST) 552 dp8393x_do_software_reset(s); 553 if (command & SONIC_CR_RRRA) 554 dp8393x_do_read_rra(s); 555 if (command & SONIC_CR_LCAM) 556 dp8393x_do_load_cam(s); 557 } 558 559 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 560 { 561 dp8393xState *s = opaque; 562 int reg = addr >> s->it_shift; 563 uint16_t val = 0; 564 565 switch (reg) { 566 /* Update data before reading it */ 567 case SONIC_WT0: 568 case SONIC_WT1: 569 dp8393x_update_wt_regs(s); 570 val = s->regs[reg]; 571 break; 572 /* Accept read to some registers only when in reset mode */ 573 case SONIC_CAP2: 574 case SONIC_CAP1: 575 case SONIC_CAP0: 576 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 577 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 578 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 579 } 580 break; 581 /* All other registers have no special contrainst */ 582 default: 583 val = s->regs[reg]; 584 } 585 586 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 587 588 return val; 589 } 590 591 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 592 unsigned int size) 593 { 594 dp8393xState *s = opaque; 595 int reg = addr >> s->it_shift; 596 597 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]); 598 599 switch (reg) { 600 /* Command register */ 601 case SONIC_CR: 602 dp8393x_do_command(s, data); 603 break; 604 /* Prevent write to read-only registers */ 605 case SONIC_CAP2: 606 case SONIC_CAP1: 607 case SONIC_CAP0: 608 case SONIC_SR: 609 case SONIC_MDT: 610 DPRINTF("writing to reg %d invalid\n", reg); 611 break; 612 /* Accept write to some registers only when in reset mode */ 613 case SONIC_DCR: 614 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 615 s->regs[reg] = data & 0xbfff; 616 } else { 617 DPRINTF("writing to DCR invalid\n"); 618 } 619 break; 620 case SONIC_DCR2: 621 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 622 s->regs[reg] = data & 0xf017; 623 } else { 624 DPRINTF("writing to DCR2 invalid\n"); 625 } 626 break; 627 /* 12 lower bytes are Read Only */ 628 case SONIC_TCR: 629 s->regs[reg] = data & 0xf000; 630 break; 631 /* 9 lower bytes are Read Only */ 632 case SONIC_RCR: 633 s->regs[reg] = data & 0xffe0; 634 break; 635 /* Ignore most significant bit */ 636 case SONIC_IMR: 637 s->regs[reg] = data & 0x7fff; 638 dp8393x_update_irq(s); 639 break; 640 /* Clear bits by writing 1 to them */ 641 case SONIC_ISR: 642 data &= s->regs[reg]; 643 s->regs[reg] &= ~data; 644 if (data & SONIC_ISR_RBE) { 645 dp8393x_do_read_rra(s); 646 } 647 dp8393x_update_irq(s); 648 if (dp8393x_can_receive(s->nic->ncs)) { 649 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 650 } 651 break; 652 /* Ignore least significant bit */ 653 case SONIC_RSA: 654 case SONIC_REA: 655 case SONIC_RRP: 656 case SONIC_RWP: 657 s->regs[reg] = data & 0xfffe; 658 break; 659 /* Invert written value for some registers */ 660 case SONIC_CRCT: 661 case SONIC_FAET: 662 case SONIC_MPT: 663 s->regs[reg] = data ^ 0xffff; 664 break; 665 /* All other registers have no special contrainst */ 666 default: 667 s->regs[reg] = data; 668 } 669 670 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 671 dp8393x_set_next_tick(s); 672 } 673 } 674 675 static const MemoryRegionOps dp8393x_ops = { 676 .read = dp8393x_read, 677 .write = dp8393x_write, 678 .impl.min_access_size = 2, 679 .impl.max_access_size = 2, 680 .endianness = DEVICE_NATIVE_ENDIAN, 681 }; 682 683 static void dp8393x_watchdog(void *opaque) 684 { 685 dp8393xState *s = opaque; 686 687 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 688 return; 689 } 690 691 s->regs[SONIC_WT1] = 0xffff; 692 s->regs[SONIC_WT0] = 0xffff; 693 dp8393x_set_next_tick(s); 694 695 /* Signal underflow */ 696 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 697 dp8393x_update_irq(s); 698 } 699 700 static int dp8393x_can_receive(NetClientState *nc) 701 { 702 dp8393xState *s = qemu_get_nic_opaque(nc); 703 704 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 705 return 0; 706 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 707 return 0; 708 return 1; 709 } 710 711 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 712 int size) 713 { 714 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 715 int i; 716 717 /* Check promiscuous mode */ 718 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 719 return 0; 720 } 721 722 /* Check multicast packets */ 723 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 724 return SONIC_RCR_MC; 725 } 726 727 /* Check broadcast */ 728 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 729 return SONIC_RCR_BC; 730 } 731 732 /* Check CAM */ 733 for (i = 0; i < 16; i++) { 734 if (s->regs[SONIC_CE] & (1 << i)) { 735 /* Entry enabled */ 736 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 737 return 0; 738 } 739 } 740 } 741 742 return -1; 743 } 744 745 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 746 size_t size) 747 { 748 dp8393xState *s = qemu_get_nic_opaque(nc); 749 int packet_type; 750 uint32_t available, address; 751 int width, rx_len = size; 752 uint32_t checksum; 753 754 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 755 756 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 757 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 758 759 packet_type = dp8393x_receive_filter(s, buf, size); 760 if (packet_type < 0) { 761 DPRINTF("packet not for netcard\n"); 762 return -1; 763 } 764 765 /* XXX: Check byte ordering */ 766 767 /* Check for EOL */ 768 if (s->regs[SONIC_LLFA] & 0x1) { 769 /* Are we still in resource exhaustion? */ 770 size = sizeof(uint16_t) * 1 * width; 771 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 772 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, 773 s->data, size); 774 if (dp8393x_get(s, width, 0) & 0x1) { 775 /* Still EOL ; stop reception */ 776 return -1; 777 } else { 778 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 779 } 780 } 781 782 /* Save current position */ 783 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 784 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 785 786 /* Calculate the ethernet checksum */ 787 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 788 789 /* Put packet into RBA */ 790 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); 791 address = dp8393x_crba(s); 792 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 793 buf, rx_len); 794 address += rx_len; 795 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 796 &checksum, 4); 797 rx_len += 4; 798 s->regs[SONIC_CRBA1] = address >> 16; 799 s->regs[SONIC_CRBA0] = address & 0xffff; 800 available = dp8393x_rbwc(s); 801 available -= rx_len / 2; 802 s->regs[SONIC_RBWC1] = available >> 16; 803 s->regs[SONIC_RBWC0] = available & 0xffff; 804 805 /* Update status */ 806 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 807 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 808 } 809 s->regs[SONIC_RCR] |= packet_type; 810 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 811 if (s->loopback_packet) { 812 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 813 s->loopback_packet = 0; 814 } 815 816 /* Write status to memory */ 817 DPRINTF("Write status at %08x\n", dp8393x_crda(s)); 818 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 819 dp8393x_put(s, width, 1, rx_len); /* byte count */ 820 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 821 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 822 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 823 size = sizeof(uint16_t) * 5 * width; 824 address_space_write(&s->as, dp8393x_crda(s), 825 MEMTXATTRS_UNSPECIFIED, 826 s->data, size); 827 828 /* Move to next descriptor */ 829 size = sizeof(uint16_t) * width; 830 address_space_read(&s->as, 831 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 832 MEMTXATTRS_UNSPECIFIED, s->data, size); 833 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 834 if (s->regs[SONIC_LLFA] & 0x1) { 835 /* EOL detected */ 836 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 837 } else { 838 /* Clear in_use, but it is always 16bit wide */ 839 int offset = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 840 if (s->big_endian && width == 2) { 841 /* we need to adjust the offset of the 16bit field */ 842 offset += sizeof(uint16_t); 843 } 844 s->data[0] = 0; 845 address_space_write(&s->as, offset, MEMTXATTRS_UNSPECIFIED, 846 s->data, sizeof(uint16_t)); 847 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 848 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 849 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 850 851 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 852 /* Read next RRA */ 853 dp8393x_do_read_rra(s); 854 } 855 } 856 857 /* Done */ 858 dp8393x_update_irq(s); 859 860 return size; 861 } 862 863 static void dp8393x_reset(DeviceState *dev) 864 { 865 dp8393xState *s = DP8393X(dev); 866 timer_del(s->watchdog); 867 868 memset(s->regs, 0, sizeof(s->regs)); 869 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 870 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 871 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 872 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 873 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 874 s->regs[SONIC_IMR] = 0; 875 s->regs[SONIC_ISR] = 0; 876 s->regs[SONIC_DCR2] = 0; 877 s->regs[SONIC_EOBC] = 0x02F8; 878 s->regs[SONIC_RSC] = 0; 879 s->regs[SONIC_CE] = 0; 880 s->regs[SONIC_RSC] = 0; 881 882 /* Network cable is connected */ 883 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 884 885 dp8393x_update_irq(s); 886 } 887 888 static NetClientInfo net_dp83932_info = { 889 .type = NET_CLIENT_DRIVER_NIC, 890 .size = sizeof(NICState), 891 .can_receive = dp8393x_can_receive, 892 .receive = dp8393x_receive, 893 }; 894 895 static void dp8393x_instance_init(Object *obj) 896 { 897 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 898 dp8393xState *s = DP8393X(obj); 899 900 sysbus_init_mmio(sbd, &s->mmio); 901 sysbus_init_mmio(sbd, &s->prom); 902 sysbus_init_irq(sbd, &s->irq); 903 } 904 905 static void dp8393x_realize(DeviceState *dev, Error **errp) 906 { 907 dp8393xState *s = DP8393X(dev); 908 int i, checksum; 909 uint8_t *prom; 910 Error *local_err = NULL; 911 912 address_space_init(&s->as, s->dma_mr, "dp8393x"); 913 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 914 "dp8393x-regs", 0x40 << s->it_shift); 915 916 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 917 object_get_typename(OBJECT(dev)), dev->id, s); 918 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 919 920 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 921 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 922 923 memory_region_init_ram(&s->prom, OBJECT(dev), 924 "dp8393x-prom", SONIC_PROM_SIZE, &local_err); 925 if (local_err) { 926 error_propagate(errp, local_err); 927 return; 928 } 929 memory_region_set_readonly(&s->prom, true); 930 prom = memory_region_get_ram_ptr(&s->prom); 931 checksum = 0; 932 for (i = 0; i < 6; i++) { 933 prom[i] = s->conf.macaddr.a[i]; 934 checksum += prom[i]; 935 if (checksum > 0xff) { 936 checksum = (checksum + 1) & 0xff; 937 } 938 } 939 prom[7] = 0xff - checksum; 940 } 941 942 static const VMStateDescription vmstate_dp8393x = { 943 .name = "dp8393x", 944 .version_id = 0, 945 .minimum_version_id = 0, 946 .fields = (VMStateField []) { 947 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 948 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 949 VMSTATE_END_OF_LIST() 950 } 951 }; 952 953 static Property dp8393x_properties[] = { 954 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 955 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 956 TYPE_MEMORY_REGION, MemoryRegion *), 957 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 958 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 959 DEFINE_PROP_END_OF_LIST(), 960 }; 961 962 static void dp8393x_class_init(ObjectClass *klass, void *data) 963 { 964 DeviceClass *dc = DEVICE_CLASS(klass); 965 966 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 967 dc->realize = dp8393x_realize; 968 dc->reset = dp8393x_reset; 969 dc->vmsd = &vmstate_dp8393x; 970 device_class_set_props(dc, dp8393x_properties); 971 } 972 973 static const TypeInfo dp8393x_info = { 974 .name = TYPE_DP8393X, 975 .parent = TYPE_SYS_BUS_DEVICE, 976 .instance_size = sizeof(dp8393xState), 977 .instance_init = dp8393x_instance_init, 978 .class_init = dp8393x_class_init, 979 }; 980 981 static void dp8393x_register_types(void) 982 { 983 type_register_static(&dp8393x_info); 984 } 985 986 type_init(dp8393x_register_types) 987