1 /* 2 * QEMU INTEL 82574 GbE NIC emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "net/net.h" 38 #include "net/tap.h" 39 #include "qemu/range.h" 40 #include "sysemu/sysemu.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 44 #include "hw/net/e1000_regs.h" 45 46 #include "e1000x_common.h" 47 #include "e1000e_core.h" 48 49 #include "trace.h" 50 51 #define TYPE_E1000E "e1000e" 52 #define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E) 53 54 typedef struct E1000EState { 55 PCIDevice parent_obj; 56 NICState *nic; 57 NICConf conf; 58 59 MemoryRegion mmio; 60 MemoryRegion flash; 61 MemoryRegion io; 62 MemoryRegion msix; 63 64 uint32_t ioaddr; 65 66 uint16_t subsys_ven; 67 uint16_t subsys; 68 69 uint16_t subsys_ven_used; 70 uint16_t subsys_used; 71 72 uint32_t intr_state; 73 bool disable_vnet; 74 75 E1000ECore core; 76 77 } E1000EState; 78 79 #define E1000E_MMIO_IDX 0 80 #define E1000E_FLASH_IDX 1 81 #define E1000E_IO_IDX 2 82 #define E1000E_MSIX_IDX 3 83 84 #define E1000E_MMIO_SIZE (128 * 1024) 85 #define E1000E_FLASH_SIZE (128 * 1024) 86 #define E1000E_IO_SIZE (32) 87 #define E1000E_MSIX_SIZE (16 * 1024) 88 89 #define E1000E_MSIX_TABLE (0x0000) 90 #define E1000E_MSIX_PBA (0x2000) 91 92 #define E1000E_USE_MSI BIT(0) 93 #define E1000E_USE_MSIX BIT(1) 94 95 static uint64_t 96 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size) 97 { 98 E1000EState *s = opaque; 99 return e1000e_core_read(&s->core, addr, size); 100 } 101 102 static void 103 e1000e_mmio_write(void *opaque, hwaddr addr, 104 uint64_t val, unsigned size) 105 { 106 E1000EState *s = opaque; 107 e1000e_core_write(&s->core, addr, val, size); 108 } 109 110 static bool 111 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx) 112 { 113 if (s->ioaddr < 0x1FFFF) { 114 *idx = s->ioaddr; 115 return true; 116 } 117 118 if (s->ioaddr < 0x7FFFF) { 119 trace_e1000e_wrn_io_addr_undefined(s->ioaddr); 120 return false; 121 } 122 123 if (s->ioaddr < 0xFFFFF) { 124 trace_e1000e_wrn_io_addr_flash(s->ioaddr); 125 return false; 126 } 127 128 trace_e1000e_wrn_io_addr_unknown(s->ioaddr); 129 return false; 130 } 131 132 static uint64_t 133 e1000e_io_read(void *opaque, hwaddr addr, unsigned size) 134 { 135 E1000EState *s = opaque; 136 uint32_t idx = 0; 137 uint64_t val; 138 139 switch (addr) { 140 case E1000_IOADDR: 141 trace_e1000e_io_read_addr(s->ioaddr); 142 return s->ioaddr; 143 case E1000_IODATA: 144 if (e1000e_io_get_reg_index(s, &idx)) { 145 val = e1000e_core_read(&s->core, idx, sizeof(val)); 146 trace_e1000e_io_read_data(idx, val); 147 return val; 148 } 149 return 0; 150 default: 151 trace_e1000e_wrn_io_read_unknown(addr); 152 return 0; 153 } 154 } 155 156 static void 157 e1000e_io_write(void *opaque, hwaddr addr, 158 uint64_t val, unsigned size) 159 { 160 E1000EState *s = opaque; 161 uint32_t idx = 0; 162 163 switch (addr) { 164 case E1000_IOADDR: 165 trace_e1000e_io_write_addr(val); 166 s->ioaddr = (uint32_t) val; 167 return; 168 case E1000_IODATA: 169 if (e1000e_io_get_reg_index(s, &idx)) { 170 trace_e1000e_io_write_data(idx, val); 171 e1000e_core_write(&s->core, idx, val, sizeof(val)); 172 } 173 return; 174 default: 175 trace_e1000e_wrn_io_write_unknown(addr); 176 return; 177 } 178 } 179 180 static const MemoryRegionOps mmio_ops = { 181 .read = e1000e_mmio_read, 182 .write = e1000e_mmio_write, 183 .endianness = DEVICE_LITTLE_ENDIAN, 184 .impl = { 185 .min_access_size = 4, 186 .max_access_size = 4, 187 }, 188 }; 189 190 static const MemoryRegionOps io_ops = { 191 .read = e1000e_io_read, 192 .write = e1000e_io_write, 193 .endianness = DEVICE_LITTLE_ENDIAN, 194 .impl = { 195 .min_access_size = 4, 196 .max_access_size = 4, 197 }, 198 }; 199 200 static int 201 e1000e_nc_can_receive(NetClientState *nc) 202 { 203 E1000EState *s = qemu_get_nic_opaque(nc); 204 return e1000e_can_receive(&s->core); 205 } 206 207 static ssize_t 208 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt) 209 { 210 E1000EState *s = qemu_get_nic_opaque(nc); 211 return e1000e_receive_iov(&s->core, iov, iovcnt); 212 } 213 214 static ssize_t 215 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size) 216 { 217 E1000EState *s = qemu_get_nic_opaque(nc); 218 return e1000e_receive(&s->core, buf, size); 219 } 220 221 static void 222 e1000e_set_link_status(NetClientState *nc) 223 { 224 E1000EState *s = qemu_get_nic_opaque(nc); 225 e1000e_core_set_link_status(&s->core); 226 } 227 228 static NetClientInfo net_e1000e_info = { 229 .type = NET_CLIENT_OPTIONS_KIND_NIC, 230 .size = sizeof(NICState), 231 .can_receive = e1000e_nc_can_receive, 232 .receive = e1000e_nc_receive, 233 .receive_iov = e1000e_nc_receive_iov, 234 .link_status_changed = e1000e_set_link_status, 235 }; 236 237 /* 238 * EEPROM (NVM) contents documented in Table 36, section 6.1 239 * and generally 6.1.2 Software accessed words. 240 */ 241 static const uint16_t e1000e_eeprom_template[64] = { 242 /* Address | Compat. | ImVer | Compat. */ 243 0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff, 244 /* PBA |ICtrl1 | SSID | SVID | DevID |-------|ICtrl2 */ 245 0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058, 246 /* NVM words 1,2,3 |-------------------------------|PCI-EID*/ 247 0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704, 248 /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */ 249 0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706, 250 /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/ 251 0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff, 252 /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP */ 253 0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff, 254 /* SW Section */ 255 0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff, 256 /* SW Section |CHKSUM */ 257 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000, 258 }; 259 260 static void e1000e_core_realize(E1000EState *s) 261 { 262 s->core.owner = &s->parent_obj; 263 s->core.owner_nic = s->nic; 264 } 265 266 static void 267 e1000e_init_msi(E1000EState *s) 268 { 269 int res; 270 271 res = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL); 272 273 if (!res) { 274 s->intr_state |= E1000E_USE_MSI; 275 } else { 276 trace_e1000e_msi_init_fail(res); 277 } 278 } 279 280 static void 281 e1000e_cleanup_msi(E1000EState *s) 282 { 283 if (s->intr_state & E1000E_USE_MSI) { 284 msi_uninit(PCI_DEVICE(s)); 285 } 286 } 287 288 static void 289 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors) 290 { 291 int i; 292 for (i = 0; i < num_vectors; i++) { 293 msix_vector_unuse(PCI_DEVICE(s), i); 294 } 295 } 296 297 static bool 298 e1000e_use_msix_vectors(E1000EState *s, int num_vectors) 299 { 300 int i; 301 for (i = 0; i < num_vectors; i++) { 302 int res = msix_vector_use(PCI_DEVICE(s), i); 303 if (res < 0) { 304 trace_e1000e_msix_use_vector_fail(i, res); 305 e1000e_unuse_msix_vectors(s, i); 306 return false; 307 } 308 } 309 return true; 310 } 311 312 static void 313 e1000e_init_msix(E1000EState *s) 314 { 315 PCIDevice *d = PCI_DEVICE(s); 316 int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM, 317 &s->msix, 318 E1000E_MSIX_IDX, E1000E_MSIX_TABLE, 319 &s->msix, 320 E1000E_MSIX_IDX, E1000E_MSIX_PBA, 321 0xA0); 322 323 if (res < 0) { 324 trace_e1000e_msix_init_fail(res); 325 } else { 326 if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) { 327 msix_uninit(d, &s->msix, &s->msix); 328 } else { 329 s->intr_state |= E1000E_USE_MSIX; 330 } 331 } 332 } 333 334 static void 335 e1000e_cleanup_msix(E1000EState *s) 336 { 337 if (s->intr_state & E1000E_USE_MSIX) { 338 e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM); 339 msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix); 340 } 341 } 342 343 static void 344 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr) 345 { 346 DeviceState *dev = DEVICE(pci_dev); 347 NetClientState *nc; 348 int i; 349 350 s->nic = qemu_new_nic(&net_e1000e_info, &s->conf, 351 object_get_typename(OBJECT(s)), dev->id, s); 352 353 s->core.max_queue_num = s->conf.peers.queues - 1; 354 355 trace_e1000e_mac_set_permanent(MAC_ARG(macaddr)); 356 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac)); 357 358 qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr); 359 360 /* Setup virtio headers */ 361 if (s->disable_vnet) { 362 s->core.has_vnet = false; 363 trace_e1000e_cfg_support_virtio(false); 364 return; 365 } else { 366 s->core.has_vnet = true; 367 } 368 369 for (i = 0; i < s->conf.peers.queues; i++) { 370 nc = qemu_get_subqueue(s->nic, i); 371 if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) { 372 s->core.has_vnet = false; 373 trace_e1000e_cfg_support_virtio(false); 374 return; 375 } 376 } 377 378 trace_e1000e_cfg_support_virtio(true); 379 380 for (i = 0; i < s->conf.peers.queues; i++) { 381 nc = qemu_get_subqueue(s->nic, i); 382 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr)); 383 qemu_using_vnet_hdr(nc->peer, true); 384 } 385 } 386 387 static inline uint64_t 388 e1000e_gen_dsn(uint8_t *mac) 389 { 390 return (uint64_t)(mac[5]) | 391 (uint64_t)(mac[4]) << 8 | 392 (uint64_t)(mac[3]) << 16 | 393 (uint64_t)(0x00FF) << 24 | 394 (uint64_t)(0x00FF) << 32 | 395 (uint64_t)(mac[2]) << 40 | 396 (uint64_t)(mac[1]) << 48 | 397 (uint64_t)(mac[0]) << 56; 398 } 399 400 static int 401 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) 402 { 403 int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF); 404 405 if (ret >= 0) { 406 pci_set_word(pdev->config + offset + PCI_PM_PMC, 407 PCI_PM_CAP_VER_1_1 | 408 pmc); 409 410 pci_set_word(pdev->wmask + offset + PCI_PM_CTRL, 411 PCI_PM_CTRL_STATE_MASK | 412 PCI_PM_CTRL_PME_ENABLE | 413 PCI_PM_CTRL_DATA_SEL_MASK); 414 415 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, 416 PCI_PM_CTRL_PME_STATUS); 417 } 418 419 return ret; 420 } 421 422 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, 423 uint32_t val, int len) 424 { 425 E1000EState *s = E1000E(pci_dev); 426 427 pci_default_write_config(pci_dev, address, val, len); 428 429 if (range_covers_byte(address, len, PCI_COMMAND) && 430 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { 431 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 432 } 433 } 434 435 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) 436 { 437 static const uint16_t e1000e_pmrb_offset = 0x0C8; 438 static const uint16_t e1000e_pcie_offset = 0x0E0; 439 static const uint16_t e1000e_aer_offset = 0x100; 440 static const uint16_t e1000e_dsn_offset = 0x140; 441 E1000EState *s = E1000E(pci_dev); 442 uint8_t *macaddr; 443 444 trace_e1000e_cb_pci_realize(); 445 446 pci_dev->config_write = e1000e_write_config; 447 448 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 449 pci_dev->config[PCI_INTERRUPT_PIN] = 1; 450 451 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven); 452 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys); 453 454 s->subsys_ven_used = s->subsys_ven; 455 s->subsys_used = s->subsys; 456 457 /* Define IO/MMIO regions */ 458 memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s, 459 "e1000e-mmio", E1000E_MMIO_SIZE); 460 pci_register_bar(pci_dev, E1000E_MMIO_IDX, 461 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio); 462 463 /* 464 * We provide a dummy implementation for the flash BAR 465 * for drivers that may theoretically probe for its presence. 466 */ 467 memory_region_init(&s->flash, OBJECT(s), 468 "e1000e-flash", E1000E_FLASH_SIZE); 469 pci_register_bar(pci_dev, E1000E_FLASH_IDX, 470 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash); 471 472 memory_region_init_io(&s->io, OBJECT(s), &io_ops, s, 473 "e1000e-io", E1000E_IO_SIZE); 474 pci_register_bar(pci_dev, E1000E_IO_IDX, 475 PCI_BASE_ADDRESS_SPACE_IO, &s->io); 476 477 memory_region_init(&s->msix, OBJECT(s), "e1000e-msix", 478 E1000E_MSIX_SIZE); 479 pci_register_bar(pci_dev, E1000E_MSIX_IDX, 480 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix); 481 482 /* Create networking backend */ 483 qemu_macaddr_default_if_unset(&s->conf.macaddr); 484 macaddr = s->conf.macaddr.a; 485 486 e1000e_init_msix(s); 487 488 if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) { 489 hw_error("Failed to initialize PCIe capability"); 490 } 491 492 e1000e_init_msi(s); 493 494 if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, 495 PCI_PM_CAP_DSI) < 0) { 496 hw_error("Failed to initialize PM capability"); 497 } 498 499 if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF) < 0) { 500 hw_error("Failed to initialize AER capability"); 501 } 502 503 pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset, 504 e1000e_gen_dsn(macaddr)); 505 506 e1000e_init_net_peer(s, pci_dev, macaddr); 507 508 /* Initialize core */ 509 e1000e_core_realize(s); 510 511 e1000e_core_pci_realize(&s->core, 512 e1000e_eeprom_template, 513 sizeof(e1000e_eeprom_template), 514 macaddr); 515 } 516 517 static void e1000e_pci_uninit(PCIDevice *pci_dev) 518 { 519 E1000EState *s = E1000E(pci_dev); 520 521 trace_e1000e_cb_pci_uninit(); 522 523 e1000e_core_pci_uninit(&s->core); 524 525 pcie_aer_exit(pci_dev); 526 pcie_cap_exit(pci_dev); 527 528 qemu_del_nic(s->nic); 529 530 e1000e_cleanup_msix(s); 531 e1000e_cleanup_msi(s); 532 } 533 534 static void e1000e_qdev_reset(DeviceState *dev) 535 { 536 E1000EState *s = E1000E(dev); 537 538 trace_e1000e_cb_qdev_reset(); 539 540 e1000e_core_reset(&s->core); 541 } 542 543 static void e1000e_pre_save(void *opaque) 544 { 545 E1000EState *s = opaque; 546 547 trace_e1000e_cb_pre_save(); 548 549 e1000e_core_pre_save(&s->core); 550 } 551 552 static int e1000e_post_load(void *opaque, int version_id) 553 { 554 E1000EState *s = opaque; 555 556 trace_e1000e_cb_post_load(); 557 558 if ((s->subsys != s->subsys_used) || 559 (s->subsys_ven != s->subsys_ven_used)) { 560 fprintf(stderr, 561 "ERROR: Cannot migrate while device properties " 562 "(subsys/subsys_ven) differ"); 563 return -1; 564 } 565 566 return e1000e_core_post_load(&s->core); 567 } 568 569 static const VMStateDescription e1000e_vmstate_tx = { 570 .name = "e1000e-tx", 571 .version_id = 1, 572 .minimum_version_id = 1, 573 .fields = (VMStateField[]) { 574 VMSTATE_UINT8(props.sum_needed, struct e1000e_tx), 575 VMSTATE_UINT8(props.ipcss, struct e1000e_tx), 576 VMSTATE_UINT8(props.ipcso, struct e1000e_tx), 577 VMSTATE_UINT16(props.ipcse, struct e1000e_tx), 578 VMSTATE_UINT8(props.tucss, struct e1000e_tx), 579 VMSTATE_UINT8(props.tucso, struct e1000e_tx), 580 VMSTATE_UINT16(props.tucse, struct e1000e_tx), 581 VMSTATE_UINT8(props.hdr_len, struct e1000e_tx), 582 VMSTATE_UINT16(props.mss, struct e1000e_tx), 583 VMSTATE_UINT32(props.paylen, struct e1000e_tx), 584 VMSTATE_INT8(props.ip, struct e1000e_tx), 585 VMSTATE_INT8(props.tcp, struct e1000e_tx), 586 VMSTATE_BOOL(props.tse, struct e1000e_tx), 587 VMSTATE_BOOL(props.cptse, struct e1000e_tx), 588 VMSTATE_BOOL(skip_cp, struct e1000e_tx), 589 VMSTATE_END_OF_LIST() 590 } 591 }; 592 593 static const VMStateDescription e1000e_vmstate_intr_timer = { 594 .name = "e1000e-intr-timer", 595 .version_id = 1, 596 .minimum_version_id = 1, 597 .fields = (VMStateField[]) { 598 VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer), 599 VMSTATE_BOOL(running, E1000IntrDelayTimer), 600 VMSTATE_END_OF_LIST() 601 } 602 }; 603 604 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s) \ 605 VMSTATE_STRUCT(_f, _s, 0, \ 606 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 607 608 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \ 609 VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \ 610 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 611 612 static const VMStateDescription e1000e_vmstate = { 613 .name = "e1000e", 614 .version_id = 1, 615 .minimum_version_id = 1, 616 .pre_save = e1000e_pre_save, 617 .post_load = e1000e_post_load, 618 .fields = (VMStateField[]) { 619 VMSTATE_PCIE_DEVICE(parent_obj, E1000EState), 620 VMSTATE_MSIX(parent_obj, E1000EState), 621 622 VMSTATE_UINT32(ioaddr, E1000EState), 623 VMSTATE_UINT32(intr_state, E1000EState), 624 VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState), 625 VMSTATE_UINT8(core.rx_desc_len, E1000EState), 626 VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState, 627 E1000_PSRCTL_BUFFS_PER_DESC), 628 VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState), 629 VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE), 630 VMSTATE_UINT16_2DARRAY(core.phy, E1000EState, 631 E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE), 632 VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE), 633 VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN), 634 635 VMSTATE_UINT32(core.delayed_causes, E1000EState), 636 637 VMSTATE_UINT16(subsys, E1000EState), 638 VMSTATE_UINT16(subsys_ven, E1000EState), 639 640 VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState), 641 VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState), 642 VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState), 643 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState), 644 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState), 645 646 VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState), 647 VMSTATE_BOOL(core.itr_intr_pending, E1000EState), 648 649 VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState, 650 E1000E_MSIX_VEC_NUM), 651 VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState, 652 E1000E_MSIX_VEC_NUM), 653 654 VMSTATE_UINT32(core.itr_guest_value, E1000EState), 655 VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState, 656 E1000E_MSIX_VEC_NUM), 657 658 VMSTATE_UINT16(core.vet, E1000EState), 659 660 VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0, 661 e1000e_vmstate_tx, struct e1000e_tx), 662 VMSTATE_END_OF_LIST() 663 } 664 }; 665 666 static PropertyInfo e1000e_prop_disable_vnet, 667 e1000e_prop_subsys_ven, 668 e1000e_prop_subsys; 669 670 static Property e1000e_properties[] = { 671 DEFINE_NIC_PROPERTIES(E1000EState, conf), 672 DEFINE_PROP_DEFAULT("disable_vnet_hdr", E1000EState, disable_vnet, false, 673 e1000e_prop_disable_vnet, bool), 674 DEFINE_PROP_DEFAULT("subsys_ven", E1000EState, subsys_ven, 675 PCI_VENDOR_ID_INTEL, 676 e1000e_prop_subsys_ven, uint16_t), 677 DEFINE_PROP_DEFAULT("subsys", E1000EState, subsys, 0, 678 e1000e_prop_subsys, uint16_t), 679 DEFINE_PROP_END_OF_LIST(), 680 }; 681 682 static void e1000e_class_init(ObjectClass *class, void *data) 683 { 684 DeviceClass *dc = DEVICE_CLASS(class); 685 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 686 687 c->realize = e1000e_pci_realize; 688 c->exit = e1000e_pci_uninit; 689 c->vendor_id = PCI_VENDOR_ID_INTEL; 690 c->device_id = E1000_DEV_ID_82574L; 691 c->revision = 0; 692 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 693 c->is_express = 1; 694 695 dc->desc = "Intel 82574L GbE Controller"; 696 dc->reset = e1000e_qdev_reset; 697 dc->vmsd = &e1000e_vmstate; 698 dc->props = e1000e_properties; 699 700 e1000e_prop_disable_vnet = qdev_prop_uint8; 701 e1000e_prop_disable_vnet.description = "Do not use virtio headers, " 702 "perform SW offloads emulation " 703 "instead"; 704 705 e1000e_prop_subsys_ven = qdev_prop_uint16; 706 e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID"; 707 708 e1000e_prop_subsys = qdev_prop_uint16; 709 e1000e_prop_subsys.description = "PCI device Subsystem ID"; 710 711 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 712 } 713 714 static void e1000e_instance_init(Object *obj) 715 { 716 E1000EState *s = E1000E(obj); 717 device_add_bootindex_property(obj, &s->conf.bootindex, 718 "bootindex", "/ethernet-phy@0", 719 DEVICE(obj), NULL); 720 } 721 722 static const TypeInfo e1000e_info = { 723 .name = TYPE_E1000E, 724 .parent = TYPE_PCI_DEVICE, 725 .instance_size = sizeof(E1000EState), 726 .class_init = e1000e_class_init, 727 .instance_init = e1000e_instance_init, 728 }; 729 730 static void e1000e_register_types(void) 731 { 732 type_register_static(&e1000e_info); 733 } 734 735 type_init(e1000e_register_types) 736