1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000x_common.h" 49 #include "e1000e_core.h" 50 51 #include "trace.h" 52 53 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 54 #define E1000E_MIN_XITR (500) 55 56 #define E1000E_MAX_TX_FRAGS (64) 57 58 union e1000_rx_desc_union { 59 struct e1000_rx_desc legacy; 60 union e1000_rx_desc_extended extended; 61 union e1000_rx_desc_packet_split packet_split; 62 }; 63 64 static ssize_t 65 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 66 bool has_vnet); 67 68 static inline void 69 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 70 71 static void e1000e_reset(E1000ECore *core, bool sw); 72 73 static inline void 74 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 75 { 76 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 77 trace_e1000e_wrn_no_ts_support(); 78 } 79 } 80 81 static inline void 82 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 83 { 84 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 85 trace_e1000e_wrn_no_snap_support(); 86 } 87 } 88 89 static inline void 90 e1000e_raise_legacy_irq(E1000ECore *core) 91 { 92 trace_e1000e_irq_legacy_notify(true); 93 e1000x_inc_reg_if_not_full(core->mac, IAC); 94 pci_set_irq(core->owner, 1); 95 } 96 97 static inline void 98 e1000e_lower_legacy_irq(E1000ECore *core) 99 { 100 trace_e1000e_irq_legacy_notify(false); 101 pci_set_irq(core->owner, 0); 102 } 103 104 static inline void 105 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 106 { 107 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 108 timer->delay_resolution_ns; 109 110 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 111 112 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 113 114 timer->running = true; 115 } 116 117 static void 118 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 119 { 120 if (timer->running) { 121 e1000e_intrmgr_rearm_timer(timer); 122 } 123 } 124 125 static void 126 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 127 { 128 if (timer->running) { 129 timer_del(timer->timer); 130 } 131 } 132 133 static inline void 134 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 135 { 136 if (timer->running) { 137 timer_del(timer->timer); 138 timer->running = false; 139 } 140 } 141 142 static inline void 143 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 144 { 145 trace_e1000e_irq_fire_delayed_interrupts(); 146 e1000e_set_interrupt_cause(core, 0); 147 } 148 149 static void 150 e1000e_intrmgr_on_timer(void *opaque) 151 { 152 E1000IntrDelayTimer *timer = opaque; 153 154 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 155 156 timer->running = false; 157 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 158 } 159 160 static void 161 e1000e_intrmgr_on_throttling_timer(void *opaque) 162 { 163 E1000IntrDelayTimer *timer = opaque; 164 165 timer->running = false; 166 167 if (msi_enabled(timer->core->owner)) { 168 trace_e1000e_irq_msi_notify_postponed(); 169 /* Clear msi_causes_pending to fire MSI eventually */ 170 timer->core->msi_causes_pending = 0; 171 e1000e_set_interrupt_cause(timer->core, 0); 172 } else { 173 trace_e1000e_irq_legacy_notify_postponed(); 174 e1000e_set_interrupt_cause(timer->core, 0); 175 } 176 } 177 178 static void 179 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 180 { 181 E1000IntrDelayTimer *timer = opaque; 182 int idx = timer - &timer->core->eitr[0]; 183 184 timer->running = false; 185 186 trace_e1000e_irq_msix_notify_postponed_vec(idx); 187 msix_notify(timer->core->owner, idx); 188 } 189 190 static void 191 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 192 { 193 int i; 194 195 core->radv.delay_reg = RADV; 196 core->rdtr.delay_reg = RDTR; 197 core->raid.delay_reg = RAID; 198 core->tadv.delay_reg = TADV; 199 core->tidv.delay_reg = TIDV; 200 201 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 202 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 204 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 205 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 206 207 core->radv.core = core; 208 core->rdtr.core = core; 209 core->raid.core = core; 210 core->tadv.core = core; 211 core->tidv.core = core; 212 213 core->itr.core = core; 214 core->itr.delay_reg = ITR; 215 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 216 217 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 218 core->eitr[i].core = core; 219 core->eitr[i].delay_reg = EITR + i; 220 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 221 } 222 223 if (!create) { 224 return; 225 } 226 227 core->radv.timer = 228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 229 core->rdtr.timer = 230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 231 core->raid.timer = 232 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 233 234 core->tadv.timer = 235 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 236 core->tidv.timer = 237 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 238 239 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 240 e1000e_intrmgr_on_throttling_timer, 241 &core->itr); 242 243 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 244 core->eitr[i].timer = 245 timer_new_ns(QEMU_CLOCK_VIRTUAL, 246 e1000e_intrmgr_on_msix_throttling_timer, 247 &core->eitr[i]); 248 } 249 } 250 251 static inline void 252 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 253 { 254 e1000e_intrmgr_stop_timer(&core->radv); 255 e1000e_intrmgr_stop_timer(&core->rdtr); 256 e1000e_intrmgr_stop_timer(&core->raid); 257 e1000e_intrmgr_stop_timer(&core->tidv); 258 e1000e_intrmgr_stop_timer(&core->tadv); 259 } 260 261 static bool 262 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 263 { 264 uint32_t delayable_causes; 265 uint32_t rdtr = core->mac[RDTR]; 266 uint32_t radv = core->mac[RADV]; 267 uint32_t raid = core->mac[RAID]; 268 269 if (msix_enabled(core->owner)) { 270 return false; 271 } 272 273 delayable_causes = E1000_ICR_RXQ0 | 274 E1000_ICR_RXQ1 | 275 E1000_ICR_RXT0; 276 277 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 278 delayable_causes |= E1000_ICR_ACK; 279 } 280 281 /* Clean up all causes that may be delayed */ 282 core->delayed_causes |= *causes & delayable_causes; 283 *causes &= ~delayable_causes; 284 285 /* 286 * Check if delayed RX interrupts disabled by client 287 * or if there are causes that cannot be delayed 288 */ 289 if ((rdtr == 0) || (*causes != 0)) { 290 return false; 291 } 292 293 /* 294 * Check if delayed RX ACK interrupts disabled by client 295 * and there is an ACK packet received 296 */ 297 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 298 return false; 299 } 300 301 /* All causes delayed */ 302 e1000e_intrmgr_rearm_timer(&core->rdtr); 303 304 if (!core->radv.running && (radv != 0)) { 305 e1000e_intrmgr_rearm_timer(&core->radv); 306 } 307 308 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 309 e1000e_intrmgr_rearm_timer(&core->raid); 310 } 311 312 return true; 313 } 314 315 static bool 316 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 317 { 318 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 319 E1000_ICR_TXQ1 | 320 E1000_ICR_TXQE | 321 E1000_ICR_TXDW; 322 323 if (msix_enabled(core->owner)) { 324 return false; 325 } 326 327 /* Clean up all causes that may be delayed */ 328 core->delayed_causes |= *causes & delayable_causes; 329 *causes &= ~delayable_causes; 330 331 /* If there are causes that cannot be delayed */ 332 if (*causes != 0) { 333 return false; 334 } 335 336 /* All causes delayed */ 337 e1000e_intrmgr_rearm_timer(&core->tidv); 338 339 if (!core->tadv.running && (core->mac[TADV] != 0)) { 340 e1000e_intrmgr_rearm_timer(&core->tadv); 341 } 342 343 return true; 344 } 345 346 static uint32_t 347 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 348 { 349 uint32_t res; 350 351 if (msix_enabled(core->owner)) { 352 assert(core->delayed_causes == 0); 353 return 0; 354 } 355 356 res = core->delayed_causes; 357 core->delayed_causes = 0; 358 359 e1000e_intrmgr_stop_delay_timers(core); 360 361 return res; 362 } 363 364 static void 365 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 366 { 367 int i; 368 uint32_t val = e1000e_intmgr_collect_delayed_causes(core); 369 370 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]); 371 core->mac[ICR] |= val; 372 373 if (core->itr.running) { 374 timer_del(core->itr.timer); 375 e1000e_intrmgr_on_throttling_timer(&core->itr); 376 } 377 378 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 379 if (core->eitr[i].running) { 380 timer_del(core->eitr[i].timer); 381 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 382 } 383 } 384 } 385 386 static void 387 e1000e_intrmgr_resume(E1000ECore *core) 388 { 389 int i; 390 391 e1000e_intmgr_timer_resume(&core->radv); 392 e1000e_intmgr_timer_resume(&core->rdtr); 393 e1000e_intmgr_timer_resume(&core->raid); 394 e1000e_intmgr_timer_resume(&core->tidv); 395 e1000e_intmgr_timer_resume(&core->tadv); 396 397 e1000e_intmgr_timer_resume(&core->itr); 398 399 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 400 e1000e_intmgr_timer_resume(&core->eitr[i]); 401 } 402 } 403 404 static void 405 e1000e_intrmgr_pause(E1000ECore *core) 406 { 407 int i; 408 409 e1000e_intmgr_timer_pause(&core->radv); 410 e1000e_intmgr_timer_pause(&core->rdtr); 411 e1000e_intmgr_timer_pause(&core->raid); 412 e1000e_intmgr_timer_pause(&core->tidv); 413 e1000e_intmgr_timer_pause(&core->tadv); 414 415 e1000e_intmgr_timer_pause(&core->itr); 416 417 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 418 e1000e_intmgr_timer_pause(&core->eitr[i]); 419 } 420 } 421 422 static void 423 e1000e_intrmgr_reset(E1000ECore *core) 424 { 425 int i; 426 427 core->delayed_causes = 0; 428 429 e1000e_intrmgr_stop_delay_timers(core); 430 431 e1000e_intrmgr_stop_timer(&core->itr); 432 433 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 434 e1000e_intrmgr_stop_timer(&core->eitr[i]); 435 } 436 } 437 438 static void 439 e1000e_intrmgr_pci_unint(E1000ECore *core) 440 { 441 int i; 442 443 timer_free(core->radv.timer); 444 timer_free(core->rdtr.timer); 445 timer_free(core->raid.timer); 446 447 timer_free(core->tadv.timer); 448 timer_free(core->tidv.timer); 449 450 timer_free(core->itr.timer); 451 452 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 453 timer_free(core->eitr[i].timer); 454 } 455 } 456 457 static void 458 e1000e_intrmgr_pci_realize(E1000ECore *core) 459 { 460 e1000e_intrmgr_initialize_all_timers(core, true); 461 } 462 463 static inline bool 464 e1000e_rx_csum_enabled(E1000ECore *core) 465 { 466 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 467 } 468 469 static inline bool 470 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 471 { 472 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 473 } 474 475 static inline bool 476 e1000e_rx_use_ps_descriptor(E1000ECore *core) 477 { 478 return !e1000e_rx_use_legacy_descriptor(core) && 479 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 480 } 481 482 static inline bool 483 e1000e_rss_enabled(E1000ECore *core) 484 { 485 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 486 !e1000e_rx_csum_enabled(core) && 487 !e1000e_rx_use_legacy_descriptor(core); 488 } 489 490 typedef struct E1000E_RSSInfo_st { 491 bool enabled; 492 uint32_t hash; 493 uint32_t queue; 494 uint32_t type; 495 } E1000E_RSSInfo; 496 497 static uint32_t 498 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 499 { 500 bool hasip4, hasip6, hasudp, hastcp; 501 502 assert(e1000e_rss_enabled(core)); 503 504 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &hasudp, &hastcp); 505 506 if (hasip4) { 507 trace_e1000e_rx_rss_ip4(hastcp, core->mac[MRQC], 508 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 509 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 510 511 if (hastcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 512 return E1000_MRQ_RSS_TYPE_IPV4TCP; 513 } 514 515 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 516 return E1000_MRQ_RSS_TYPE_IPV4; 517 } 518 } else if (hasip6) { 519 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 520 521 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 522 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 523 524 /* 525 * Following two traces must not be combined because resulting 526 * event will have 11 arguments totally and some trace backends 527 * (at least "ust") have limitation of maximum 10 arguments per 528 * event. Events with more arguments fail to compile for 529 * backends like these. 530 */ 531 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 532 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, hastcp, 533 ip6info->has_ext_hdrs, 534 ip6info->rss_ex_dst_valid, 535 ip6info->rss_ex_src_valid, 536 core->mac[MRQC], 537 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 538 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 539 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 540 541 if ((!ex_dis || !ip6info->has_ext_hdrs) && 542 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 543 ip6info->rss_ex_src_valid))) { 544 545 if (hastcp && E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 546 return E1000_MRQ_RSS_TYPE_IPV6TCP; 547 } 548 549 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 550 return E1000_MRQ_RSS_TYPE_IPV6EX; 551 } 552 553 } 554 555 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 556 return E1000_MRQ_RSS_TYPE_IPV6; 557 } 558 559 } 560 561 return E1000_MRQ_RSS_TYPE_NONE; 562 } 563 564 static uint32_t 565 e1000e_rss_calc_hash(E1000ECore *core, 566 struct NetRxPkt *pkt, 567 E1000E_RSSInfo *info) 568 { 569 NetRxPktRssType type; 570 571 assert(e1000e_rss_enabled(core)); 572 573 switch (info->type) { 574 case E1000_MRQ_RSS_TYPE_IPV4: 575 type = NetPktRssIpV4; 576 break; 577 case E1000_MRQ_RSS_TYPE_IPV4TCP: 578 type = NetPktRssIpV4Tcp; 579 break; 580 case E1000_MRQ_RSS_TYPE_IPV6TCP: 581 type = NetPktRssIpV6TcpEx; 582 break; 583 case E1000_MRQ_RSS_TYPE_IPV6: 584 type = NetPktRssIpV6; 585 break; 586 case E1000_MRQ_RSS_TYPE_IPV6EX: 587 type = NetPktRssIpV6Ex; 588 break; 589 default: 590 assert(false); 591 return 0; 592 } 593 594 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 595 } 596 597 static void 598 e1000e_rss_parse_packet(E1000ECore *core, 599 struct NetRxPkt *pkt, 600 E1000E_RSSInfo *info) 601 { 602 trace_e1000e_rx_rss_started(); 603 604 if (!e1000e_rss_enabled(core)) { 605 info->enabled = false; 606 info->hash = 0; 607 info->queue = 0; 608 info->type = 0; 609 trace_e1000e_rx_rss_disabled(); 610 return; 611 } 612 613 info->enabled = true; 614 615 info->type = e1000e_rss_get_hash_type(core, pkt); 616 617 trace_e1000e_rx_rss_type(info->type); 618 619 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 620 info->hash = 0; 621 info->queue = 0; 622 return; 623 } 624 625 info->hash = e1000e_rss_calc_hash(core, pkt, info); 626 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 627 } 628 629 static bool 630 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 631 { 632 if (tx->props.tse && tx->cptse) { 633 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 634 return false; 635 } 636 637 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 638 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 639 return true; 640 } 641 642 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 643 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 644 return false; 645 } 646 } 647 648 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 649 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 650 } 651 652 return true; 653 } 654 655 static void e1000e_tx_pkt_callback(void *core, 656 const struct iovec *iov, 657 int iovcnt, 658 const struct iovec *virt_iov, 659 int virt_iovcnt) 660 { 661 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 662 } 663 664 static bool 665 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 666 { 667 int target_queue = MIN(core->max_queue_num, queue_index); 668 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 669 670 if (!e1000e_setup_tx_offloads(core, tx)) { 671 return false; 672 } 673 674 net_tx_pkt_dump(tx->tx_pkt); 675 676 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 677 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 678 return net_tx_pkt_send_custom(tx->tx_pkt, false, 679 e1000e_tx_pkt_callback, core); 680 } else { 681 return net_tx_pkt_send(tx->tx_pkt, queue); 682 } 683 } 684 685 static void 686 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 687 { 688 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 689 PTC1023, PTC1522 }; 690 691 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 692 693 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 694 e1000x_inc_reg_if_not_full(core->mac, TPT); 695 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 696 697 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 698 case ETH_PKT_BCAST: 699 e1000x_inc_reg_if_not_full(core->mac, BPTC); 700 break; 701 case ETH_PKT_MCAST: 702 e1000x_inc_reg_if_not_full(core->mac, MPTC); 703 break; 704 case ETH_PKT_UCAST: 705 break; 706 default: 707 g_assert_not_reached(); 708 } 709 710 core->mac[GPTC] = core->mac[TPT]; 711 core->mac[GOTCL] = core->mac[TOTL]; 712 core->mac[GOTCH] = core->mac[TOTH]; 713 } 714 715 static void 716 e1000e_process_tx_desc(E1000ECore *core, 717 struct e1000e_tx *tx, 718 struct e1000_tx_desc *dp, 719 int queue_index) 720 { 721 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 722 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 723 unsigned int split_size = txd_lower & 0xffff; 724 uint64_t addr; 725 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 726 bool eop = txd_lower & E1000_TXD_CMD_EOP; 727 728 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 729 e1000x_read_tx_ctx_descr(xp, &tx->props); 730 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 731 return; 732 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 733 /* data descriptor */ 734 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 735 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 736 e1000e_process_ts_option(core, dp); 737 } else { 738 /* legacy descriptor */ 739 e1000e_process_ts_option(core, dp); 740 tx->cptse = 0; 741 } 742 743 addr = le64_to_cpu(dp->buffer_addr); 744 745 if (!tx->skip_cp) { 746 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) { 747 tx->skip_cp = true; 748 } 749 } 750 751 if (eop) { 752 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 753 if (e1000x_vlan_enabled(core->mac) && 754 e1000x_is_vlan_txd(txd_lower)) { 755 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 756 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 757 } 758 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 759 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 760 } 761 } 762 763 tx->skip_cp = false; 764 net_tx_pkt_reset(tx->tx_pkt); 765 766 tx->sum_needed = 0; 767 tx->cptse = 0; 768 } 769 } 770 771 static inline uint32_t 772 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 773 { 774 if (!msix_enabled(core->owner)) { 775 return E1000_ICR_TXDW; 776 } 777 778 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 779 } 780 781 static inline uint32_t 782 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 783 bool min_threshold_hit) 784 { 785 if (!msix_enabled(core->owner)) { 786 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 787 } 788 789 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 790 } 791 792 static uint32_t 793 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 794 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 795 { 796 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 797 798 if (!(txd_lower & E1000_TXD_CMD_RS) && 799 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 800 return 0; 801 } 802 803 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 804 805 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 806 807 dp->upper.data = cpu_to_le32(txd_upper); 808 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 809 &dp->upper, sizeof(dp->upper)); 810 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 811 } 812 813 typedef struct E1000E_RingInfo_st { 814 int dbah; 815 int dbal; 816 int dlen; 817 int dh; 818 int dt; 819 int idx; 820 } E1000E_RingInfo; 821 822 static inline bool 823 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 824 { 825 return core->mac[r->dh] == core->mac[r->dt] || 826 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 827 } 828 829 static inline uint64_t 830 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 831 { 832 uint64_t bah = core->mac[r->dbah]; 833 uint64_t bal = core->mac[r->dbal]; 834 835 return (bah << 32) + bal; 836 } 837 838 static inline uint64_t 839 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 840 { 841 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 842 } 843 844 static inline void 845 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 846 { 847 core->mac[r->dh] += count; 848 849 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 850 core->mac[r->dh] = 0; 851 } 852 } 853 854 static inline uint32_t 855 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 856 { 857 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 858 core->mac[r->dh], core->mac[r->dt]); 859 860 if (core->mac[r->dh] <= core->mac[r->dt]) { 861 return core->mac[r->dt] - core->mac[r->dh]; 862 } 863 864 if (core->mac[r->dh] > core->mac[r->dt]) { 865 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 866 core->mac[r->dt] - core->mac[r->dh]; 867 } 868 869 g_assert_not_reached(); 870 return 0; 871 } 872 873 static inline bool 874 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 875 { 876 return core->mac[r->dlen] > 0; 877 } 878 879 static inline uint32_t 880 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 881 { 882 return core->mac[r->dlen]; 883 } 884 885 typedef struct E1000E_TxRing_st { 886 const E1000E_RingInfo *i; 887 struct e1000e_tx *tx; 888 } E1000E_TxRing; 889 890 static inline int 891 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 892 { 893 return (reg_idx - base_reg_idx) / (0x100 >> 2); 894 } 895 896 static inline void 897 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 898 { 899 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 900 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 901 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 902 }; 903 904 assert(idx < ARRAY_SIZE(i)); 905 906 txr->i = &i[idx]; 907 txr->tx = &core->tx[idx]; 908 } 909 910 typedef struct E1000E_RxRing_st { 911 const E1000E_RingInfo *i; 912 } E1000E_RxRing; 913 914 static inline void 915 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 916 { 917 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 918 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 919 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 920 }; 921 922 assert(idx < ARRAY_SIZE(i)); 923 924 rxr->i = &i[idx]; 925 } 926 927 static void 928 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 929 { 930 dma_addr_t base; 931 struct e1000_tx_desc desc; 932 bool ide = false; 933 const E1000E_RingInfo *txi = txr->i; 934 uint32_t cause = E1000_ICS_TXQE; 935 936 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 937 trace_e1000e_tx_disabled(); 938 return; 939 } 940 941 while (!e1000e_ring_empty(core, txi)) { 942 base = e1000e_ring_head_descr(core, txi); 943 944 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 945 946 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 947 desc.lower.data, desc.upper.data); 948 949 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 950 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 951 952 e1000e_ring_advance(core, txi, 1); 953 } 954 955 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 956 e1000e_set_interrupt_cause(core, cause); 957 } 958 } 959 960 static bool 961 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 962 size_t total_size) 963 { 964 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 965 966 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 967 core->rx_desc_buf_size); 968 969 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 970 core->rx_desc_buf_size; 971 } 972 973 void 974 e1000e_start_recv(E1000ECore *core) 975 { 976 int i; 977 978 trace_e1000e_rx_start_recv(); 979 980 for (i = 0; i <= core->max_queue_num; i++) { 981 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 982 } 983 } 984 985 bool 986 e1000e_can_receive(E1000ECore *core) 987 { 988 int i; 989 990 if (!e1000x_rx_ready(core->owner, core->mac)) { 991 return false; 992 } 993 994 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 995 E1000E_RxRing rxr; 996 997 e1000e_rx_ring_init(core, &rxr, i); 998 if (e1000e_ring_enabled(core, rxr.i) && 999 e1000e_has_rxbufs(core, rxr.i, 1)) { 1000 trace_e1000e_rx_can_recv(); 1001 return true; 1002 } 1003 } 1004 1005 trace_e1000e_rx_can_recv_rings_full(); 1006 return false; 1007 } 1008 1009 ssize_t 1010 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 1011 { 1012 const struct iovec iov = { 1013 .iov_base = (uint8_t *)buf, 1014 .iov_len = size 1015 }; 1016 1017 return e1000e_receive_iov(core, &iov, 1); 1018 } 1019 1020 static inline bool 1021 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1022 { 1023 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1024 } 1025 1026 static inline bool 1027 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1028 { 1029 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1030 } 1031 1032 static bool 1033 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size) 1034 { 1035 uint32_t rctl = core->mac[RCTL]; 1036 1037 if (e1000x_is_vlan_packet(buf, core->mac[VET]) && 1038 e1000x_vlan_rx_filter_enabled(core->mac)) { 1039 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(buf)->h_tci); 1040 uint32_t vfta = 1041 ldl_le_p((uint32_t *)(core->mac + VFTA) + 1042 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK)); 1043 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) { 1044 trace_e1000e_rx_flt_vlan_mismatch(vid); 1045 return false; 1046 } else { 1047 trace_e1000e_rx_flt_vlan_match(vid); 1048 } 1049 } 1050 1051 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1052 case ETH_PKT_UCAST: 1053 if (rctl & E1000_RCTL_UPE) { 1054 return true; /* promiscuous ucast */ 1055 } 1056 break; 1057 1058 case ETH_PKT_BCAST: 1059 if (rctl & E1000_RCTL_BAM) { 1060 return true; /* broadcast enabled */ 1061 } 1062 break; 1063 1064 case ETH_PKT_MCAST: 1065 if (rctl & E1000_RCTL_MPE) { 1066 return true; /* promiscuous mcast */ 1067 } 1068 break; 1069 1070 default: 1071 g_assert_not_reached(); 1072 } 1073 1074 return e1000x_rx_group_filter(core->mac, buf); 1075 } 1076 1077 static inline void 1078 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1079 hwaddr *buff_addr) 1080 { 1081 *buff_addr = le64_to_cpu(desc->buffer_addr); 1082 } 1083 1084 static inline void 1085 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1086 hwaddr *buff_addr) 1087 { 1088 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1089 } 1090 1091 static inline void 1092 e1000e_read_ps_rx_descr(E1000ECore *core, 1093 union e1000_rx_desc_packet_split *desc, 1094 hwaddr buff_addr[MAX_PS_BUFFERS]) 1095 { 1096 int i; 1097 1098 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1099 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1100 } 1101 1102 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1103 buff_addr[2], buff_addr[3]); 1104 } 1105 1106 static inline void 1107 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1108 hwaddr buff_addr[MAX_PS_BUFFERS]) 1109 { 1110 if (e1000e_rx_use_legacy_descriptor(core)) { 1111 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1112 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1113 } else { 1114 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1115 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1116 } else { 1117 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1118 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1119 } 1120 } 1121 } 1122 1123 static void 1124 e1000e_verify_csum_in_sw(E1000ECore *core, 1125 struct NetRxPkt *pkt, 1126 uint32_t *status_flags, 1127 bool hastcp, bool hasudp) 1128 { 1129 bool csum_valid; 1130 uint32_t csum_error; 1131 1132 if (e1000e_rx_l3_cso_enabled(core)) { 1133 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1134 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1135 } else { 1136 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1137 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1138 } 1139 } else { 1140 trace_e1000e_rx_metadata_l3_cso_disabled(); 1141 } 1142 1143 if (!e1000e_rx_l4_cso_enabled(core)) { 1144 trace_e1000e_rx_metadata_l4_cso_disabled(); 1145 return; 1146 } 1147 1148 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1149 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1150 return; 1151 } 1152 1153 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1154 1155 if (hastcp) { 1156 *status_flags |= E1000_RXD_STAT_TCPCS | 1157 csum_error; 1158 } else if (hasudp) { 1159 *status_flags |= E1000_RXD_STAT_TCPCS | 1160 E1000_RXD_STAT_UDPCS | 1161 csum_error; 1162 } 1163 } 1164 1165 static inline bool 1166 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1167 { 1168 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1169 return false; 1170 } 1171 1172 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1173 return !net_rx_pkt_has_tcp_data(rx_pkt); 1174 } 1175 1176 return true; 1177 } 1178 1179 static void 1180 e1000e_build_rx_metadata(E1000ECore *core, 1181 struct NetRxPkt *pkt, 1182 bool is_eop, 1183 const E1000E_RSSInfo *rss_info, 1184 uint32_t *rss, uint32_t *mrq, 1185 uint32_t *status_flags, 1186 uint16_t *ip_id, 1187 uint16_t *vlan_tag) 1188 { 1189 struct virtio_net_hdr *vhdr; 1190 bool hasip4, hasip6, hastcp, hasudp; 1191 uint32_t pkt_type; 1192 1193 *status_flags = E1000_RXD_STAT_DD; 1194 1195 /* No additional metadata needed for non-EOP descriptors */ 1196 if (!is_eop) { 1197 goto func_exit; 1198 } 1199 1200 *status_flags |= E1000_RXD_STAT_EOP; 1201 1202 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &hasudp, &hastcp); 1203 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, hasudp, hastcp); 1204 1205 /* VLAN state */ 1206 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1207 *status_flags |= E1000_RXD_STAT_VP; 1208 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1209 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1210 } 1211 1212 /* Packet parsing results */ 1213 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1214 if (rss_info->enabled) { 1215 *rss = cpu_to_le32(rss_info->hash); 1216 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1217 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1218 } 1219 } else if (hasip4) { 1220 *status_flags |= E1000_RXD_STAT_IPIDV; 1221 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1222 trace_e1000e_rx_metadata_ip_id(*ip_id); 1223 } 1224 1225 if (hastcp && e1000e_is_tcp_ack(core, pkt)) { 1226 *status_flags |= E1000_RXD_STAT_ACK; 1227 trace_e1000e_rx_metadata_ack(); 1228 } 1229 1230 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1231 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1232 pkt_type = E1000_RXD_PKT_MAC; 1233 } else if (hastcp || hasudp) { 1234 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1235 } else if (hasip4 || hasip6) { 1236 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1237 } else { 1238 pkt_type = E1000_RXD_PKT_MAC; 1239 } 1240 1241 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1242 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1243 1244 /* RX CSO information */ 1245 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1246 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1247 goto func_exit; 1248 } 1249 1250 vhdr = net_rx_pkt_get_vhdr(pkt); 1251 1252 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1253 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1254 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1255 e1000e_verify_csum_in_sw(core, pkt, status_flags, hastcp, hasudp); 1256 goto func_exit; 1257 } 1258 1259 if (e1000e_rx_l3_cso_enabled(core)) { 1260 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1261 } else { 1262 trace_e1000e_rx_metadata_l3_cso_disabled(); 1263 } 1264 1265 if (e1000e_rx_l4_cso_enabled(core)) { 1266 if (hastcp) { 1267 *status_flags |= E1000_RXD_STAT_TCPCS; 1268 } else if (hasudp) { 1269 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1270 } 1271 } else { 1272 trace_e1000e_rx_metadata_l4_cso_disabled(); 1273 } 1274 1275 trace_e1000e_rx_metadata_status_flags(*status_flags); 1276 1277 func_exit: 1278 *status_flags = cpu_to_le32(*status_flags); 1279 } 1280 1281 static inline void 1282 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1283 struct NetRxPkt *pkt, 1284 const E1000E_RSSInfo *rss_info, 1285 uint16_t length) 1286 { 1287 uint32_t status_flags, rss, mrq; 1288 uint16_t ip_id; 1289 1290 assert(!rss_info->enabled); 1291 1292 desc->length = cpu_to_le16(length); 1293 desc->csum = 0; 1294 1295 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1296 rss_info, 1297 &rss, &mrq, 1298 &status_flags, &ip_id, 1299 &desc->special); 1300 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1301 desc->status = (uint8_t) le32_to_cpu(status_flags); 1302 } 1303 1304 static inline void 1305 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1306 struct NetRxPkt *pkt, 1307 const E1000E_RSSInfo *rss_info, 1308 uint16_t length) 1309 { 1310 memset(&desc->wb, 0, sizeof(desc->wb)); 1311 1312 desc->wb.upper.length = cpu_to_le16(length); 1313 1314 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1315 rss_info, 1316 &desc->wb.lower.hi_dword.rss, 1317 &desc->wb.lower.mrq, 1318 &desc->wb.upper.status_error, 1319 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1320 &desc->wb.upper.vlan); 1321 } 1322 1323 static inline void 1324 e1000e_write_ps_rx_descr(E1000ECore *core, 1325 union e1000_rx_desc_packet_split *desc, 1326 struct NetRxPkt *pkt, 1327 const E1000E_RSSInfo *rss_info, 1328 size_t ps_hdr_len, 1329 uint16_t(*written)[MAX_PS_BUFFERS]) 1330 { 1331 int i; 1332 1333 memset(&desc->wb, 0, sizeof(desc->wb)); 1334 1335 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1336 1337 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1338 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1339 } 1340 1341 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1342 rss_info, 1343 &desc->wb.lower.hi_dword.rss, 1344 &desc->wb.lower.mrq, 1345 &desc->wb.middle.status_error, 1346 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1347 &desc->wb.middle.vlan); 1348 1349 desc->wb.upper.header_status = 1350 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1351 1352 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1353 (*written)[2], (*written)[3]); 1354 } 1355 1356 static inline void 1357 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1358 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1359 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1360 { 1361 if (e1000e_rx_use_legacy_descriptor(core)) { 1362 assert(ps_hdr_len == 0); 1363 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1364 (*written)[0]); 1365 } else { 1366 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1367 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1368 ps_hdr_len, written); 1369 } else { 1370 assert(ps_hdr_len == 0); 1371 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1372 (*written)[0]); 1373 } 1374 } 1375 } 1376 1377 static inline void 1378 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1379 union e1000_rx_desc_union *desc, dma_addr_t len) 1380 { 1381 PCIDevice *dev = core->owner; 1382 1383 if (e1000e_rx_use_legacy_descriptor(core)) { 1384 struct e1000_rx_desc *d = &desc->legacy; 1385 size_t offset = offsetof(struct e1000_rx_desc, status); 1386 uint8_t status = d->status; 1387 1388 d->status &= ~E1000_RXD_STAT_DD; 1389 pci_dma_write(dev, addr, desc, len); 1390 1391 if (status & E1000_RXD_STAT_DD) { 1392 d->status = status; 1393 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1394 } 1395 } else { 1396 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1397 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1398 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1399 wb.middle.status_error); 1400 uint32_t status = d->wb.middle.status_error; 1401 1402 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1403 pci_dma_write(dev, addr, desc, len); 1404 1405 if (status & E1000_RXD_STAT_DD) { 1406 d->wb.middle.status_error = status; 1407 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1408 } 1409 } else { 1410 union e1000_rx_desc_extended *d = &desc->extended; 1411 size_t offset = offsetof(union e1000_rx_desc_extended, 1412 wb.upper.status_error); 1413 uint32_t status = d->wb.upper.status_error; 1414 1415 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1416 pci_dma_write(dev, addr, desc, len); 1417 1418 if (status & E1000_RXD_STAT_DD) { 1419 d->wb.upper.status_error = status; 1420 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1421 } 1422 } 1423 } 1424 } 1425 1426 typedef struct e1000e_ba_state_st { 1427 uint16_t written[MAX_PS_BUFFERS]; 1428 uint8_t cur_idx; 1429 } e1000e_ba_state; 1430 1431 static inline void 1432 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1433 hwaddr ba[MAX_PS_BUFFERS], 1434 e1000e_ba_state *bastate, 1435 const char *data, 1436 dma_addr_t data_len) 1437 { 1438 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1439 1440 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1441 bastate->written[0] += data_len; 1442 1443 bastate->cur_idx = 1; 1444 } 1445 1446 static void 1447 e1000e_write_to_rx_buffers(E1000ECore *core, 1448 hwaddr ba[MAX_PS_BUFFERS], 1449 e1000e_ba_state *bastate, 1450 const char *data, 1451 dma_addr_t data_len) 1452 { 1453 while (data_len > 0) { 1454 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1455 uint32_t cur_buf_bytes_left = cur_buf_len - 1456 bastate->written[bastate->cur_idx]; 1457 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1458 1459 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1460 ba[bastate->cur_idx], 1461 bastate->written[bastate->cur_idx], 1462 data, 1463 bytes_to_write); 1464 1465 pci_dma_write(core->owner, 1466 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1467 data, bytes_to_write); 1468 1469 bastate->written[bastate->cur_idx] += bytes_to_write; 1470 data += bytes_to_write; 1471 data_len -= bytes_to_write; 1472 1473 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1474 bastate->cur_idx++; 1475 } 1476 1477 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1478 } 1479 } 1480 1481 static void 1482 e1000e_update_rx_stats(E1000ECore *core, 1483 size_t data_size, 1484 size_t data_fcs_size) 1485 { 1486 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size); 1487 1488 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1489 case ETH_PKT_BCAST: 1490 e1000x_inc_reg_if_not_full(core->mac, BPRC); 1491 break; 1492 1493 case ETH_PKT_MCAST: 1494 e1000x_inc_reg_if_not_full(core->mac, MPRC); 1495 break; 1496 1497 default: 1498 break; 1499 } 1500 } 1501 1502 static inline bool 1503 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1504 { 1505 return e1000e_ring_free_descr_num(core, rxi) == 1506 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1507 } 1508 1509 static bool 1510 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1511 { 1512 bool hasip4, hasip6, hasudp, hastcp; 1513 bool fragment; 1514 1515 if (!e1000e_rx_use_ps_descriptor(core)) { 1516 return false; 1517 } 1518 1519 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &hasudp, &hastcp); 1520 1521 if (hasip4) { 1522 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1523 } else if (hasip6) { 1524 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1525 } else { 1526 return false; 1527 } 1528 1529 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1530 return false; 1531 } 1532 1533 if (hasudp || hastcp) { 1534 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1535 } else { 1536 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1537 } 1538 1539 if ((*hdr_len > core->rxbuf_sizes[0]) || 1540 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1541 return false; 1542 } 1543 1544 return true; 1545 } 1546 1547 static void 1548 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1549 const E1000E_RxRing *rxr, 1550 const E1000E_RSSInfo *rss_info) 1551 { 1552 PCIDevice *d = core->owner; 1553 dma_addr_t base; 1554 union e1000_rx_desc_union desc; 1555 size_t desc_size; 1556 size_t desc_offset = 0; 1557 size_t iov_ofs = 0; 1558 1559 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1560 size_t size = net_rx_pkt_get_total_len(pkt); 1561 size_t total_size = size + e1000x_fcs_len(core->mac); 1562 const E1000E_RingInfo *rxi; 1563 size_t ps_hdr_len = 0; 1564 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1565 bool is_first = true; 1566 1567 rxi = rxr->i; 1568 1569 do { 1570 hwaddr ba[MAX_PS_BUFFERS]; 1571 e1000e_ba_state bastate = { { 0 } }; 1572 bool is_last = false; 1573 1574 desc_size = total_size - desc_offset; 1575 1576 if (desc_size > core->rx_desc_buf_size) { 1577 desc_size = core->rx_desc_buf_size; 1578 } 1579 1580 if (e1000e_ring_empty(core, rxi)) { 1581 return; 1582 } 1583 1584 base = e1000e_ring_head_descr(core, rxi); 1585 1586 pci_dma_read(d, base, &desc, core->rx_desc_len); 1587 1588 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1589 1590 e1000e_read_rx_descr(core, &desc, ba); 1591 1592 if (ba[0]) { 1593 if (desc_offset < size) { 1594 static const uint32_t fcs_pad; 1595 size_t iov_copy; 1596 size_t copy_size = size - desc_offset; 1597 if (copy_size > core->rx_desc_buf_size) { 1598 copy_size = core->rx_desc_buf_size; 1599 } 1600 1601 /* For PS mode copy the packet header first */ 1602 if (do_ps) { 1603 if (is_first) { 1604 size_t ps_hdr_copied = 0; 1605 do { 1606 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1607 iov->iov_len - iov_ofs); 1608 1609 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1610 iov->iov_base, iov_copy); 1611 1612 copy_size -= iov_copy; 1613 ps_hdr_copied += iov_copy; 1614 1615 iov_ofs += iov_copy; 1616 if (iov_ofs == iov->iov_len) { 1617 iov++; 1618 iov_ofs = 0; 1619 } 1620 } while (ps_hdr_copied < ps_hdr_len); 1621 1622 is_first = false; 1623 } else { 1624 /* Leave buffer 0 of each descriptor except first */ 1625 /* empty as per spec 7.1.5.1 */ 1626 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1627 NULL, 0); 1628 } 1629 } 1630 1631 /* Copy packet payload */ 1632 while (copy_size) { 1633 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1634 1635 e1000e_write_to_rx_buffers(core, ba, &bastate, 1636 iov->iov_base + iov_ofs, iov_copy); 1637 1638 copy_size -= iov_copy; 1639 iov_ofs += iov_copy; 1640 if (iov_ofs == iov->iov_len) { 1641 iov++; 1642 iov_ofs = 0; 1643 } 1644 } 1645 1646 if (desc_offset + desc_size >= total_size) { 1647 /* Simulate FCS checksum presence in the last descriptor */ 1648 e1000e_write_to_rx_buffers(core, ba, &bastate, 1649 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1650 } 1651 } 1652 } else { /* as per intel docs; skip descriptors with null buf addr */ 1653 trace_e1000e_rx_null_descriptor(); 1654 } 1655 desc_offset += desc_size; 1656 if (desc_offset >= total_size) { 1657 is_last = true; 1658 } 1659 1660 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1661 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1662 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1663 1664 e1000e_ring_advance(core, rxi, 1665 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1666 1667 } while (desc_offset < total_size); 1668 1669 e1000e_update_rx_stats(core, size, total_size); 1670 } 1671 1672 static inline void 1673 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1674 { 1675 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1676 1677 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1678 net_rx_pkt_fix_l4_csum(pkt); 1679 } 1680 } 1681 1682 ssize_t 1683 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1684 { 1685 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1686 } 1687 1688 static ssize_t 1689 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1690 bool has_vnet) 1691 { 1692 static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4); 1693 1694 uint32_t n = 0; 1695 uint8_t min_buf[ETH_ZLEN]; 1696 struct iovec min_iov; 1697 uint8_t *filter_buf; 1698 size_t size, orig_size; 1699 size_t iov_ofs = 0; 1700 E1000E_RxRing rxr; 1701 E1000E_RSSInfo rss_info; 1702 size_t total_size; 1703 ssize_t retval; 1704 bool rdmts_hit; 1705 1706 trace_e1000e_rx_receive_iov(iovcnt); 1707 1708 if (!e1000x_hw_rx_enabled(core->mac)) { 1709 return -1; 1710 } 1711 1712 /* Pull virtio header in */ 1713 if (has_vnet) { 1714 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1715 iov_ofs = sizeof(struct virtio_net_hdr); 1716 } else { 1717 net_rx_pkt_unset_vhdr(core->rx_pkt); 1718 } 1719 1720 filter_buf = iov->iov_base + iov_ofs; 1721 orig_size = iov_size(iov, iovcnt); 1722 size = orig_size - iov_ofs; 1723 1724 /* Pad to minimum Ethernet frame length */ 1725 if (size < sizeof(min_buf)) { 1726 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size); 1727 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1728 e1000x_inc_reg_if_not_full(core->mac, RUC); 1729 min_iov.iov_base = filter_buf = min_buf; 1730 min_iov.iov_len = size = sizeof(min_buf); 1731 iovcnt = 1; 1732 iov = &min_iov; 1733 iov_ofs = 0; 1734 } else if (iov->iov_len < maximum_ethernet_hdr_len) { 1735 /* This is very unlikely, but may happen. */ 1736 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len); 1737 filter_buf = min_buf; 1738 } 1739 1740 /* Discard oversized packets if !LPE and !SBP. */ 1741 if (e1000x_is_oversized(core->mac, size)) { 1742 return orig_size; 1743 } 1744 1745 net_rx_pkt_set_packet_type(core->rx_pkt, 1746 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf))); 1747 1748 if (!e1000e_receive_filter(core, filter_buf, size)) { 1749 trace_e1000e_rx_flt_dropped(); 1750 return orig_size; 1751 } 1752 1753 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1754 e1000x_vlan_enabled(core->mac), core->mac[VET]); 1755 1756 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1757 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1758 1759 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1760 e1000x_fcs_len(core->mac); 1761 1762 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1763 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1764 1765 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1766 1767 retval = orig_size; 1768 1769 /* Perform small receive detection (RSRPD) */ 1770 if (total_size < core->mac[RSRPD]) { 1771 n |= E1000_ICS_SRPD; 1772 } 1773 1774 /* Perform ACK receive detection */ 1775 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1776 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1777 n |= E1000_ICS_ACK; 1778 } 1779 1780 /* Check if receive descriptor minimum threshold hit */ 1781 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1782 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1783 1784 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1785 } else { 1786 n |= E1000_ICS_RXO; 1787 retval = 0; 1788 1789 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1790 } 1791 1792 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) { 1793 trace_e1000e_rx_interrupt_set(n); 1794 e1000e_set_interrupt_cause(core, n); 1795 } else { 1796 trace_e1000e_rx_interrupt_delayed(n); 1797 } 1798 1799 return retval; 1800 } 1801 1802 static inline bool 1803 e1000e_have_autoneg(E1000ECore *core) 1804 { 1805 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1806 } 1807 1808 static void e1000e_update_flowctl_status(E1000ECore *core) 1809 { 1810 if (e1000e_have_autoneg(core) && 1811 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1812 trace_e1000e_link_autoneg_flowctl(true); 1813 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1814 } else { 1815 trace_e1000e_link_autoneg_flowctl(false); 1816 } 1817 } 1818 1819 static inline void 1820 e1000e_link_down(E1000ECore *core) 1821 { 1822 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1823 e1000e_update_flowctl_status(core); 1824 } 1825 1826 static inline void 1827 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1828 { 1829 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1830 core->phy[0][MII_BMCR] = val & ~(0x3f | 1831 MII_BMCR_RESET | 1832 MII_BMCR_ANRESTART); 1833 1834 if ((val & MII_BMCR_ANRESTART) && 1835 e1000e_have_autoneg(core)) { 1836 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1837 } 1838 } 1839 1840 static void 1841 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1842 { 1843 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1844 1845 if (val & BIT(10)) { 1846 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1847 } 1848 } 1849 1850 static void 1851 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1852 { 1853 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1854 } 1855 1856 void 1857 e1000e_core_set_link_status(E1000ECore *core) 1858 { 1859 NetClientState *nc = qemu_get_queue(core->owner_nic); 1860 uint32_t old_status = core->mac[STATUS]; 1861 1862 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1863 1864 if (nc->link_down) { 1865 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1866 } else { 1867 if (e1000e_have_autoneg(core) && 1868 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1869 e1000x_restart_autoneg(core->mac, core->phy[0], 1870 core->autoneg_timer); 1871 } else { 1872 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1873 e1000e_start_recv(core); 1874 } 1875 } 1876 1877 if (core->mac[STATUS] != old_status) { 1878 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1879 } 1880 } 1881 1882 static void 1883 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1884 { 1885 trace_e1000e_core_ctrl_write(index, val); 1886 1887 /* RST is self clearing */ 1888 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1889 core->mac[CTRL_DUP] = core->mac[CTRL]; 1890 1891 trace_e1000e_link_set_params( 1892 !!(val & E1000_CTRL_ASDE), 1893 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1894 !!(val & E1000_CTRL_FRCSPD), 1895 !!(val & E1000_CTRL_FRCDPX), 1896 !!(val & E1000_CTRL_RFCE), 1897 !!(val & E1000_CTRL_TFCE)); 1898 1899 if (val & E1000_CTRL_RST) { 1900 trace_e1000e_core_ctrl_sw_reset(); 1901 e1000e_reset(core, true); 1902 } 1903 1904 if (val & E1000_CTRL_PHY_RST) { 1905 trace_e1000e_core_ctrl_phy_reset(); 1906 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1907 } 1908 } 1909 1910 static void 1911 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1912 { 1913 trace_e1000e_rx_set_rfctl(val); 1914 1915 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1916 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1917 } 1918 1919 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1920 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1921 } 1922 1923 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1924 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1925 } 1926 1927 core->mac[RFCTL] = val; 1928 } 1929 1930 static void 1931 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1932 { 1933 int i; 1934 core->rx_desc_buf_size = 0; 1935 1936 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1937 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1938 } 1939 } 1940 1941 static void 1942 e1000e_parse_rxbufsize(E1000ECore *core) 1943 { 1944 uint32_t rctl = core->mac[RCTL]; 1945 1946 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1947 1948 if (rctl & E1000_RCTL_DTYP_MASK) { 1949 uint32_t bsize; 1950 1951 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1952 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1953 1954 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1955 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1956 1957 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1958 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1959 1960 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1961 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1962 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1963 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1964 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1965 } else { 1966 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1967 } 1968 1969 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1970 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1971 1972 e1000e_calc_per_desc_buf_size(core); 1973 } 1974 1975 static void 1976 e1000e_calc_rxdesclen(E1000ECore *core) 1977 { 1978 if (e1000e_rx_use_legacy_descriptor(core)) { 1979 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1980 } else { 1981 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1982 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1983 } else { 1984 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1985 } 1986 } 1987 trace_e1000e_rx_desc_len(core->rx_desc_len); 1988 } 1989 1990 static void 1991 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1992 { 1993 core->mac[RCTL] = val; 1994 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1995 1996 if (val & E1000_RCTL_EN) { 1997 e1000e_parse_rxbufsize(core); 1998 e1000e_calc_rxdesclen(core); 1999 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 2000 E1000_RING_DESC_LEN_SHIFT; 2001 2002 e1000e_start_recv(core); 2003 } 2004 } 2005 2006 static 2007 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 2008 (E1000ECore *, int, uint16_t) = { 2009 [0] = { 2010 [MII_BMCR] = e1000e_set_phy_ctrl, 2011 [PHY_PAGE] = e1000e_set_phy_page, 2012 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 2013 } 2014 }; 2015 2016 static inline void 2017 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits) 2018 { 2019 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 2020 core->mac[IMS] &= ~bits; 2021 } 2022 2023 static inline bool 2024 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 2025 { 2026 if (timer->running) { 2027 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 2028 2029 return true; 2030 } 2031 2032 if (timer->core->mac[timer->delay_reg] != 0) { 2033 e1000e_intrmgr_rearm_timer(timer); 2034 } 2035 2036 return false; 2037 } 2038 2039 static inline bool 2040 e1000e_itr_should_postpone(E1000ECore *core) 2041 { 2042 return e1000e_postpone_interrupt(&core->itr); 2043 } 2044 2045 static inline bool 2046 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 2047 { 2048 return e1000e_postpone_interrupt(&core->eitr[idx]); 2049 } 2050 2051 static void 2052 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2053 { 2054 uint32_t effective_eiac; 2055 2056 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2057 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2058 if (vec < E1000E_MSIX_VEC_NUM) { 2059 if (!e1000e_eitr_should_postpone(core, vec)) { 2060 trace_e1000e_irq_msix_notify_vec(vec); 2061 msix_notify(core->owner, vec); 2062 } 2063 } else { 2064 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2065 } 2066 } else { 2067 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2068 } 2069 2070 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2071 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2072 core->mac[IAM] &= ~cause; 2073 } 2074 2075 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2076 2077 effective_eiac = core->mac[EIAC] & cause; 2078 2079 core->mac[ICR] &= ~effective_eiac; 2080 core->msi_causes_pending &= ~effective_eiac; 2081 2082 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2083 core->mac[IMS] &= ~effective_eiac; 2084 } 2085 } 2086 2087 static void 2088 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2089 { 2090 if (causes & E1000_ICR_RXQ0) { 2091 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2092 E1000_IVAR_RXQ0(core->mac[IVAR])); 2093 } 2094 2095 if (causes & E1000_ICR_RXQ1) { 2096 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2097 E1000_IVAR_RXQ1(core->mac[IVAR])); 2098 } 2099 2100 if (causes & E1000_ICR_TXQ0) { 2101 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2102 E1000_IVAR_TXQ0(core->mac[IVAR])); 2103 } 2104 2105 if (causes & E1000_ICR_TXQ1) { 2106 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2107 E1000_IVAR_TXQ1(core->mac[IVAR])); 2108 } 2109 2110 if (causes & E1000_ICR_OTHER) { 2111 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2112 E1000_IVAR_OTHER(core->mac[IVAR])); 2113 } 2114 } 2115 2116 static void 2117 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2118 { 2119 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2120 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2121 if (vec < E1000E_MSIX_VEC_NUM) { 2122 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2123 msix_clr_pending(core->owner, vec); 2124 } else { 2125 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2126 } 2127 } else { 2128 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2129 } 2130 } 2131 2132 static void 2133 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2134 { 2135 if (causes & E1000_ICR_RXQ0) { 2136 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2137 E1000_IVAR_RXQ0(core->mac[IVAR])); 2138 } 2139 2140 if (causes & E1000_ICR_RXQ1) { 2141 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2142 E1000_IVAR_RXQ1(core->mac[IVAR])); 2143 } 2144 2145 if (causes & E1000_ICR_TXQ0) { 2146 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2147 E1000_IVAR_TXQ0(core->mac[IVAR])); 2148 } 2149 2150 if (causes & E1000_ICR_TXQ1) { 2151 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2152 E1000_IVAR_TXQ1(core->mac[IVAR])); 2153 } 2154 2155 if (causes & E1000_ICR_OTHER) { 2156 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2157 E1000_IVAR_OTHER(core->mac[IVAR])); 2158 } 2159 } 2160 2161 static inline void 2162 e1000e_fix_icr_asserted(E1000ECore *core) 2163 { 2164 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2165 if (core->mac[ICR]) { 2166 core->mac[ICR] |= E1000_ICR_ASSERTED; 2167 } 2168 2169 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2170 } 2171 2172 static void 2173 e1000e_send_msi(E1000ECore *core, bool msix) 2174 { 2175 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED; 2176 2177 core->msi_causes_pending &= causes; 2178 causes ^= core->msi_causes_pending; 2179 if (causes == 0) { 2180 return; 2181 } 2182 core->msi_causes_pending |= causes; 2183 2184 if (msix) { 2185 e1000e_msix_notify(core, causes); 2186 } else { 2187 if (!e1000e_itr_should_postpone(core)) { 2188 trace_e1000e_irq_msi_notify(causes); 2189 msi_notify(core->owner, 0); 2190 } 2191 } 2192 } 2193 2194 static void 2195 e1000e_update_interrupt_state(E1000ECore *core) 2196 { 2197 bool interrupts_pending; 2198 bool is_msix = msix_enabled(core->owner); 2199 2200 /* Set ICR[OTHER] for MSI-X */ 2201 if (is_msix) { 2202 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2203 core->mac[ICR] |= E1000_ICR_OTHER; 2204 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2205 } 2206 } 2207 2208 e1000e_fix_icr_asserted(core); 2209 2210 /* 2211 * Make sure ICR and ICS registers have the same value. 2212 * The spec says that the ICS register is write-only. However in practice, 2213 * on real hardware ICS is readable, and for reads it has the same value as 2214 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2215 * 2216 * The VxWorks PRO/1000 driver uses this behaviour. 2217 */ 2218 core->mac[ICS] = core->mac[ICR]; 2219 2220 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false; 2221 if (!interrupts_pending) { 2222 core->msi_causes_pending = 0; 2223 } 2224 2225 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2226 core->mac[ICR], core->mac[IMS]); 2227 2228 if (is_msix || msi_enabled(core->owner)) { 2229 if (interrupts_pending) { 2230 e1000e_send_msi(core, is_msix); 2231 } 2232 } else { 2233 if (interrupts_pending) { 2234 if (!e1000e_itr_should_postpone(core)) { 2235 e1000e_raise_legacy_irq(core); 2236 } 2237 } else { 2238 e1000e_lower_legacy_irq(core); 2239 } 2240 } 2241 } 2242 2243 static void 2244 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2245 { 2246 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 2247 2248 val |= e1000e_intmgr_collect_delayed_causes(core); 2249 core->mac[ICR] |= val; 2250 2251 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 2252 2253 e1000e_update_interrupt_state(core); 2254 } 2255 2256 static inline void 2257 e1000e_autoneg_timer(void *opaque) 2258 { 2259 E1000ECore *core = opaque; 2260 if (!qemu_get_queue(core->owner_nic)->link_down) { 2261 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2262 e1000e_start_recv(core); 2263 2264 e1000e_update_flowctl_status(core); 2265 /* signal link status change to the guest */ 2266 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2267 } 2268 } 2269 2270 static inline uint16_t 2271 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2272 { 2273 uint16_t index = (addr & 0x1ffff) >> 2; 2274 return index + (mac_reg_access[index] & 0xfffe); 2275 } 2276 2277 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2278 [0] = { 2279 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2280 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2281 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2282 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2283 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2284 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2285 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2286 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2287 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2288 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2289 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2290 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2291 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2292 2293 [PHY_COPPER_CTRL1] = PHY_RW, 2294 [PHY_COPPER_STAT1] = PHY_R, 2295 [PHY_COPPER_CTRL3] = PHY_RW, 2296 [PHY_RX_ERR_CNTR] = PHY_R, 2297 [PHY_OEM_BITS] = PHY_RW, 2298 [PHY_BIAS_1] = PHY_RW, 2299 [PHY_BIAS_2] = PHY_RW, 2300 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2301 [PHY_COPPER_STAT2] = PHY_R, 2302 [PHY_COPPER_CTRL2] = PHY_RW 2303 }, 2304 [2] = { 2305 [PHY_MAC_CTRL1] = PHY_RW, 2306 [PHY_MAC_INT_ENABLE] = PHY_RW, 2307 [PHY_MAC_STAT] = PHY_R, 2308 [PHY_MAC_CTRL2] = PHY_RW 2309 }, 2310 [3] = { 2311 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2312 [PHY_LED_03_POL_CTRL] = PHY_RW, 2313 [PHY_LED_TIMER_CTRL] = PHY_RW, 2314 [PHY_LED_45_CTRL] = PHY_RW 2315 }, 2316 [5] = { 2317 [PHY_1000T_SKEW] = PHY_R, 2318 [PHY_1000T_SWAP] = PHY_R 2319 }, 2320 [6] = { 2321 [PHY_CRC_COUNTERS] = PHY_R 2322 } 2323 }; 2324 2325 static bool 2326 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2327 char cap, uint8_t *page) 2328 { 2329 *page = 2330 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2331 : core->phy[0][PHY_PAGE]; 2332 2333 if (*page >= E1000E_PHY_PAGES) { 2334 return false; 2335 } 2336 2337 return e1000e_phy_regcap[*page][addr] & cap; 2338 } 2339 2340 static void 2341 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2342 uint32_t addr, uint16_t data) 2343 { 2344 assert(page < E1000E_PHY_PAGES); 2345 assert(addr < E1000E_PHY_PAGE_SIZE); 2346 2347 if (e1000e_phyreg_writeops[page][addr]) { 2348 e1000e_phyreg_writeops[page][addr](core, addr, data); 2349 } else { 2350 core->phy[page][addr] = data; 2351 } 2352 } 2353 2354 static void 2355 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2356 { 2357 uint32_t data = val & E1000_MDIC_DATA_MASK; 2358 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2359 uint8_t page; 2360 2361 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2362 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2363 } else if (val & E1000_MDIC_OP_READ) { 2364 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2365 trace_e1000e_core_mdic_read_unhandled(page, addr); 2366 val |= E1000_MDIC_ERROR; 2367 } else { 2368 val = (val ^ data) | core->phy[page][addr]; 2369 trace_e1000e_core_mdic_read(page, addr, val); 2370 } 2371 } else if (val & E1000_MDIC_OP_WRITE) { 2372 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2373 trace_e1000e_core_mdic_write_unhandled(page, addr); 2374 val |= E1000_MDIC_ERROR; 2375 } else { 2376 trace_e1000e_core_mdic_write(page, addr, data); 2377 e1000e_phy_reg_write(core, page, addr, data); 2378 } 2379 } 2380 core->mac[MDIC] = val | E1000_MDIC_READY; 2381 2382 if (val & E1000_MDIC_INT_EN) { 2383 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2384 } 2385 } 2386 2387 static void 2388 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2389 { 2390 core->mac[index] = val & 0xffff; 2391 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2392 e1000e_start_recv(core); 2393 } 2394 2395 static void 2396 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2397 { 2398 if ((val & E1000_STATUS_PHYRA) == 0) { 2399 core->mac[index] &= ~E1000_STATUS_PHYRA; 2400 } 2401 } 2402 2403 static void 2404 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2405 { 2406 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2407 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2408 2409 /* Zero self-clearing bits */ 2410 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2411 core->mac[CTRL_EXT] = val; 2412 } 2413 2414 static void 2415 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2416 { 2417 int i; 2418 2419 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2420 2421 if (!msix_enabled(core->owner)) { 2422 return; 2423 } 2424 2425 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2426 if (core->mac[PBACLR] & BIT(i)) { 2427 msix_clr_pending(core->owner, i); 2428 } 2429 } 2430 } 2431 2432 static void 2433 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2434 { 2435 core->mac[FCRTH] = val & 0xFFF8; 2436 } 2437 2438 static void 2439 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2440 { 2441 core->mac[FCRTL] = val & 0x8000FFF8; 2442 } 2443 2444 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2445 static void \ 2446 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2447 { \ 2448 core->mac[index] = val & (BIT(num) - 1); \ 2449 } 2450 2451 E1000E_LOW_BITS_SET_FUNC(4) 2452 E1000E_LOW_BITS_SET_FUNC(6) 2453 E1000E_LOW_BITS_SET_FUNC(11) 2454 E1000E_LOW_BITS_SET_FUNC(12) 2455 E1000E_LOW_BITS_SET_FUNC(13) 2456 E1000E_LOW_BITS_SET_FUNC(16) 2457 2458 static void 2459 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2460 { 2461 core->mac[VET] = val & 0xffff; 2462 trace_e1000e_vlan_vet(core->mac[VET]); 2463 } 2464 2465 static void 2466 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2467 { 2468 core->mac[index] = val & E1000_XDLEN_MASK; 2469 } 2470 2471 static void 2472 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2473 { 2474 core->mac[index] = val & E1000_XDBAL_MASK; 2475 } 2476 2477 static void 2478 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2479 { 2480 E1000E_TxRing txr; 2481 core->mac[index] = val; 2482 2483 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2484 e1000e_tx_ring_init(core, &txr, 0); 2485 e1000e_start_xmit(core, &txr); 2486 } 2487 2488 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2489 e1000e_tx_ring_init(core, &txr, 1); 2490 e1000e_start_xmit(core, &txr); 2491 } 2492 } 2493 2494 static void 2495 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2496 { 2497 E1000E_TxRing txr; 2498 int qidx = e1000e_mq_queue_idx(TDT, index); 2499 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2500 2501 core->mac[index] = val & 0xffff; 2502 2503 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2504 e1000e_tx_ring_init(core, &txr, qidx); 2505 e1000e_start_xmit(core, &txr); 2506 } 2507 } 2508 2509 static void 2510 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2511 { 2512 trace_e1000e_irq_write_ics(val); 2513 e1000e_set_interrupt_cause(core, val); 2514 } 2515 2516 static void 2517 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2518 { 2519 uint32_t icr = 0; 2520 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2521 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2522 trace_e1000e_irq_icr_process_iame(); 2523 e1000e_clear_ims_bits(core, core->mac[IAM]); 2524 } 2525 2526 icr = core->mac[ICR] & ~val; 2527 /* 2528 * Windows driver expects that the "receive overrun" bit and other 2529 * ones to be cleared when the "Other" bit (#24) is cleared. 2530 */ 2531 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr; 2532 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr); 2533 core->mac[ICR] = icr; 2534 e1000e_update_interrupt_state(core); 2535 } 2536 2537 static void 2538 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2539 { 2540 trace_e1000e_irq_ims_clear_set_imc(val); 2541 e1000e_clear_ims_bits(core, val); 2542 e1000e_update_interrupt_state(core); 2543 } 2544 2545 static void 2546 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2547 { 2548 static const uint32_t ims_ext_mask = 2549 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2550 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2551 E1000_IMS_OTHER; 2552 2553 static const uint32_t ims_valid_mask = 2554 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2555 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2556 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2557 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2558 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2559 E1000_IMS_OTHER; 2560 2561 uint32_t valid_val = val & ims_valid_mask; 2562 2563 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2564 core->mac[IMS] |= valid_val; 2565 2566 if ((valid_val & ims_ext_mask) && 2567 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2568 msix_enabled(core->owner)) { 2569 e1000e_msix_clear(core, valid_val); 2570 } 2571 2572 if ((valid_val == ims_valid_mask) && 2573 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2574 trace_e1000e_irq_fire_all_timers(val); 2575 e1000e_intrmgr_fire_all_timers(core); 2576 } 2577 2578 e1000e_update_interrupt_state(core); 2579 } 2580 2581 static void 2582 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2583 { 2584 e1000e_set_16bit(core, index, val); 2585 2586 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2587 trace_e1000e_irq_rdtr_fpd_running(); 2588 e1000e_intrmgr_fire_delayed_interrupts(core); 2589 } else { 2590 trace_e1000e_irq_rdtr_fpd_not_running(); 2591 } 2592 } 2593 2594 static void 2595 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2596 { 2597 e1000e_set_16bit(core, index, val); 2598 2599 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2600 trace_e1000e_irq_tidv_fpd_running(); 2601 e1000e_intrmgr_fire_delayed_interrupts(core); 2602 } else { 2603 trace_e1000e_irq_tidv_fpd_not_running(); 2604 } 2605 } 2606 2607 static uint32_t 2608 e1000e_mac_readreg(E1000ECore *core, int index) 2609 { 2610 return core->mac[index]; 2611 } 2612 2613 static uint32_t 2614 e1000e_mac_ics_read(E1000ECore *core, int index) 2615 { 2616 trace_e1000e_irq_read_ics(core->mac[ICS]); 2617 return core->mac[ICS]; 2618 } 2619 2620 static uint32_t 2621 e1000e_mac_ims_read(E1000ECore *core, int index) 2622 { 2623 trace_e1000e_irq_read_ims(core->mac[IMS]); 2624 return core->mac[IMS]; 2625 } 2626 2627 static uint32_t 2628 e1000e_mac_swsm_read(E1000ECore *core, int index) 2629 { 2630 uint32_t val = core->mac[SWSM]; 2631 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2632 return val; 2633 } 2634 2635 static uint32_t 2636 e1000e_mac_itr_read(E1000ECore *core, int index) 2637 { 2638 return core->itr_guest_value; 2639 } 2640 2641 static uint32_t 2642 e1000e_mac_eitr_read(E1000ECore *core, int index) 2643 { 2644 return core->eitr_guest_value[index - EITR]; 2645 } 2646 2647 static uint32_t 2648 e1000e_mac_icr_read(E1000ECore *core, int index) 2649 { 2650 uint32_t ret = core->mac[ICR]; 2651 trace_e1000e_irq_icr_read_entry(ret); 2652 2653 if (core->mac[IMS] == 0) { 2654 trace_e1000e_irq_icr_clear_zero_ims(); 2655 core->mac[ICR] = 0; 2656 } 2657 2658 if (!msix_enabled(core->owner)) { 2659 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2660 core->mac[ICR] = 0; 2661 } 2662 2663 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2664 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2665 trace_e1000e_irq_icr_clear_iame(); 2666 core->mac[ICR] = 0; 2667 trace_e1000e_irq_icr_process_iame(); 2668 e1000e_clear_ims_bits(core, core->mac[IAM]); 2669 } 2670 2671 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2672 e1000e_update_interrupt_state(core); 2673 return ret; 2674 } 2675 2676 static uint32_t 2677 e1000e_mac_read_clr4(E1000ECore *core, int index) 2678 { 2679 uint32_t ret = core->mac[index]; 2680 2681 core->mac[index] = 0; 2682 return ret; 2683 } 2684 2685 static uint32_t 2686 e1000e_mac_read_clr8(E1000ECore *core, int index) 2687 { 2688 uint32_t ret = core->mac[index]; 2689 2690 core->mac[index] = 0; 2691 core->mac[index - 1] = 0; 2692 return ret; 2693 } 2694 2695 static uint32_t 2696 e1000e_get_ctrl(E1000ECore *core, int index) 2697 { 2698 uint32_t val = core->mac[CTRL]; 2699 2700 trace_e1000e_link_read_params( 2701 !!(val & E1000_CTRL_ASDE), 2702 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2703 !!(val & E1000_CTRL_FRCSPD), 2704 !!(val & E1000_CTRL_FRCDPX), 2705 !!(val & E1000_CTRL_RFCE), 2706 !!(val & E1000_CTRL_TFCE)); 2707 2708 return val; 2709 } 2710 2711 static uint32_t 2712 e1000e_get_status(E1000ECore *core, int index) 2713 { 2714 uint32_t res = core->mac[STATUS]; 2715 2716 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2717 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2718 } 2719 2720 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2721 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2722 } else { 2723 res |= E1000_STATUS_FD; 2724 } 2725 2726 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2727 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2728 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2729 case E1000_CTRL_SPD_10: 2730 res |= E1000_STATUS_SPEED_10; 2731 break; 2732 case E1000_CTRL_SPD_100: 2733 res |= E1000_STATUS_SPEED_100; 2734 break; 2735 case E1000_CTRL_SPD_1000: 2736 default: 2737 res |= E1000_STATUS_SPEED_1000; 2738 break; 2739 } 2740 } else { 2741 res |= E1000_STATUS_SPEED_1000; 2742 } 2743 2744 trace_e1000e_link_status( 2745 !!(res & E1000_STATUS_LU), 2746 !!(res & E1000_STATUS_FD), 2747 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2748 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2749 2750 return res; 2751 } 2752 2753 static uint32_t 2754 e1000e_get_tarc(E1000ECore *core, int index) 2755 { 2756 return core->mac[index] & ((BIT(11) - 1) | 2757 BIT(27) | 2758 BIT(28) | 2759 BIT(29) | 2760 BIT(30)); 2761 } 2762 2763 static void 2764 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2765 { 2766 core->mac[index] = val; 2767 } 2768 2769 static void 2770 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2771 { 2772 uint32_t macaddr[2]; 2773 2774 core->mac[index] = val; 2775 2776 macaddr[0] = cpu_to_le32(core->mac[RA]); 2777 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2778 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2779 (uint8_t *) macaddr); 2780 2781 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2782 } 2783 2784 static void 2785 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2786 { 2787 static const uint32_t ro_bits = E1000_EECD_PRES | 2788 E1000_EECD_AUTO_RD | 2789 E1000_EECD_SIZE_EX_MASK; 2790 2791 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2792 } 2793 2794 static void 2795 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2796 { 2797 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2798 uint32_t flags = 0; 2799 uint32_t data = 0; 2800 2801 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2802 data = core->eeprom[addr]; 2803 flags = E1000_EERW_DONE; 2804 } 2805 2806 core->mac[EERD] = flags | 2807 (addr << E1000_EERW_ADDR_SHIFT) | 2808 (data << E1000_EERW_DATA_SHIFT); 2809 } 2810 2811 static void 2812 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2813 { 2814 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2815 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2816 uint32_t flags = 0; 2817 2818 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2819 core->eeprom[addr] = data; 2820 flags = E1000_EERW_DONE; 2821 } 2822 2823 core->mac[EERD] = flags | 2824 (addr << E1000_EERW_ADDR_SHIFT) | 2825 (data << E1000_EERW_DATA_SHIFT); 2826 } 2827 2828 static void 2829 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2830 { 2831 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2832 } 2833 2834 static void 2835 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2836 { 2837 uint32_t interval = val & 0xffff; 2838 2839 trace_e1000e_irq_itr_set(val); 2840 2841 core->itr_guest_value = interval; 2842 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2843 } 2844 2845 static void 2846 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2847 { 2848 uint32_t interval = val & 0xffff; 2849 uint32_t eitr_num = index - EITR; 2850 2851 trace_e1000e_irq_eitr_set(eitr_num, val); 2852 2853 core->eitr_guest_value[eitr_num] = interval; 2854 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2855 } 2856 2857 static void 2858 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2859 { 2860 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2861 2862 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2863 qemu_log_mask(LOG_GUEST_ERROR, 2864 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2865 return; 2866 } 2867 2868 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2869 qemu_log_mask(LOG_GUEST_ERROR, 2870 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2871 return; 2872 } 2873 } 2874 2875 core->mac[PSRCTL] = val; 2876 } 2877 2878 static void 2879 e1000e_update_rx_offloads(E1000ECore *core) 2880 { 2881 int cso_state = e1000e_rx_l4_cso_enabled(core); 2882 2883 trace_e1000e_rx_set_cso(cso_state); 2884 2885 if (core->has_vnet) { 2886 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2887 cso_state, 0, 0, 0, 0); 2888 } 2889 } 2890 2891 static void 2892 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2893 { 2894 core->mac[RXCSUM] = val; 2895 e1000e_update_rx_offloads(core); 2896 } 2897 2898 static void 2899 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2900 { 2901 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2902 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2903 } 2904 2905 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2906 typedef uint32_t (*readops)(E1000ECore *, int); 2907 static const readops e1000e_macreg_readops[] = { 2908 e1000e_getreg(PBA), 2909 e1000e_getreg(WUFC), 2910 e1000e_getreg(MANC), 2911 e1000e_getreg(TOTL), 2912 e1000e_getreg(RDT0), 2913 e1000e_getreg(RDBAH0), 2914 e1000e_getreg(TDBAL1), 2915 e1000e_getreg(RDLEN0), 2916 e1000e_getreg(RDH1), 2917 e1000e_getreg(LATECOL), 2918 e1000e_getreg(SEQEC), 2919 e1000e_getreg(XONTXC), 2920 e1000e_getreg(AIT), 2921 e1000e_getreg(TDFH), 2922 e1000e_getreg(TDFT), 2923 e1000e_getreg(TDFHS), 2924 e1000e_getreg(TDFTS), 2925 e1000e_getreg(TDFPC), 2926 e1000e_getreg(WUS), 2927 e1000e_getreg(PBS), 2928 e1000e_getreg(RDFH), 2929 e1000e_getreg(RDFT), 2930 e1000e_getreg(RDFHS), 2931 e1000e_getreg(RDFTS), 2932 e1000e_getreg(RDFPC), 2933 e1000e_getreg(GORCL), 2934 e1000e_getreg(MGTPRC), 2935 e1000e_getreg(EERD), 2936 e1000e_getreg(EIAC), 2937 e1000e_getreg(PSRCTL), 2938 e1000e_getreg(MANC2H), 2939 e1000e_getreg(RXCSUM), 2940 e1000e_getreg(GSCL_3), 2941 e1000e_getreg(GSCN_2), 2942 e1000e_getreg(RSRPD), 2943 e1000e_getreg(RDBAL1), 2944 e1000e_getreg(FCAH), 2945 e1000e_getreg(FCRTH), 2946 e1000e_getreg(FLOP), 2947 e1000e_getreg(FLASHT), 2948 e1000e_getreg(RXSTMPH), 2949 e1000e_getreg(TXSTMPL), 2950 e1000e_getreg(TIMADJL), 2951 e1000e_getreg(TXDCTL), 2952 e1000e_getreg(RDH0), 2953 e1000e_getreg(TDT1), 2954 e1000e_getreg(TNCRS), 2955 e1000e_getreg(RJC), 2956 e1000e_getreg(IAM), 2957 e1000e_getreg(GSCL_2), 2958 e1000e_getreg(RDBAH1), 2959 e1000e_getreg(FLSWDATA), 2960 e1000e_getreg(RXSATRH), 2961 e1000e_getreg(TIPG), 2962 e1000e_getreg(FLMNGCTL), 2963 e1000e_getreg(FLMNGCNT), 2964 e1000e_getreg(TSYNCTXCTL), 2965 e1000e_getreg(EXTCNF_SIZE), 2966 e1000e_getreg(EXTCNF_CTRL), 2967 e1000e_getreg(EEMNGDATA), 2968 e1000e_getreg(CTRL_EXT), 2969 e1000e_getreg(SYSTIMH), 2970 e1000e_getreg(EEMNGCTL), 2971 e1000e_getreg(FLMNGDATA), 2972 e1000e_getreg(TSYNCRXCTL), 2973 e1000e_getreg(TDH), 2974 e1000e_getreg(LEDCTL), 2975 e1000e_getreg(TCTL), 2976 e1000e_getreg(TDBAL), 2977 e1000e_getreg(TDLEN), 2978 e1000e_getreg(TDH1), 2979 e1000e_getreg(RADV), 2980 e1000e_getreg(ECOL), 2981 e1000e_getreg(DC), 2982 e1000e_getreg(RLEC), 2983 e1000e_getreg(XOFFTXC), 2984 e1000e_getreg(RFC), 2985 e1000e_getreg(RNBC), 2986 e1000e_getreg(MGTPTC), 2987 e1000e_getreg(TIMINCA), 2988 e1000e_getreg(RXCFGL), 2989 e1000e_getreg(MFUTP01), 2990 e1000e_getreg(FACTPS), 2991 e1000e_getreg(GSCL_1), 2992 e1000e_getreg(GSCN_0), 2993 e1000e_getreg(GCR2), 2994 e1000e_getreg(RDT1), 2995 e1000e_getreg(PBACLR), 2996 e1000e_getreg(FCTTV), 2997 e1000e_getreg(EEWR), 2998 e1000e_getreg(FLSWCTL), 2999 e1000e_getreg(RXDCTL1), 3000 e1000e_getreg(RXSATRL), 3001 e1000e_getreg(SYSTIML), 3002 e1000e_getreg(RXUDP), 3003 e1000e_getreg(TORL), 3004 e1000e_getreg(TDLEN1), 3005 e1000e_getreg(MCC), 3006 e1000e_getreg(WUC), 3007 e1000e_getreg(EECD), 3008 e1000e_getreg(MFUTP23), 3009 e1000e_getreg(RAID), 3010 e1000e_getreg(FCRTV), 3011 e1000e_getreg(TXDCTL1), 3012 e1000e_getreg(RCTL), 3013 e1000e_getreg(TDT), 3014 e1000e_getreg(MDIC), 3015 e1000e_getreg(FCRUC), 3016 e1000e_getreg(VET), 3017 e1000e_getreg(RDBAL0), 3018 e1000e_getreg(TDBAH1), 3019 e1000e_getreg(RDTR), 3020 e1000e_getreg(SCC), 3021 e1000e_getreg(COLC), 3022 e1000e_getreg(CEXTERR), 3023 e1000e_getreg(XOFFRXC), 3024 e1000e_getreg(IPAV), 3025 e1000e_getreg(GOTCL), 3026 e1000e_getreg(MGTPDC), 3027 e1000e_getreg(GCR), 3028 e1000e_getreg(IVAR), 3029 e1000e_getreg(POEMB), 3030 e1000e_getreg(MFVAL), 3031 e1000e_getreg(FUNCTAG), 3032 e1000e_getreg(GSCL_4), 3033 e1000e_getreg(GSCN_3), 3034 e1000e_getreg(MRQC), 3035 e1000e_getreg(RDLEN1), 3036 e1000e_getreg(FCT), 3037 e1000e_getreg(FLA), 3038 e1000e_getreg(FLOL), 3039 e1000e_getreg(RXDCTL), 3040 e1000e_getreg(RXSTMPL), 3041 e1000e_getreg(TXSTMPH), 3042 e1000e_getreg(TIMADJH), 3043 e1000e_getreg(FCRTL), 3044 e1000e_getreg(TDBAH), 3045 e1000e_getreg(TADV), 3046 e1000e_getreg(XONRXC), 3047 e1000e_getreg(TSCTFC), 3048 e1000e_getreg(RFCTL), 3049 e1000e_getreg(GSCN_1), 3050 e1000e_getreg(FCAL), 3051 e1000e_getreg(FLSWCNT), 3052 3053 [TOTH] = e1000e_mac_read_clr8, 3054 [GOTCH] = e1000e_mac_read_clr8, 3055 [PRC64] = e1000e_mac_read_clr4, 3056 [PRC255] = e1000e_mac_read_clr4, 3057 [PRC1023] = e1000e_mac_read_clr4, 3058 [PTC64] = e1000e_mac_read_clr4, 3059 [PTC255] = e1000e_mac_read_clr4, 3060 [PTC1023] = e1000e_mac_read_clr4, 3061 [GPRC] = e1000e_mac_read_clr4, 3062 [TPT] = e1000e_mac_read_clr4, 3063 [RUC] = e1000e_mac_read_clr4, 3064 [BPRC] = e1000e_mac_read_clr4, 3065 [MPTC] = e1000e_mac_read_clr4, 3066 [IAC] = e1000e_mac_read_clr4, 3067 [ICR] = e1000e_mac_icr_read, 3068 [STATUS] = e1000e_get_status, 3069 [TARC0] = e1000e_get_tarc, 3070 [ICS] = e1000e_mac_ics_read, 3071 [TORH] = e1000e_mac_read_clr8, 3072 [GORCH] = e1000e_mac_read_clr8, 3073 [PRC127] = e1000e_mac_read_clr4, 3074 [PRC511] = e1000e_mac_read_clr4, 3075 [PRC1522] = e1000e_mac_read_clr4, 3076 [PTC127] = e1000e_mac_read_clr4, 3077 [PTC511] = e1000e_mac_read_clr4, 3078 [PTC1522] = e1000e_mac_read_clr4, 3079 [GPTC] = e1000e_mac_read_clr4, 3080 [TPR] = e1000e_mac_read_clr4, 3081 [ROC] = e1000e_mac_read_clr4, 3082 [MPRC] = e1000e_mac_read_clr4, 3083 [BPTC] = e1000e_mac_read_clr4, 3084 [TSCTC] = e1000e_mac_read_clr4, 3085 [ITR] = e1000e_mac_itr_read, 3086 [CTRL] = e1000e_get_ctrl, 3087 [TARC1] = e1000e_get_tarc, 3088 [SWSM] = e1000e_mac_swsm_read, 3089 [IMS] = e1000e_mac_ims_read, 3090 3091 [CRCERRS ... MPC] = e1000e_mac_readreg, 3092 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3093 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3094 [RA ... RA + 31] = e1000e_mac_readreg, 3095 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3096 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3097 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3098 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3099 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3100 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3101 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3102 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3103 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3104 [RETA ... RETA + 31] = e1000e_mac_readreg, 3105 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3106 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3107 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3108 }; 3109 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3110 3111 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3112 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3113 static const writeops e1000e_macreg_writeops[] = { 3114 e1000e_putreg(PBA), 3115 e1000e_putreg(SWSM), 3116 e1000e_putreg(WUFC), 3117 e1000e_putreg(RDBAH1), 3118 e1000e_putreg(TDBAH), 3119 e1000e_putreg(TXDCTL), 3120 e1000e_putreg(RDBAH0), 3121 e1000e_putreg(LEDCTL), 3122 e1000e_putreg(FCAL), 3123 e1000e_putreg(FCRUC), 3124 e1000e_putreg(WUC), 3125 e1000e_putreg(WUS), 3126 e1000e_putreg(IPAV), 3127 e1000e_putreg(TDBAH1), 3128 e1000e_putreg(TIMINCA), 3129 e1000e_putreg(IAM), 3130 e1000e_putreg(EIAC), 3131 e1000e_putreg(IVAR), 3132 e1000e_putreg(TARC0), 3133 e1000e_putreg(TARC1), 3134 e1000e_putreg(FLSWDATA), 3135 e1000e_putreg(POEMB), 3136 e1000e_putreg(MFUTP01), 3137 e1000e_putreg(MFUTP23), 3138 e1000e_putreg(MANC), 3139 e1000e_putreg(MANC2H), 3140 e1000e_putreg(MFVAL), 3141 e1000e_putreg(EXTCNF_CTRL), 3142 e1000e_putreg(FACTPS), 3143 e1000e_putreg(FUNCTAG), 3144 e1000e_putreg(GSCL_1), 3145 e1000e_putreg(GSCL_2), 3146 e1000e_putreg(GSCL_3), 3147 e1000e_putreg(GSCL_4), 3148 e1000e_putreg(GSCN_0), 3149 e1000e_putreg(GSCN_1), 3150 e1000e_putreg(GSCN_2), 3151 e1000e_putreg(GSCN_3), 3152 e1000e_putreg(GCR2), 3153 e1000e_putreg(MRQC), 3154 e1000e_putreg(FLOP), 3155 e1000e_putreg(FLOL), 3156 e1000e_putreg(FLSWCTL), 3157 e1000e_putreg(FLSWCNT), 3158 e1000e_putreg(FLA), 3159 e1000e_putreg(RXDCTL1), 3160 e1000e_putreg(TXDCTL1), 3161 e1000e_putreg(TIPG), 3162 e1000e_putreg(RXSTMPH), 3163 e1000e_putreg(RXSTMPL), 3164 e1000e_putreg(RXSATRL), 3165 e1000e_putreg(RXSATRH), 3166 e1000e_putreg(TXSTMPL), 3167 e1000e_putreg(TXSTMPH), 3168 e1000e_putreg(SYSTIML), 3169 e1000e_putreg(SYSTIMH), 3170 e1000e_putreg(TIMADJL), 3171 e1000e_putreg(TIMADJH), 3172 e1000e_putreg(RXUDP), 3173 e1000e_putreg(RXCFGL), 3174 e1000e_putreg(TSYNCRXCTL), 3175 e1000e_putreg(TSYNCTXCTL), 3176 e1000e_putreg(EXTCNF_SIZE), 3177 e1000e_putreg(EEMNGCTL), 3178 e1000e_putreg(RA), 3179 3180 [TDH1] = e1000e_set_16bit, 3181 [TDT1] = e1000e_set_tdt, 3182 [TCTL] = e1000e_set_tctl, 3183 [TDT] = e1000e_set_tdt, 3184 [MDIC] = e1000e_set_mdic, 3185 [ICS] = e1000e_set_ics, 3186 [TDH] = e1000e_set_16bit, 3187 [RDH0] = e1000e_set_16bit, 3188 [RDT0] = e1000e_set_rdt, 3189 [IMC] = e1000e_set_imc, 3190 [IMS] = e1000e_set_ims, 3191 [ICR] = e1000e_set_icr, 3192 [EECD] = e1000e_set_eecd, 3193 [RCTL] = e1000e_set_rx_control, 3194 [CTRL] = e1000e_set_ctrl, 3195 [RDTR] = e1000e_set_rdtr, 3196 [RADV] = e1000e_set_16bit, 3197 [TADV] = e1000e_set_16bit, 3198 [ITR] = e1000e_set_itr, 3199 [EERD] = e1000e_set_eerd, 3200 [AIT] = e1000e_set_16bit, 3201 [TDFH] = e1000e_set_13bit, 3202 [TDFT] = e1000e_set_13bit, 3203 [TDFHS] = e1000e_set_13bit, 3204 [TDFTS] = e1000e_set_13bit, 3205 [TDFPC] = e1000e_set_13bit, 3206 [RDFH] = e1000e_set_13bit, 3207 [RDFHS] = e1000e_set_13bit, 3208 [RDFT] = e1000e_set_13bit, 3209 [RDFTS] = e1000e_set_13bit, 3210 [RDFPC] = e1000e_set_13bit, 3211 [PBS] = e1000e_set_6bit, 3212 [GCR] = e1000e_set_gcr, 3213 [PSRCTL] = e1000e_set_psrctl, 3214 [RXCSUM] = e1000e_set_rxcsum, 3215 [RAID] = e1000e_set_16bit, 3216 [RSRPD] = e1000e_set_12bit, 3217 [TIDV] = e1000e_set_tidv, 3218 [TDLEN1] = e1000e_set_dlen, 3219 [TDLEN] = e1000e_set_dlen, 3220 [RDLEN0] = e1000e_set_dlen, 3221 [RDLEN1] = e1000e_set_dlen, 3222 [TDBAL] = e1000e_set_dbal, 3223 [TDBAL1] = e1000e_set_dbal, 3224 [RDBAL0] = e1000e_set_dbal, 3225 [RDBAL1] = e1000e_set_dbal, 3226 [RDH1] = e1000e_set_16bit, 3227 [RDT1] = e1000e_set_rdt, 3228 [STATUS] = e1000e_set_status, 3229 [PBACLR] = e1000e_set_pbaclr, 3230 [CTRL_EXT] = e1000e_set_ctrlext, 3231 [FCAH] = e1000e_set_16bit, 3232 [FCT] = e1000e_set_16bit, 3233 [FCTTV] = e1000e_set_16bit, 3234 [FCRTV] = e1000e_set_16bit, 3235 [FCRTH] = e1000e_set_fcrth, 3236 [FCRTL] = e1000e_set_fcrtl, 3237 [VET] = e1000e_set_vet, 3238 [RXDCTL] = e1000e_set_rxdctl, 3239 [FLASHT] = e1000e_set_16bit, 3240 [EEWR] = e1000e_set_eewr, 3241 [CTRL_DUP] = e1000e_set_ctrl, 3242 [RFCTL] = e1000e_set_rfctl, 3243 [RA + 1] = e1000e_mac_setmacaddr, 3244 3245 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3246 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3247 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3248 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3249 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3250 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3251 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3252 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3253 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3254 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3255 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3256 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3257 [RETA ... RETA + 31] = e1000e_mac_writereg, 3258 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3259 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3260 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3261 }; 3262 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3263 3264 enum { MAC_ACCESS_PARTIAL = 1 }; 3265 3266 /* 3267 * The array below combines alias offsets of the index values for the 3268 * MAC registers that have aliases, with the indication of not fully 3269 * implemented registers (lowest bit). This combination is possible 3270 * because all of the offsets are even. 3271 */ 3272 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3273 /* Alias index offsets */ 3274 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3275 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3276 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3277 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3278 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3279 [RA_A ... RA_A + 31] = 0x14f0, 3280 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3281 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3282 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3283 /* Access options */ 3284 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3285 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3286 [RDFPC] = MAC_ACCESS_PARTIAL, 3287 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3288 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3289 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3290 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3291 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3292 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3293 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3294 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3295 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3296 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3297 }; 3298 3299 void 3300 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3301 { 3302 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3303 3304 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3305 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3306 trace_e1000e_wrn_regs_write_trivial(index << 2); 3307 } 3308 trace_e1000e_core_write(index << 2, size, val); 3309 e1000e_macreg_writeops[index](core, index, val); 3310 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3311 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3312 } else { 3313 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3314 } 3315 } 3316 3317 uint64_t 3318 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3319 { 3320 uint64_t val; 3321 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3322 3323 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3324 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3325 trace_e1000e_wrn_regs_read_trivial(index << 2); 3326 } 3327 val = e1000e_macreg_readops[index](core, index); 3328 trace_e1000e_core_read(index << 2, size, val); 3329 return val; 3330 } else { 3331 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3332 } 3333 return 0; 3334 } 3335 3336 static inline void 3337 e1000e_autoneg_pause(E1000ECore *core) 3338 { 3339 timer_del(core->autoneg_timer); 3340 } 3341 3342 static void 3343 e1000e_autoneg_resume(E1000ECore *core) 3344 { 3345 if (e1000e_have_autoneg(core) && 3346 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3347 qemu_get_queue(core->owner_nic)->link_down = false; 3348 timer_mod(core->autoneg_timer, 3349 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3350 } 3351 } 3352 3353 static void 3354 e1000e_vm_state_change(void *opaque, bool running, RunState state) 3355 { 3356 E1000ECore *core = opaque; 3357 3358 if (running) { 3359 trace_e1000e_vm_state_running(); 3360 e1000e_intrmgr_resume(core); 3361 e1000e_autoneg_resume(core); 3362 } else { 3363 trace_e1000e_vm_state_stopped(); 3364 e1000e_autoneg_pause(core); 3365 e1000e_intrmgr_pause(core); 3366 } 3367 } 3368 3369 void 3370 e1000e_core_pci_realize(E1000ECore *core, 3371 const uint16_t *eeprom_templ, 3372 uint32_t eeprom_size, 3373 const uint8_t *macaddr) 3374 { 3375 int i; 3376 3377 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3378 e1000e_autoneg_timer, core); 3379 e1000e_intrmgr_pci_realize(core); 3380 3381 core->vmstate = 3382 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3383 3384 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3385 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner, E1000E_MAX_TX_FRAGS); 3386 } 3387 3388 net_rx_pkt_init(&core->rx_pkt); 3389 3390 e1000x_core_prepare_eeprom(core->eeprom, 3391 eeprom_templ, 3392 eeprom_size, 3393 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3394 macaddr); 3395 e1000e_update_rx_offloads(core); 3396 } 3397 3398 void 3399 e1000e_core_pci_uninit(E1000ECore *core) 3400 { 3401 int i; 3402 3403 timer_free(core->autoneg_timer); 3404 3405 e1000e_intrmgr_pci_unint(core); 3406 3407 qemu_del_vm_change_state_handler(core->vmstate); 3408 3409 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3410 net_tx_pkt_reset(core->tx[i].tx_pkt); 3411 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3412 } 3413 3414 net_rx_pkt_uninit(core->rx_pkt); 3415 } 3416 3417 static const uint16_t 3418 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3419 [0] = { 3420 [MII_BMCR] = MII_BMCR_SPEED1000 | 3421 MII_BMCR_FD | 3422 MII_BMCR_AUTOEN, 3423 3424 [MII_BMSR] = MII_BMSR_EXTCAP | 3425 MII_BMSR_LINK_ST | 3426 MII_BMSR_AUTONEG | 3427 MII_BMSR_MFPS | 3428 MII_BMSR_EXTSTAT | 3429 MII_BMSR_10T_HD | 3430 MII_BMSR_10T_FD | 3431 MII_BMSR_100TX_HD | 3432 MII_BMSR_100TX_FD, 3433 3434 [MII_PHYID1] = 0x141, 3435 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3436 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3437 MII_ANAR_10FD | MII_ANAR_TX | 3438 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3439 MII_ANAR_PAUSE_ASYM, 3440 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3441 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3442 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3443 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3444 [MII_ANNP] = 1 | MII_ANNP_MP, 3445 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3446 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3447 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3448 MII_STAT1000_ROK | MII_STAT1000_LOK, 3449 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3450 3451 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3452 BIT(12) | BIT(13), 3453 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3454 }, 3455 [2] = { 3456 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3457 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3458 }, 3459 [3] = { 3460 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3461 } 3462 }; 3463 3464 static const uint32_t e1000e_mac_reg_init[] = { 3465 [PBA] = 0x00140014, 3466 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3467 [EXTCNF_CTRL] = BIT(3), 3468 [EEMNGCTL] = BIT(31), 3469 [FLASHT] = 0x2, 3470 [FLSWCTL] = BIT(30) | BIT(31), 3471 [FLOL] = BIT(0), 3472 [RXDCTL] = BIT(16), 3473 [RXDCTL1] = BIT(16), 3474 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3475 [RXCFGL] = 0x88F7, 3476 [RXUDP] = 0x319, 3477 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3478 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3479 E1000_CTRL_ADVD3WUC, 3480 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3481 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3482 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3483 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3484 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3485 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3486 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3487 [EERD] = E1000_EERW_DONE, 3488 [EEWR] = E1000_EERW_DONE, 3489 [GCR] = E1000_L0S_ADJUST | 3490 E1000_L1_ENTRY_LATENCY_MSB | 3491 E1000_L1_ENTRY_LATENCY_LSB, 3492 [TDFH] = 0x600, 3493 [TDFT] = 0x600, 3494 [TDFHS] = 0x600, 3495 [TDFTS] = 0x600, 3496 [POEMB] = 0x30D, 3497 [PBS] = 0x028, 3498 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3499 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3500 [SWSM] = 1, 3501 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3502 [ITR] = E1000E_MIN_XITR, 3503 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3504 }; 3505 3506 static void e1000e_reset(E1000ECore *core, bool sw) 3507 { 3508 int i; 3509 3510 timer_del(core->autoneg_timer); 3511 3512 e1000e_intrmgr_reset(core); 3513 3514 memset(core->phy, 0, sizeof core->phy); 3515 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3516 3517 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3518 if (sw && (i == PBA || i == PBS || i == FLA)) { 3519 continue; 3520 } 3521 3522 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3523 e1000e_mac_reg_init[i] : 0; 3524 } 3525 3526 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3527 3528 if (qemu_get_queue(core->owner_nic)->link_down) { 3529 e1000e_link_down(core); 3530 } 3531 3532 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3533 3534 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3535 net_tx_pkt_reset(core->tx[i].tx_pkt); 3536 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3537 core->tx[i].skip_cp = false; 3538 } 3539 } 3540 3541 void 3542 e1000e_core_reset(E1000ECore *core) 3543 { 3544 e1000e_reset(core, false); 3545 } 3546 3547 void e1000e_core_pre_save(E1000ECore *core) 3548 { 3549 int i; 3550 NetClientState *nc = qemu_get_queue(core->owner_nic); 3551 3552 /* 3553 * If link is down and auto-negotiation is supported and ongoing, 3554 * complete auto-negotiation immediately. This allows us to look 3555 * at MII_BMSR_AN_COMP to infer link status on load. 3556 */ 3557 if (nc->link_down && e1000e_have_autoneg(core)) { 3558 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3559 e1000e_update_flowctl_status(core); 3560 } 3561 3562 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3563 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3564 core->tx[i].skip_cp = true; 3565 } 3566 } 3567 } 3568 3569 int 3570 e1000e_core_post_load(E1000ECore *core) 3571 { 3572 NetClientState *nc = qemu_get_queue(core->owner_nic); 3573 3574 /* 3575 * nc.link_down can't be migrated, so infer link_down according 3576 * to link status bit in core.mac[STATUS]. 3577 */ 3578 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3579 3580 return 0; 3581 } 3582