1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "sysemu/sysemu.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/pci/msi.h" 41 #include "hw/pci/msix.h" 42 43 #include "net_tx_pkt.h" 44 #include "net_rx_pkt.h" 45 46 #include "e1000x_common.h" 47 #include "e1000e_core.h" 48 49 #include "trace.h" 50 51 #define E1000E_MIN_XITR (500) /* No more then 7813 interrupts per 52 second according to spec 10.2.4.2 */ 53 #define E1000E_MAX_TX_FRAGS (64) 54 55 static inline void 56 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 57 58 static inline void 59 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 60 { 61 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 62 trace_e1000e_wrn_no_ts_support(); 63 } 64 } 65 66 static inline void 67 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 68 { 69 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 70 trace_e1000e_wrn_no_snap_support(); 71 } 72 } 73 74 static inline void 75 e1000e_raise_legacy_irq(E1000ECore *core) 76 { 77 trace_e1000e_irq_legacy_notify(true); 78 e1000x_inc_reg_if_not_full(core->mac, IAC); 79 pci_set_irq(core->owner, 1); 80 } 81 82 static inline void 83 e1000e_lower_legacy_irq(E1000ECore *core) 84 { 85 trace_e1000e_irq_legacy_notify(false); 86 pci_set_irq(core->owner, 0); 87 } 88 89 static inline void 90 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 91 { 92 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 93 timer->delay_resolution_ns; 94 95 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 96 97 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 98 99 timer->running = true; 100 } 101 102 static void 103 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 104 { 105 if (timer->running) { 106 e1000e_intrmgr_rearm_timer(timer); 107 } 108 } 109 110 static void 111 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 112 { 113 if (timer->running) { 114 timer_del(timer->timer); 115 } 116 } 117 118 static inline void 119 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 timer_del(timer->timer); 123 timer->running = false; 124 } 125 } 126 127 static inline void 128 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 129 { 130 trace_e1000e_irq_fire_delayed_interrupts(); 131 e1000e_set_interrupt_cause(core, 0); 132 } 133 134 static void 135 e1000e_intrmgr_on_timer(void *opaque) 136 { 137 E1000IntrDelayTimer *timer = opaque; 138 139 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 140 141 timer->running = false; 142 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 143 } 144 145 static void 146 e1000e_intrmgr_on_throttling_timer(void *opaque) 147 { 148 E1000IntrDelayTimer *timer = opaque; 149 150 assert(!msix_enabled(timer->core->owner)); 151 152 timer->running = false; 153 154 if (!timer->core->itr_intr_pending) { 155 trace_e1000e_irq_throttling_no_pending_interrupts(); 156 return; 157 } 158 159 if (msi_enabled(timer->core->owner)) { 160 trace_e1000e_irq_msi_notify_postponed(); 161 e1000e_set_interrupt_cause(timer->core, 0); 162 } else { 163 trace_e1000e_irq_legacy_notify_postponed(); 164 e1000e_set_interrupt_cause(timer->core, 0); 165 } 166 } 167 168 static void 169 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 170 { 171 E1000IntrDelayTimer *timer = opaque; 172 int idx = timer - &timer->core->eitr[0]; 173 174 assert(msix_enabled(timer->core->owner)); 175 176 timer->running = false; 177 178 if (!timer->core->eitr_intr_pending[idx]) { 179 trace_e1000e_irq_throttling_no_pending_vec(idx); 180 return; 181 } 182 183 trace_e1000e_irq_msix_notify_postponed_vec(idx); 184 msix_notify(timer->core->owner, idx); 185 } 186 187 static void 188 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 189 { 190 int i; 191 192 core->radv.delay_reg = RADV; 193 core->rdtr.delay_reg = RDTR; 194 core->raid.delay_reg = RAID; 195 core->tadv.delay_reg = TADV; 196 core->tidv.delay_reg = TIDV; 197 198 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 199 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 200 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 201 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 202 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 204 core->radv.core = core; 205 core->rdtr.core = core; 206 core->raid.core = core; 207 core->tadv.core = core; 208 core->tidv.core = core; 209 210 core->itr.core = core; 211 core->itr.delay_reg = ITR; 212 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 213 214 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 215 core->eitr[i].core = core; 216 core->eitr[i].delay_reg = EITR + i; 217 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 218 } 219 220 if (!create) { 221 return; 222 } 223 224 core->radv.timer = 225 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 226 core->rdtr.timer = 227 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 228 core->raid.timer = 229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 230 231 core->tadv.timer = 232 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 233 core->tidv.timer = 234 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 235 236 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 237 e1000e_intrmgr_on_throttling_timer, 238 &core->itr); 239 240 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 241 core->eitr[i].timer = 242 timer_new_ns(QEMU_CLOCK_VIRTUAL, 243 e1000e_intrmgr_on_msix_throttling_timer, 244 &core->eitr[i]); 245 } 246 } 247 248 static inline void 249 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 250 { 251 e1000e_intrmgr_stop_timer(&core->radv); 252 e1000e_intrmgr_stop_timer(&core->rdtr); 253 e1000e_intrmgr_stop_timer(&core->raid); 254 e1000e_intrmgr_stop_timer(&core->tidv); 255 e1000e_intrmgr_stop_timer(&core->tadv); 256 } 257 258 static bool 259 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 260 { 261 uint32_t delayable_causes; 262 uint32_t rdtr = core->mac[RDTR]; 263 uint32_t radv = core->mac[RADV]; 264 uint32_t raid = core->mac[RAID]; 265 266 if (msix_enabled(core->owner)) { 267 return false; 268 } 269 270 delayable_causes = E1000_ICR_RXQ0 | 271 E1000_ICR_RXQ1 | 272 E1000_ICR_RXT0; 273 274 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 275 delayable_causes |= E1000_ICR_ACK; 276 } 277 278 /* Clean up all causes that may be delayed */ 279 core->delayed_causes |= *causes & delayable_causes; 280 *causes &= ~delayable_causes; 281 282 /* Check if delayed RX interrupts disabled by client 283 or if there are causes that cannot be delayed */ 284 if ((rdtr == 0) || (*causes != 0)) { 285 return false; 286 } 287 288 /* Check if delayed RX ACK interrupts disabled by client 289 and there is an ACK packet received */ 290 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 291 return false; 292 } 293 294 /* All causes delayed */ 295 e1000e_intrmgr_rearm_timer(&core->rdtr); 296 297 if (!core->radv.running && (radv != 0)) { 298 e1000e_intrmgr_rearm_timer(&core->radv); 299 } 300 301 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 302 e1000e_intrmgr_rearm_timer(&core->raid); 303 } 304 305 return true; 306 } 307 308 static bool 309 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 310 { 311 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 312 E1000_ICR_TXQ1 | 313 E1000_ICR_TXQE | 314 E1000_ICR_TXDW; 315 316 if (msix_enabled(core->owner)) { 317 return false; 318 } 319 320 /* Clean up all causes that may be delayed */ 321 core->delayed_causes |= *causes & delayable_causes; 322 *causes &= ~delayable_causes; 323 324 /* If there are causes that cannot be delayed */ 325 if (*causes != 0) { 326 return false; 327 } 328 329 /* All causes delayed */ 330 e1000e_intrmgr_rearm_timer(&core->tidv); 331 332 if (!core->tadv.running && (core->mac[TADV] != 0)) { 333 e1000e_intrmgr_rearm_timer(&core->tadv); 334 } 335 336 return true; 337 } 338 339 static uint32_t 340 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 341 { 342 uint32_t res; 343 344 if (msix_enabled(core->owner)) { 345 assert(core->delayed_causes == 0); 346 return 0; 347 } 348 349 res = core->delayed_causes; 350 core->delayed_causes = 0; 351 352 e1000e_intrmgr_stop_delay_timers(core); 353 354 return res; 355 } 356 357 static void 358 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 359 { 360 int i; 361 uint32_t val = e1000e_intmgr_collect_delayed_causes(core); 362 363 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]); 364 core->mac[ICR] |= val; 365 366 if (core->itr.running) { 367 timer_del(core->itr.timer); 368 e1000e_intrmgr_on_throttling_timer(&core->itr); 369 } 370 371 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 372 if (core->eitr[i].running) { 373 timer_del(core->eitr[i].timer); 374 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 375 } 376 } 377 } 378 379 static void 380 e1000e_intrmgr_resume(E1000ECore *core) 381 { 382 int i; 383 384 e1000e_intmgr_timer_resume(&core->radv); 385 e1000e_intmgr_timer_resume(&core->rdtr); 386 e1000e_intmgr_timer_resume(&core->raid); 387 e1000e_intmgr_timer_resume(&core->tidv); 388 e1000e_intmgr_timer_resume(&core->tadv); 389 390 e1000e_intmgr_timer_resume(&core->itr); 391 392 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 393 e1000e_intmgr_timer_resume(&core->eitr[i]); 394 } 395 } 396 397 static void 398 e1000e_intrmgr_pause(E1000ECore *core) 399 { 400 int i; 401 402 e1000e_intmgr_timer_pause(&core->radv); 403 e1000e_intmgr_timer_pause(&core->rdtr); 404 e1000e_intmgr_timer_pause(&core->raid); 405 e1000e_intmgr_timer_pause(&core->tidv); 406 e1000e_intmgr_timer_pause(&core->tadv); 407 408 e1000e_intmgr_timer_pause(&core->itr); 409 410 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 411 e1000e_intmgr_timer_pause(&core->eitr[i]); 412 } 413 } 414 415 static void 416 e1000e_intrmgr_reset(E1000ECore *core) 417 { 418 int i; 419 420 core->delayed_causes = 0; 421 422 e1000e_intrmgr_stop_delay_timers(core); 423 424 e1000e_intrmgr_stop_timer(&core->itr); 425 426 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 427 e1000e_intrmgr_stop_timer(&core->eitr[i]); 428 } 429 } 430 431 static void 432 e1000e_intrmgr_pci_unint(E1000ECore *core) 433 { 434 int i; 435 436 timer_del(core->radv.timer); 437 timer_free(core->radv.timer); 438 timer_del(core->rdtr.timer); 439 timer_free(core->rdtr.timer); 440 timer_del(core->raid.timer); 441 timer_free(core->raid.timer); 442 443 timer_del(core->tadv.timer); 444 timer_free(core->tadv.timer); 445 timer_del(core->tidv.timer); 446 timer_free(core->tidv.timer); 447 448 timer_del(core->itr.timer); 449 timer_free(core->itr.timer); 450 451 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 452 timer_del(core->eitr[i].timer); 453 timer_free(core->eitr[i].timer); 454 } 455 } 456 457 static void 458 e1000e_intrmgr_pci_realize(E1000ECore *core) 459 { 460 e1000e_intrmgr_initialize_all_timers(core, true); 461 } 462 463 static inline bool 464 e1000e_rx_csum_enabled(E1000ECore *core) 465 { 466 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 467 } 468 469 static inline bool 470 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 471 { 472 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 473 } 474 475 static inline bool 476 e1000e_rx_use_ps_descriptor(E1000ECore *core) 477 { 478 return !e1000e_rx_use_legacy_descriptor(core) && 479 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 480 } 481 482 static inline bool 483 e1000e_rss_enabled(E1000ECore *core) 484 { 485 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 486 !e1000e_rx_csum_enabled(core) && 487 !e1000e_rx_use_legacy_descriptor(core); 488 } 489 490 typedef struct E1000E_RSSInfo_st { 491 bool enabled; 492 uint32_t hash; 493 uint32_t queue; 494 uint32_t type; 495 } E1000E_RSSInfo; 496 497 static uint32_t 498 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 499 { 500 bool isip4, isip6, isudp, istcp; 501 502 assert(e1000e_rss_enabled(core)); 503 504 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 505 506 if (isip4) { 507 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 508 509 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC], 510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 511 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 512 513 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 514 return E1000_MRQ_RSS_TYPE_IPV4TCP; 515 } 516 517 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 518 return E1000_MRQ_RSS_TYPE_IPV4; 519 } 520 } else if (isip6) { 521 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 522 523 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 524 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 525 526 /* 527 * Following two traces must not be combined because resulting 528 * event will have 11 arguments totally and some trace backends 529 * (at least "ust") have limitation of maximum 10 arguments per 530 * event. Events with more arguments fail to compile for 531 * backends like these. 532 */ 533 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 534 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, istcp, 535 ip6info->has_ext_hdrs, 536 ip6info->rss_ex_dst_valid, 537 ip6info->rss_ex_src_valid, 538 core->mac[MRQC], 539 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 540 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 541 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 542 543 if ((!ex_dis || !ip6info->has_ext_hdrs) && 544 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 545 ip6info->rss_ex_src_valid))) { 546 547 if (istcp && !ip6info->fragment && 548 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 549 return E1000_MRQ_RSS_TYPE_IPV6TCP; 550 } 551 552 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 553 return E1000_MRQ_RSS_TYPE_IPV6EX; 554 } 555 556 } 557 558 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 559 return E1000_MRQ_RSS_TYPE_IPV6; 560 } 561 562 } 563 564 return E1000_MRQ_RSS_TYPE_NONE; 565 } 566 567 static uint32_t 568 e1000e_rss_calc_hash(E1000ECore *core, 569 struct NetRxPkt *pkt, 570 E1000E_RSSInfo *info) 571 { 572 NetRxPktRssType type; 573 574 assert(e1000e_rss_enabled(core)); 575 576 switch (info->type) { 577 case E1000_MRQ_RSS_TYPE_IPV4: 578 type = NetPktRssIpV4; 579 break; 580 case E1000_MRQ_RSS_TYPE_IPV4TCP: 581 type = NetPktRssIpV4Tcp; 582 break; 583 case E1000_MRQ_RSS_TYPE_IPV6TCP: 584 type = NetPktRssIpV6Tcp; 585 break; 586 case E1000_MRQ_RSS_TYPE_IPV6: 587 type = NetPktRssIpV6; 588 break; 589 case E1000_MRQ_RSS_TYPE_IPV6EX: 590 type = NetPktRssIpV6Ex; 591 break; 592 default: 593 assert(false); 594 return 0; 595 } 596 597 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 598 } 599 600 static void 601 e1000e_rss_parse_packet(E1000ECore *core, 602 struct NetRxPkt *pkt, 603 E1000E_RSSInfo *info) 604 { 605 trace_e1000e_rx_rss_started(); 606 607 if (!e1000e_rss_enabled(core)) { 608 info->enabled = false; 609 info->hash = 0; 610 info->queue = 0; 611 info->type = 0; 612 trace_e1000e_rx_rss_disabled(); 613 return; 614 } 615 616 info->enabled = true; 617 618 info->type = e1000e_rss_get_hash_type(core, pkt); 619 620 trace_e1000e_rx_rss_type(info->type); 621 622 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 623 info->hash = 0; 624 info->queue = 0; 625 return; 626 } 627 628 info->hash = e1000e_rss_calc_hash(core, pkt, info); 629 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 630 } 631 632 static void 633 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 634 { 635 if (tx->props.tse && tx->props.cptse) { 636 net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss); 637 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 638 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 639 return; 640 } 641 642 if (tx->props.sum_needed & E1000_TXD_POPTS_TXSM) { 643 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0); 644 } 645 646 if (tx->props.sum_needed & E1000_TXD_POPTS_IXSM) { 647 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 648 } 649 } 650 651 static bool 652 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 653 { 654 int target_queue = MIN(core->max_queue_num, queue_index); 655 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 656 657 e1000e_setup_tx_offloads(core, tx); 658 659 net_tx_pkt_dump(tx->tx_pkt); 660 661 if ((core->phy[0][PHY_CTRL] & MII_CR_LOOPBACK) || 662 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 663 return net_tx_pkt_send_loopback(tx->tx_pkt, queue); 664 } else { 665 return net_tx_pkt_send(tx->tx_pkt, queue); 666 } 667 } 668 669 static void 670 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 671 { 672 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 673 PTC1023, PTC1522 }; 674 675 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt); 676 677 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 678 e1000x_inc_reg_if_not_full(core->mac, TPT); 679 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 680 681 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 682 case ETH_PKT_BCAST: 683 e1000x_inc_reg_if_not_full(core->mac, BPTC); 684 break; 685 case ETH_PKT_MCAST: 686 e1000x_inc_reg_if_not_full(core->mac, MPTC); 687 break; 688 case ETH_PKT_UCAST: 689 break; 690 default: 691 g_assert_not_reached(); 692 } 693 694 core->mac[GPTC] = core->mac[TPT]; 695 core->mac[GOTCL] = core->mac[TOTL]; 696 core->mac[GOTCH] = core->mac[TOTH]; 697 } 698 699 static void 700 e1000e_process_tx_desc(E1000ECore *core, 701 struct e1000e_tx *tx, 702 struct e1000_tx_desc *dp, 703 int queue_index) 704 { 705 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 706 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 707 unsigned int split_size = txd_lower & 0xffff; 708 uint64_t addr; 709 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 710 bool eop = txd_lower & E1000_TXD_CMD_EOP; 711 712 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 713 e1000x_read_tx_ctx_descr(xp, &tx->props); 714 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 715 return; 716 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 717 /* data descriptor */ 718 tx->props.sum_needed = le32_to_cpu(dp->upper.data) >> 8; 719 tx->props.cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 720 e1000e_process_ts_option(core, dp); 721 } else { 722 /* legacy descriptor */ 723 e1000e_process_ts_option(core, dp); 724 tx->props.cptse = 0; 725 } 726 727 addr = le64_to_cpu(dp->buffer_addr); 728 729 if (!tx->skip_cp) { 730 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) { 731 tx->skip_cp = true; 732 } 733 } 734 735 if (eop) { 736 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 737 if (e1000x_vlan_enabled(core->mac) && 738 e1000x_is_vlan_txd(txd_lower)) { 739 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 740 le16_to_cpu(dp->upper.fields.special), core->vet); 741 } 742 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 743 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 744 } 745 } 746 747 tx->skip_cp = false; 748 net_tx_pkt_reset(tx->tx_pkt); 749 750 tx->props.sum_needed = 0; 751 tx->props.cptse = 0; 752 } 753 } 754 755 static inline uint32_t 756 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 757 { 758 if (!msix_enabled(core->owner)) { 759 return E1000_ICR_TXDW; 760 } 761 762 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 763 } 764 765 static inline uint32_t 766 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 767 bool min_threshold_hit) 768 { 769 if (!msix_enabled(core->owner)) { 770 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 771 } 772 773 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 774 } 775 776 static uint32_t 777 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 778 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 779 { 780 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 781 782 if (!(txd_lower & E1000_TXD_CMD_RS) && 783 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 784 return 0; 785 } 786 787 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 788 789 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 790 791 dp->upper.data = cpu_to_le32(txd_upper); 792 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 793 &dp->upper, sizeof(dp->upper)); 794 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 795 } 796 797 typedef struct E1000E_RingInfo_st { 798 int dbah; 799 int dbal; 800 int dlen; 801 int dh; 802 int dt; 803 int idx; 804 } E1000E_RingInfo; 805 806 static inline bool 807 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 808 { 809 return core->mac[r->dh] == core->mac[r->dt]; 810 } 811 812 static inline uint64_t 813 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 814 { 815 uint64_t bah = core->mac[r->dbah]; 816 uint64_t bal = core->mac[r->dbal]; 817 818 return (bah << 32) + bal; 819 } 820 821 static inline uint64_t 822 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 823 { 824 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 825 } 826 827 static inline void 828 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 829 { 830 core->mac[r->dh] += count; 831 832 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 833 core->mac[r->dh] = 0; 834 } 835 } 836 837 static inline uint32_t 838 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 839 { 840 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 841 core->mac[r->dh], core->mac[r->dt]); 842 843 if (core->mac[r->dh] <= core->mac[r->dt]) { 844 return core->mac[r->dt] - core->mac[r->dh]; 845 } 846 847 if (core->mac[r->dh] > core->mac[r->dt]) { 848 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 849 core->mac[r->dt] - core->mac[r->dh]; 850 } 851 852 g_assert_not_reached(); 853 return 0; 854 } 855 856 static inline bool 857 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 858 { 859 return core->mac[r->dlen] > 0; 860 } 861 862 static inline uint32_t 863 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 864 { 865 return core->mac[r->dlen]; 866 } 867 868 typedef struct E1000E_TxRing_st { 869 const E1000E_RingInfo *i; 870 struct e1000e_tx *tx; 871 } E1000E_TxRing; 872 873 static inline int 874 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 875 { 876 return (reg_idx - base_reg_idx) / (0x100 >> 2); 877 } 878 879 static inline void 880 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 881 { 882 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 883 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 884 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 885 }; 886 887 assert(idx < ARRAY_SIZE(i)); 888 889 txr->i = &i[idx]; 890 txr->tx = &core->tx[idx]; 891 } 892 893 typedef struct E1000E_RxRing_st { 894 const E1000E_RingInfo *i; 895 } E1000E_RxRing; 896 897 static inline void 898 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 899 { 900 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 901 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 902 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 903 }; 904 905 assert(idx < ARRAY_SIZE(i)); 906 907 rxr->i = &i[idx]; 908 } 909 910 static void 911 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 912 { 913 dma_addr_t base; 914 struct e1000_tx_desc desc; 915 bool ide = false; 916 const E1000E_RingInfo *txi = txr->i; 917 uint32_t cause = E1000_ICS_TXQE; 918 919 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 920 trace_e1000e_tx_disabled(); 921 return; 922 } 923 924 while (!e1000e_ring_empty(core, txi)) { 925 base = e1000e_ring_head_descr(core, txi); 926 927 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 928 929 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 930 desc.lower.data, desc.upper.data); 931 932 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 933 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 934 935 e1000e_ring_advance(core, txi, 1); 936 } 937 938 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 939 e1000e_set_interrupt_cause(core, cause); 940 } 941 } 942 943 static bool 944 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 945 size_t total_size) 946 { 947 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 948 949 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 950 core->rx_desc_buf_size); 951 952 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 953 core->rx_desc_buf_size; 954 } 955 956 void 957 e1000e_start_recv(E1000ECore *core) 958 { 959 int i; 960 961 trace_e1000e_rx_start_recv(); 962 963 for (i = 0; i <= core->max_queue_num; i++) { 964 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 965 } 966 } 967 968 int 969 e1000e_can_receive(E1000ECore *core) 970 { 971 int i; 972 973 if (!e1000x_rx_ready(core->owner, core->mac)) { 974 return false; 975 } 976 977 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 978 E1000E_RxRing rxr; 979 980 e1000e_rx_ring_init(core, &rxr, i); 981 if (e1000e_ring_enabled(core, rxr.i) && 982 e1000e_has_rxbufs(core, rxr.i, 1)) { 983 trace_e1000e_rx_can_recv(); 984 return true; 985 } 986 } 987 988 trace_e1000e_rx_can_recv_rings_full(); 989 return false; 990 } 991 992 ssize_t 993 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 994 { 995 const struct iovec iov = { 996 .iov_base = (uint8_t *)buf, 997 .iov_len = size 998 }; 999 1000 return e1000e_receive_iov(core, &iov, 1); 1001 } 1002 1003 static inline bool 1004 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1005 { 1006 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1007 } 1008 1009 static inline bool 1010 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1011 { 1012 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1013 } 1014 1015 static bool 1016 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size) 1017 { 1018 uint32_t rctl = core->mac[RCTL]; 1019 1020 if (e1000x_is_vlan_packet(buf, core->vet) && 1021 e1000x_vlan_rx_filter_enabled(core->mac)) { 1022 uint16_t vid = lduw_be_p(buf + 14); 1023 uint32_t vfta = ldl_le_p((uint32_t *)(core->mac + VFTA) + 1024 ((vid >> 5) & 0x7f)); 1025 if ((vfta & (1 << (vid & 0x1f))) == 0) { 1026 trace_e1000e_rx_flt_vlan_mismatch(vid); 1027 return false; 1028 } else { 1029 trace_e1000e_rx_flt_vlan_match(vid); 1030 } 1031 } 1032 1033 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1034 case ETH_PKT_UCAST: 1035 if (rctl & E1000_RCTL_UPE) { 1036 return true; /* promiscuous ucast */ 1037 } 1038 break; 1039 1040 case ETH_PKT_BCAST: 1041 if (rctl & E1000_RCTL_BAM) { 1042 return true; /* broadcast enabled */ 1043 } 1044 break; 1045 1046 case ETH_PKT_MCAST: 1047 if (rctl & E1000_RCTL_MPE) { 1048 return true; /* promiscuous mcast */ 1049 } 1050 break; 1051 1052 default: 1053 g_assert_not_reached(); 1054 } 1055 1056 return e1000x_rx_group_filter(core->mac, buf); 1057 } 1058 1059 static inline void 1060 e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr) 1061 { 1062 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc; 1063 *buff_addr = le64_to_cpu(d->buffer_addr); 1064 } 1065 1066 static inline void 1067 e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr) 1068 { 1069 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc; 1070 *buff_addr = le64_to_cpu(d->read.buffer_addr); 1071 } 1072 1073 static inline void 1074 e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc, 1075 hwaddr (*buff_addr)[MAX_PS_BUFFERS]) 1076 { 1077 int i; 1078 union e1000_rx_desc_packet_split *d = 1079 (union e1000_rx_desc_packet_split *) desc; 1080 1081 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1082 (*buff_addr)[i] = le64_to_cpu(d->read.buffer_addr[i]); 1083 } 1084 1085 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1], 1086 (*buff_addr)[2], (*buff_addr)[3]); 1087 } 1088 1089 static inline void 1090 e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc, 1091 hwaddr (*buff_addr)[MAX_PS_BUFFERS]) 1092 { 1093 if (e1000e_rx_use_legacy_descriptor(core)) { 1094 e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]); 1095 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0; 1096 } else { 1097 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1098 e1000e_read_ps_rx_descr(core, desc, buff_addr); 1099 } else { 1100 e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]); 1101 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0; 1102 } 1103 } 1104 } 1105 1106 static void 1107 e1000e_verify_csum_in_sw(E1000ECore *core, 1108 struct NetRxPkt *pkt, 1109 uint32_t *status_flags, 1110 bool istcp, bool isudp) 1111 { 1112 bool csum_valid; 1113 uint32_t csum_error; 1114 1115 if (e1000e_rx_l3_cso_enabled(core)) { 1116 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1117 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1118 } else { 1119 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1120 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1121 } 1122 } else { 1123 trace_e1000e_rx_metadata_l3_cso_disabled(); 1124 } 1125 1126 if (!e1000e_rx_l4_cso_enabled(core)) { 1127 trace_e1000e_rx_metadata_l4_cso_disabled(); 1128 return; 1129 } 1130 1131 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1132 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1133 return; 1134 } 1135 1136 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1137 1138 if (istcp) { 1139 *status_flags |= E1000_RXD_STAT_TCPCS | 1140 csum_error; 1141 } else if (isudp) { 1142 *status_flags |= E1000_RXD_STAT_TCPCS | 1143 E1000_RXD_STAT_UDPCS | 1144 csum_error; 1145 } 1146 } 1147 1148 static inline bool 1149 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1150 { 1151 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1152 return false; 1153 } 1154 1155 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1156 return !net_rx_pkt_has_tcp_data(rx_pkt); 1157 } 1158 1159 return true; 1160 } 1161 1162 static void 1163 e1000e_build_rx_metadata(E1000ECore *core, 1164 struct NetRxPkt *pkt, 1165 bool is_eop, 1166 const E1000E_RSSInfo *rss_info, 1167 uint32_t *rss, uint32_t *mrq, 1168 uint32_t *status_flags, 1169 uint16_t *ip_id, 1170 uint16_t *vlan_tag) 1171 { 1172 struct virtio_net_hdr *vhdr; 1173 bool isip4, isip6, istcp, isudp; 1174 uint32_t pkt_type; 1175 1176 *status_flags = E1000_RXD_STAT_DD; 1177 1178 /* No additional metadata needed for non-EOP descriptors */ 1179 if (!is_eop) { 1180 goto func_exit; 1181 } 1182 1183 *status_flags |= E1000_RXD_STAT_EOP; 1184 1185 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1186 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp); 1187 1188 /* VLAN state */ 1189 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1190 *status_flags |= E1000_RXD_STAT_VP; 1191 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1192 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1193 } 1194 1195 /* Packet parsing results */ 1196 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1197 if (rss_info->enabled) { 1198 *rss = cpu_to_le32(rss_info->hash); 1199 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1200 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1201 } 1202 } else if (isip4) { 1203 *status_flags |= E1000_RXD_STAT_IPIDV; 1204 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1205 trace_e1000e_rx_metadata_ip_id(*ip_id); 1206 } 1207 1208 if (istcp && e1000e_is_tcp_ack(core, pkt)) { 1209 *status_flags |= E1000_RXD_STAT_ACK; 1210 trace_e1000e_rx_metadata_ack(); 1211 } 1212 1213 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1214 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1215 pkt_type = E1000_RXD_PKT_MAC; 1216 } else if (istcp || isudp) { 1217 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1218 } else if (isip4 || isip6) { 1219 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1220 } else { 1221 pkt_type = E1000_RXD_PKT_MAC; 1222 } 1223 1224 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1225 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1226 1227 /* RX CSO information */ 1228 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1229 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1230 goto func_exit; 1231 } 1232 1233 if (!net_rx_pkt_has_virt_hdr(pkt)) { 1234 trace_e1000e_rx_metadata_no_virthdr(); 1235 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp); 1236 goto func_exit; 1237 } 1238 1239 vhdr = net_rx_pkt_get_vhdr(pkt); 1240 1241 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1242 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1243 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1244 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp); 1245 goto func_exit; 1246 } 1247 1248 if (e1000e_rx_l3_cso_enabled(core)) { 1249 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0; 1250 } else { 1251 trace_e1000e_rx_metadata_l3_cso_disabled(); 1252 } 1253 1254 if (e1000e_rx_l4_cso_enabled(core)) { 1255 if (istcp) { 1256 *status_flags |= E1000_RXD_STAT_TCPCS; 1257 } else if (isudp) { 1258 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1259 } 1260 } else { 1261 trace_e1000e_rx_metadata_l4_cso_disabled(); 1262 } 1263 1264 trace_e1000e_rx_metadata_status_flags(*status_flags); 1265 1266 func_exit: 1267 *status_flags = cpu_to_le32(*status_flags); 1268 } 1269 1270 static inline void 1271 e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, 1272 struct NetRxPkt *pkt, 1273 const E1000E_RSSInfo *rss_info, 1274 uint16_t length) 1275 { 1276 uint32_t status_flags, rss, mrq; 1277 uint16_t ip_id; 1278 1279 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc; 1280 1281 assert(!rss_info->enabled); 1282 1283 d->length = cpu_to_le16(length); 1284 d->csum = 0; 1285 1286 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1287 rss_info, 1288 &rss, &mrq, 1289 &status_flags, &ip_id, 1290 &d->special); 1291 d->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1292 d->status = (uint8_t) le32_to_cpu(status_flags); 1293 d->special = 0; 1294 } 1295 1296 static inline void 1297 e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc, 1298 struct NetRxPkt *pkt, 1299 const E1000E_RSSInfo *rss_info, 1300 uint16_t length) 1301 { 1302 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc; 1303 1304 memset(&d->wb, 0, sizeof(d->wb)); 1305 1306 d->wb.upper.length = cpu_to_le16(length); 1307 1308 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1309 rss_info, 1310 &d->wb.lower.hi_dword.rss, 1311 &d->wb.lower.mrq, 1312 &d->wb.upper.status_error, 1313 &d->wb.lower.hi_dword.csum_ip.ip_id, 1314 &d->wb.upper.vlan); 1315 } 1316 1317 static inline void 1318 e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc, 1319 struct NetRxPkt *pkt, 1320 const E1000E_RSSInfo *rss_info, 1321 size_t ps_hdr_len, 1322 uint16_t(*written)[MAX_PS_BUFFERS]) 1323 { 1324 int i; 1325 union e1000_rx_desc_packet_split *d = 1326 (union e1000_rx_desc_packet_split *) desc; 1327 1328 memset(&d->wb, 0, sizeof(d->wb)); 1329 1330 d->wb.middle.length0 = cpu_to_le16((*written)[0]); 1331 1332 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1333 d->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1334 } 1335 1336 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1337 rss_info, 1338 &d->wb.lower.hi_dword.rss, 1339 &d->wb.lower.mrq, 1340 &d->wb.middle.status_error, 1341 &d->wb.lower.hi_dword.csum_ip.ip_id, 1342 &d->wb.middle.vlan); 1343 1344 d->wb.upper.header_status = 1345 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1346 1347 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1348 (*written)[2], (*written)[3]); 1349 } 1350 1351 static inline void 1352 e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc, 1353 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1354 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1355 { 1356 if (e1000e_rx_use_legacy_descriptor(core)) { 1357 assert(ps_hdr_len == 0); 1358 e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0]); 1359 } else { 1360 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1361 e1000e_write_ps_rx_descr(core, desc, pkt, rss_info, 1362 ps_hdr_len, written); 1363 } else { 1364 assert(ps_hdr_len == 0); 1365 e1000e_write_ext_rx_descr(core, desc, pkt, rss_info, 1366 (*written)[0]); 1367 } 1368 } 1369 } 1370 1371 typedef struct e1000e_ba_state_st { 1372 uint16_t written[MAX_PS_BUFFERS]; 1373 uint8_t cur_idx; 1374 } e1000e_ba_state; 1375 1376 static inline void 1377 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1378 hwaddr (*ba)[MAX_PS_BUFFERS], 1379 e1000e_ba_state *bastate, 1380 const char *data, 1381 dma_addr_t data_len) 1382 { 1383 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1384 1385 pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_len); 1386 bastate->written[0] += data_len; 1387 1388 bastate->cur_idx = 1; 1389 } 1390 1391 static void 1392 e1000e_write_to_rx_buffers(E1000ECore *core, 1393 hwaddr (*ba)[MAX_PS_BUFFERS], 1394 e1000e_ba_state *bastate, 1395 const char *data, 1396 dma_addr_t data_len) 1397 { 1398 while (data_len > 0) { 1399 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1400 uint32_t cur_buf_bytes_left = cur_buf_len - 1401 bastate->written[bastate->cur_idx]; 1402 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1403 1404 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1405 (*ba)[bastate->cur_idx], 1406 bastate->written[bastate->cur_idx], 1407 data, 1408 bytes_to_write); 1409 1410 pci_dma_write(core->owner, 1411 (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1412 data, bytes_to_write); 1413 1414 bastate->written[bastate->cur_idx] += bytes_to_write; 1415 data += bytes_to_write; 1416 data_len -= bytes_to_write; 1417 1418 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1419 bastate->cur_idx++; 1420 } 1421 1422 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1423 } 1424 } 1425 1426 static void 1427 e1000e_update_rx_stats(E1000ECore *core, 1428 size_t data_size, 1429 size_t data_fcs_size) 1430 { 1431 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size); 1432 1433 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1434 case ETH_PKT_BCAST: 1435 e1000x_inc_reg_if_not_full(core->mac, BPRC); 1436 break; 1437 1438 case ETH_PKT_MCAST: 1439 e1000x_inc_reg_if_not_full(core->mac, MPRC); 1440 break; 1441 1442 default: 1443 break; 1444 } 1445 } 1446 1447 static inline bool 1448 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1449 { 1450 return e1000e_ring_free_descr_num(core, rxi) == 1451 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1452 } 1453 1454 static bool 1455 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1456 { 1457 bool isip4, isip6, isudp, istcp; 1458 bool fragment; 1459 1460 if (!e1000e_rx_use_ps_descriptor(core)) { 1461 return false; 1462 } 1463 1464 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1465 1466 if (isip4) { 1467 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1468 } else if (isip6) { 1469 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1470 } else { 1471 return false; 1472 } 1473 1474 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1475 return false; 1476 } 1477 1478 if (!fragment && (isudp || istcp)) { 1479 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1480 } else { 1481 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1482 } 1483 1484 if ((*hdr_len > core->rxbuf_sizes[0]) || 1485 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1486 return false; 1487 } 1488 1489 return true; 1490 } 1491 1492 static void 1493 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1494 const E1000E_RxRing *rxr, 1495 const E1000E_RSSInfo *rss_info) 1496 { 1497 PCIDevice *d = core->owner; 1498 dma_addr_t base; 1499 uint8_t desc[E1000_MAX_RX_DESC_LEN]; 1500 size_t desc_size; 1501 size_t desc_offset = 0; 1502 size_t iov_ofs = 0; 1503 1504 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1505 size_t size = net_rx_pkt_get_total_len(pkt); 1506 size_t total_size = size + e1000x_fcs_len(core->mac); 1507 const E1000E_RingInfo *rxi; 1508 size_t ps_hdr_len = 0; 1509 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1510 1511 rxi = rxr->i; 1512 1513 do { 1514 hwaddr ba[MAX_PS_BUFFERS]; 1515 e1000e_ba_state bastate = { { 0 } }; 1516 bool is_last = false; 1517 bool is_first = true; 1518 1519 desc_size = total_size - desc_offset; 1520 1521 if (desc_size > core->rx_desc_buf_size) { 1522 desc_size = core->rx_desc_buf_size; 1523 } 1524 1525 base = e1000e_ring_head_descr(core, rxi); 1526 1527 pci_dma_read(d, base, &desc, core->rx_desc_len); 1528 1529 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1530 1531 e1000e_read_rx_descr(core, desc, &ba); 1532 1533 if (ba[0]) { 1534 if (desc_offset < size) { 1535 static const uint32_t fcs_pad; 1536 size_t iov_copy; 1537 size_t copy_size = size - desc_offset; 1538 if (copy_size > core->rx_desc_buf_size) { 1539 copy_size = core->rx_desc_buf_size; 1540 } 1541 1542 /* For PS mode copy the packet header first */ 1543 if (do_ps) { 1544 if (is_first) { 1545 size_t ps_hdr_copied = 0; 1546 do { 1547 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1548 iov->iov_len - iov_ofs); 1549 1550 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate, 1551 iov->iov_base, iov_copy); 1552 1553 copy_size -= iov_copy; 1554 ps_hdr_copied += iov_copy; 1555 1556 iov_ofs += iov_copy; 1557 if (iov_ofs == iov->iov_len) { 1558 iov++; 1559 iov_ofs = 0; 1560 } 1561 } while (ps_hdr_copied < ps_hdr_len); 1562 1563 is_first = false; 1564 } else { 1565 /* Leave buffer 0 of each descriptor except first */ 1566 /* empty as per spec 7.1.5.1 */ 1567 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate, 1568 NULL, 0); 1569 } 1570 } 1571 1572 /* Copy packet payload */ 1573 while (copy_size) { 1574 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1575 1576 e1000e_write_to_rx_buffers(core, &ba, &bastate, 1577 iov->iov_base + iov_ofs, iov_copy); 1578 1579 copy_size -= iov_copy; 1580 iov_ofs += iov_copy; 1581 if (iov_ofs == iov->iov_len) { 1582 iov++; 1583 iov_ofs = 0; 1584 } 1585 } 1586 1587 if (desc_offset + desc_size >= total_size) { 1588 /* Simulate FCS checksum presence in the last descriptor */ 1589 e1000e_write_to_rx_buffers(core, &ba, &bastate, 1590 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1591 } 1592 } 1593 desc_offset += desc_size; 1594 if (desc_offset >= total_size) { 1595 is_last = true; 1596 } 1597 } else { /* as per intel docs; skip descriptors with null buf addr */ 1598 trace_e1000e_rx_null_descriptor(); 1599 } 1600 1601 e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL, 1602 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1603 pci_dma_write(d, base, &desc, core->rx_desc_len); 1604 1605 e1000e_ring_advance(core, rxi, 1606 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1607 1608 } while (desc_offset < total_size); 1609 1610 e1000e_update_rx_stats(core, size, total_size); 1611 } 1612 1613 static inline void 1614 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1615 { 1616 if (net_rx_pkt_has_virt_hdr(pkt)) { 1617 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1618 1619 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1620 net_rx_pkt_fix_l4_csum(pkt); 1621 } 1622 } 1623 } 1624 1625 ssize_t 1626 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1627 { 1628 static const int maximum_ethernet_hdr_len = (14 + 4); 1629 /* Min. octets in an ethernet frame sans FCS */ 1630 static const int min_buf_size = 60; 1631 1632 uint32_t n = 0; 1633 uint8_t min_buf[min_buf_size]; 1634 struct iovec min_iov; 1635 uint8_t *filter_buf; 1636 size_t size, orig_size; 1637 size_t iov_ofs = 0; 1638 E1000E_RxRing rxr; 1639 E1000E_RSSInfo rss_info; 1640 size_t total_size; 1641 ssize_t retval; 1642 bool rdmts_hit; 1643 1644 trace_e1000e_rx_receive_iov(iovcnt); 1645 1646 if (!e1000x_hw_rx_enabled(core->mac)) { 1647 return -1; 1648 } 1649 1650 /* Pull virtio header in */ 1651 if (core->has_vnet) { 1652 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1653 iov_ofs = sizeof(struct virtio_net_hdr); 1654 } 1655 1656 filter_buf = iov->iov_base + iov_ofs; 1657 orig_size = iov_size(iov, iovcnt); 1658 size = orig_size - iov_ofs; 1659 1660 /* Pad to minimum Ethernet frame length */ 1661 if (size < sizeof(min_buf)) { 1662 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size); 1663 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1664 e1000x_inc_reg_if_not_full(core->mac, RUC); 1665 min_iov.iov_base = filter_buf = min_buf; 1666 min_iov.iov_len = size = sizeof(min_buf); 1667 iovcnt = 1; 1668 iov = &min_iov; 1669 iov_ofs = 0; 1670 } else if (iov->iov_len < maximum_ethernet_hdr_len) { 1671 /* This is very unlikely, but may happen. */ 1672 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len); 1673 filter_buf = min_buf; 1674 } 1675 1676 /* Discard oversized packets if !LPE and !SBP. */ 1677 if (e1000x_is_oversized(core->mac, size)) { 1678 return orig_size; 1679 } 1680 1681 net_rx_pkt_set_packet_type(core->rx_pkt, 1682 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf))); 1683 1684 if (!e1000e_receive_filter(core, filter_buf, size)) { 1685 trace_e1000e_rx_flt_dropped(); 1686 return orig_size; 1687 } 1688 1689 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1690 e1000x_vlan_enabled(core->mac), core->vet); 1691 1692 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1693 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1694 1695 trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx); 1696 1697 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1698 e1000x_fcs_len(core->mac); 1699 1700 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1701 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1702 1703 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1704 1705 retval = orig_size; 1706 1707 /* Perform small receive detection (RSRPD) */ 1708 if (total_size < core->mac[RSRPD]) { 1709 n |= E1000_ICS_SRPD; 1710 } 1711 1712 /* Perform ACK receive detection */ 1713 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1714 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1715 n |= E1000_ICS_ACK; 1716 } 1717 1718 /* Check if receive descriptor minimum threshold hit */ 1719 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1720 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1721 1722 trace_e1000e_rx_written_to_guest(n); 1723 } else { 1724 n |= E1000_ICS_RXO; 1725 retval = 0; 1726 1727 trace_e1000e_rx_not_written_to_guest(n); 1728 } 1729 1730 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) { 1731 trace_e1000e_rx_interrupt_set(n); 1732 e1000e_set_interrupt_cause(core, n); 1733 } else { 1734 trace_e1000e_rx_interrupt_delayed(n); 1735 } 1736 1737 return retval; 1738 } 1739 1740 static inline bool 1741 e1000e_have_autoneg(E1000ECore *core) 1742 { 1743 return core->phy[0][PHY_CTRL] & MII_CR_AUTO_NEG_EN; 1744 } 1745 1746 static void e1000e_update_flowctl_status(E1000ECore *core) 1747 { 1748 if (e1000e_have_autoneg(core) && 1749 core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE) { 1750 trace_e1000e_link_autoneg_flowctl(true); 1751 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1752 } else { 1753 trace_e1000e_link_autoneg_flowctl(false); 1754 } 1755 } 1756 1757 static inline void 1758 e1000e_link_down(E1000ECore *core) 1759 { 1760 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1761 e1000e_update_flowctl_status(core); 1762 } 1763 1764 static inline void 1765 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1766 { 1767 /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */ 1768 core->phy[0][PHY_CTRL] = val & ~(0x3f | 1769 MII_CR_RESET | 1770 MII_CR_RESTART_AUTO_NEG); 1771 1772 if ((val & MII_CR_RESTART_AUTO_NEG) && 1773 e1000e_have_autoneg(core)) { 1774 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1775 } 1776 } 1777 1778 static void 1779 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1780 { 1781 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1782 1783 if (val & BIT(10)) { 1784 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1785 } 1786 } 1787 1788 static void 1789 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1790 { 1791 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1792 } 1793 1794 void 1795 e1000e_core_set_link_status(E1000ECore *core) 1796 { 1797 NetClientState *nc = qemu_get_queue(core->owner_nic); 1798 uint32_t old_status = core->mac[STATUS]; 1799 1800 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1801 1802 if (nc->link_down) { 1803 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1804 } else { 1805 if (e1000e_have_autoneg(core) && 1806 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { 1807 e1000x_restart_autoneg(core->mac, core->phy[0], 1808 core->autoneg_timer); 1809 } else { 1810 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1811 e1000e_start_recv(core); 1812 } 1813 } 1814 1815 if (core->mac[STATUS] != old_status) { 1816 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1817 } 1818 } 1819 1820 static void 1821 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1822 { 1823 trace_e1000e_core_ctrl_write(index, val); 1824 1825 /* RST is self clearing */ 1826 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1827 core->mac[CTRL_DUP] = core->mac[CTRL]; 1828 1829 trace_e1000e_link_set_params( 1830 !!(val & E1000_CTRL_ASDE), 1831 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1832 !!(val & E1000_CTRL_FRCSPD), 1833 !!(val & E1000_CTRL_FRCDPX), 1834 !!(val & E1000_CTRL_RFCE), 1835 !!(val & E1000_CTRL_TFCE)); 1836 1837 if (val & E1000_CTRL_RST) { 1838 trace_e1000e_core_ctrl_sw_reset(); 1839 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 1840 } 1841 1842 if (val & E1000_CTRL_PHY_RST) { 1843 trace_e1000e_core_ctrl_phy_reset(); 1844 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1845 } 1846 } 1847 1848 static void 1849 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1850 { 1851 trace_e1000e_rx_set_rfctl(val); 1852 1853 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1854 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1855 } 1856 1857 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1858 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1859 } 1860 1861 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1862 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1863 } 1864 1865 core->mac[RFCTL] = val; 1866 } 1867 1868 static void 1869 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1870 { 1871 int i; 1872 core->rx_desc_buf_size = 0; 1873 1874 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1875 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1876 } 1877 } 1878 1879 static void 1880 e1000e_parse_rxbufsize(E1000ECore *core) 1881 { 1882 uint32_t rctl = core->mac[RCTL]; 1883 1884 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1885 1886 if (rctl & E1000_RCTL_DTYP_MASK) { 1887 uint32_t bsize; 1888 1889 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1890 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1891 1892 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1893 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1894 1895 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1896 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1897 1898 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1899 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1900 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1901 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1902 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1903 } else { 1904 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1905 } 1906 1907 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1908 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1909 1910 e1000e_calc_per_desc_buf_size(core); 1911 } 1912 1913 static void 1914 e1000e_calc_rxdesclen(E1000ECore *core) 1915 { 1916 if (e1000e_rx_use_legacy_descriptor(core)) { 1917 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1918 } else { 1919 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1920 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1921 } else { 1922 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1923 } 1924 } 1925 trace_e1000e_rx_desc_len(core->rx_desc_len); 1926 } 1927 1928 static void 1929 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1930 { 1931 core->mac[RCTL] = val; 1932 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1933 1934 if (val & E1000_RCTL_EN) { 1935 e1000e_parse_rxbufsize(core); 1936 e1000e_calc_rxdesclen(core); 1937 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1938 E1000_RING_DESC_LEN_SHIFT; 1939 1940 e1000e_start_recv(core); 1941 } 1942 } 1943 1944 static 1945 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1946 (E1000ECore *, int, uint16_t) = { 1947 [0] = { 1948 [PHY_CTRL] = e1000e_set_phy_ctrl, 1949 [PHY_PAGE] = e1000e_set_phy_page, 1950 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 1951 } 1952 }; 1953 1954 static inline void 1955 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits) 1956 { 1957 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 1958 core->mac[IMS] &= ~bits; 1959 } 1960 1961 static inline bool 1962 e1000e_postpone_interrupt(bool *interrupt_pending, 1963 E1000IntrDelayTimer *timer) 1964 { 1965 if (timer->running) { 1966 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1967 1968 *interrupt_pending = true; 1969 return true; 1970 } 1971 1972 if (timer->core->mac[timer->delay_reg] != 0) { 1973 e1000e_intrmgr_rearm_timer(timer); 1974 } 1975 1976 return false; 1977 } 1978 1979 static inline bool 1980 e1000e_itr_should_postpone(E1000ECore *core) 1981 { 1982 return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr); 1983 } 1984 1985 static inline bool 1986 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 1987 { 1988 return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx], 1989 &core->eitr[idx]); 1990 } 1991 1992 static void 1993 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 1994 { 1995 uint32_t effective_eiac; 1996 1997 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 1998 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 1999 if (vec < E1000E_MSIX_VEC_NUM) { 2000 if (!e1000e_eitr_should_postpone(core, vec)) { 2001 trace_e1000e_irq_msix_notify_vec(vec); 2002 msix_notify(core->owner, vec); 2003 } 2004 } else { 2005 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2006 } 2007 } else { 2008 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2009 } 2010 2011 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2012 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2013 core->mac[IAM] &= ~cause; 2014 } 2015 2016 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2017 2018 effective_eiac = core->mac[EIAC] & cause; 2019 2020 if (effective_eiac == E1000_ICR_OTHER) { 2021 effective_eiac |= E1000_ICR_OTHER_CAUSES; 2022 } 2023 2024 core->mac[ICR] &= ~effective_eiac; 2025 2026 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2027 core->mac[IMS] &= ~effective_eiac; 2028 } 2029 } 2030 2031 static void 2032 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2033 { 2034 if (causes & E1000_ICR_RXQ0) { 2035 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2036 E1000_IVAR_RXQ0(core->mac[IVAR])); 2037 } 2038 2039 if (causes & E1000_ICR_RXQ1) { 2040 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2041 E1000_IVAR_RXQ1(core->mac[IVAR])); 2042 } 2043 2044 if (causes & E1000_ICR_TXQ0) { 2045 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2046 E1000_IVAR_TXQ0(core->mac[IVAR])); 2047 } 2048 2049 if (causes & E1000_ICR_TXQ1) { 2050 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2051 E1000_IVAR_TXQ1(core->mac[IVAR])); 2052 } 2053 2054 if (causes & E1000_ICR_OTHER) { 2055 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2056 E1000_IVAR_OTHER(core->mac[IVAR])); 2057 } 2058 } 2059 2060 static void 2061 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2062 { 2063 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2064 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2065 if (vec < E1000E_MSIX_VEC_NUM) { 2066 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2067 msix_clr_pending(core->owner, vec); 2068 } else { 2069 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2070 } 2071 } else { 2072 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2073 } 2074 } 2075 2076 static void 2077 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2078 { 2079 if (causes & E1000_ICR_RXQ0) { 2080 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2081 E1000_IVAR_RXQ0(core->mac[IVAR])); 2082 } 2083 2084 if (causes & E1000_ICR_RXQ1) { 2085 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2086 E1000_IVAR_RXQ1(core->mac[IVAR])); 2087 } 2088 2089 if (causes & E1000_ICR_TXQ0) { 2090 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2091 E1000_IVAR_TXQ0(core->mac[IVAR])); 2092 } 2093 2094 if (causes & E1000_ICR_TXQ1) { 2095 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2096 E1000_IVAR_TXQ1(core->mac[IVAR])); 2097 } 2098 2099 if (causes & E1000_ICR_OTHER) { 2100 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2101 E1000_IVAR_OTHER(core->mac[IVAR])); 2102 } 2103 } 2104 2105 static inline void 2106 e1000e_fix_icr_asserted(E1000ECore *core) 2107 { 2108 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2109 if (core->mac[ICR]) { 2110 core->mac[ICR] |= E1000_ICR_ASSERTED; 2111 } 2112 2113 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2114 } 2115 2116 static void 2117 e1000e_send_msi(E1000ECore *core, bool msix) 2118 { 2119 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED; 2120 2121 if (msix) { 2122 e1000e_msix_notify(core, causes); 2123 } else { 2124 if (!e1000e_itr_should_postpone(core)) { 2125 trace_e1000e_irq_msi_notify(causes); 2126 msi_notify(core->owner, 0); 2127 } 2128 } 2129 } 2130 2131 static void 2132 e1000e_update_interrupt_state(E1000ECore *core) 2133 { 2134 bool interrupts_pending; 2135 bool is_msix = msix_enabled(core->owner); 2136 2137 /* Set ICR[OTHER] for MSI-X */ 2138 if (is_msix) { 2139 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2140 core->mac[ICR] |= E1000_ICR_OTHER; 2141 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2142 } 2143 } 2144 2145 e1000e_fix_icr_asserted(core); 2146 2147 /* 2148 * Make sure ICR and ICS registers have the same value. 2149 * The spec says that the ICS register is write-only. However in practice, 2150 * on real hardware ICS is readable, and for reads it has the same value as 2151 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2152 * 2153 * The VxWorks PRO/1000 driver uses this behaviour. 2154 */ 2155 core->mac[ICS] = core->mac[ICR]; 2156 2157 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false; 2158 2159 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2160 core->mac[ICR], core->mac[IMS]); 2161 2162 if (is_msix || msi_enabled(core->owner)) { 2163 if (interrupts_pending) { 2164 e1000e_send_msi(core, is_msix); 2165 } 2166 } else { 2167 if (interrupts_pending) { 2168 if (!e1000e_itr_should_postpone(core)) { 2169 e1000e_raise_legacy_irq(core); 2170 } 2171 } else { 2172 e1000e_lower_legacy_irq(core); 2173 } 2174 } 2175 } 2176 2177 static void 2178 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2179 { 2180 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 2181 2182 val |= e1000e_intmgr_collect_delayed_causes(core); 2183 core->mac[ICR] |= val; 2184 2185 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 2186 2187 e1000e_update_interrupt_state(core); 2188 } 2189 2190 static inline void 2191 e1000e_autoneg_timer(void *opaque) 2192 { 2193 E1000ECore *core = opaque; 2194 if (!qemu_get_queue(core->owner_nic)->link_down) { 2195 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2196 e1000e_start_recv(core); 2197 2198 e1000e_update_flowctl_status(core); 2199 /* signal link status change to the guest */ 2200 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2201 } 2202 } 2203 2204 static inline uint16_t 2205 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2206 { 2207 uint16_t index = (addr & 0x1ffff) >> 2; 2208 return index + (mac_reg_access[index] & 0xfffe); 2209 } 2210 2211 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2212 [0] = { 2213 [PHY_CTRL] = PHY_ANYPAGE | PHY_RW, 2214 [PHY_STATUS] = PHY_ANYPAGE | PHY_R, 2215 [PHY_ID1] = PHY_ANYPAGE | PHY_R, 2216 [PHY_ID2] = PHY_ANYPAGE | PHY_R, 2217 [PHY_AUTONEG_ADV] = PHY_ANYPAGE | PHY_RW, 2218 [PHY_LP_ABILITY] = PHY_ANYPAGE | PHY_R, 2219 [PHY_AUTONEG_EXP] = PHY_ANYPAGE | PHY_R, 2220 [PHY_NEXT_PAGE_TX] = PHY_ANYPAGE | PHY_RW, 2221 [PHY_LP_NEXT_PAGE] = PHY_ANYPAGE | PHY_R, 2222 [PHY_1000T_CTRL] = PHY_ANYPAGE | PHY_RW, 2223 [PHY_1000T_STATUS] = PHY_ANYPAGE | PHY_R, 2224 [PHY_EXT_STATUS] = PHY_ANYPAGE | PHY_R, 2225 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2226 2227 [PHY_COPPER_CTRL1] = PHY_RW, 2228 [PHY_COPPER_STAT1] = PHY_R, 2229 [PHY_COPPER_CTRL3] = PHY_RW, 2230 [PHY_RX_ERR_CNTR] = PHY_R, 2231 [PHY_OEM_BITS] = PHY_RW, 2232 [PHY_BIAS_1] = PHY_RW, 2233 [PHY_BIAS_2] = PHY_RW, 2234 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2235 [PHY_COPPER_STAT2] = PHY_R, 2236 [PHY_COPPER_CTRL2] = PHY_RW 2237 }, 2238 [2] = { 2239 [PHY_MAC_CTRL1] = PHY_RW, 2240 [PHY_MAC_INT_ENABLE] = PHY_RW, 2241 [PHY_MAC_STAT] = PHY_R, 2242 [PHY_MAC_CTRL2] = PHY_RW 2243 }, 2244 [3] = { 2245 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2246 [PHY_LED_03_POL_CTRL] = PHY_RW, 2247 [PHY_LED_TIMER_CTRL] = PHY_RW, 2248 [PHY_LED_45_CTRL] = PHY_RW 2249 }, 2250 [5] = { 2251 [PHY_1000T_SKEW] = PHY_R, 2252 [PHY_1000T_SWAP] = PHY_R 2253 }, 2254 [6] = { 2255 [PHY_CRC_COUNTERS] = PHY_R 2256 } 2257 }; 2258 2259 static bool 2260 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2261 char cap, uint8_t *page) 2262 { 2263 *page = 2264 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2265 : core->phy[0][PHY_PAGE]; 2266 2267 if (*page >= E1000E_PHY_PAGES) { 2268 return false; 2269 } 2270 2271 return e1000e_phy_regcap[*page][addr] & cap; 2272 } 2273 2274 static void 2275 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2276 uint32_t addr, uint16_t data) 2277 { 2278 assert(page < E1000E_PHY_PAGES); 2279 assert(addr < E1000E_PHY_PAGE_SIZE); 2280 2281 if (e1000e_phyreg_writeops[page][addr]) { 2282 e1000e_phyreg_writeops[page][addr](core, addr, data); 2283 } else { 2284 core->phy[page][addr] = data; 2285 } 2286 } 2287 2288 static void 2289 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2290 { 2291 uint32_t data = val & E1000_MDIC_DATA_MASK; 2292 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2293 uint8_t page; 2294 2295 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2296 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2297 } else if (val & E1000_MDIC_OP_READ) { 2298 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2299 trace_e1000e_core_mdic_read_unhandled(page, addr); 2300 val |= E1000_MDIC_ERROR; 2301 } else { 2302 val = (val ^ data) | core->phy[page][addr]; 2303 trace_e1000e_core_mdic_read(page, addr, val); 2304 } 2305 } else if (val & E1000_MDIC_OP_WRITE) { 2306 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2307 trace_e1000e_core_mdic_write_unhandled(page, addr); 2308 val |= E1000_MDIC_ERROR; 2309 } else { 2310 trace_e1000e_core_mdic_write(page, addr, data); 2311 e1000e_phy_reg_write(core, page, addr, data); 2312 } 2313 } 2314 core->mac[MDIC] = val | E1000_MDIC_READY; 2315 2316 if (val & E1000_MDIC_INT_EN) { 2317 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2318 } 2319 } 2320 2321 static void 2322 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2323 { 2324 core->mac[index] = val & 0xffff; 2325 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2326 e1000e_start_recv(core); 2327 } 2328 2329 static void 2330 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2331 { 2332 if ((val & E1000_STATUS_PHYRA) == 0) { 2333 core->mac[index] &= ~E1000_STATUS_PHYRA; 2334 } 2335 } 2336 2337 static void 2338 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2339 { 2340 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2341 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2342 2343 /* Zero self-clearing bits */ 2344 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2345 core->mac[CTRL_EXT] = val; 2346 } 2347 2348 static void 2349 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2350 { 2351 int i; 2352 2353 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2354 2355 if (!msix_enabled(core->owner)) { 2356 return; 2357 } 2358 2359 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2360 if (core->mac[PBACLR] & BIT(i)) { 2361 msix_clr_pending(core->owner, i); 2362 } 2363 } 2364 } 2365 2366 static void 2367 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2368 { 2369 core->mac[FCRTH] = val & 0xFFF8; 2370 } 2371 2372 static void 2373 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2374 { 2375 core->mac[FCRTL] = val & 0x8000FFF8; 2376 } 2377 2378 static inline void 2379 e1000e_set_16bit(E1000ECore *core, int index, uint32_t val) 2380 { 2381 core->mac[index] = val & 0xffff; 2382 } 2383 2384 static void 2385 e1000e_set_12bit(E1000ECore *core, int index, uint32_t val) 2386 { 2387 core->mac[index] = val & 0xfff; 2388 } 2389 2390 static void 2391 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2392 { 2393 core->mac[VET] = val & 0xffff; 2394 core->vet = le16_to_cpu(core->mac[VET]); 2395 trace_e1000e_vlan_vet(core->vet); 2396 } 2397 2398 static void 2399 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2400 { 2401 core->mac[index] = val & E1000_XDLEN_MASK; 2402 } 2403 2404 static void 2405 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2406 { 2407 core->mac[index] = val & E1000_XDBAL_MASK; 2408 } 2409 2410 static void 2411 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2412 { 2413 E1000E_TxRing txr; 2414 core->mac[index] = val; 2415 2416 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2417 e1000e_tx_ring_init(core, &txr, 0); 2418 e1000e_start_xmit(core, &txr); 2419 } 2420 2421 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2422 e1000e_tx_ring_init(core, &txr, 1); 2423 e1000e_start_xmit(core, &txr); 2424 } 2425 } 2426 2427 static void 2428 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2429 { 2430 E1000E_TxRing txr; 2431 int qidx = e1000e_mq_queue_idx(TDT, index); 2432 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2433 2434 core->mac[index] = val & 0xffff; 2435 2436 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2437 e1000e_tx_ring_init(core, &txr, qidx); 2438 e1000e_start_xmit(core, &txr); 2439 } 2440 } 2441 2442 static void 2443 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2444 { 2445 trace_e1000e_irq_write_ics(val); 2446 e1000e_set_interrupt_cause(core, val); 2447 } 2448 2449 static void 2450 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2451 { 2452 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2453 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2454 trace_e1000e_irq_icr_process_iame(); 2455 e1000e_clear_ims_bits(core, core->mac[IAM]); 2456 } 2457 2458 trace_e1000e_irq_icr_write(val, core->mac[ICR], core->mac[ICR] & ~val); 2459 core->mac[ICR] &= ~val; 2460 e1000e_update_interrupt_state(core); 2461 } 2462 2463 static void 2464 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2465 { 2466 trace_e1000e_irq_ims_clear_set_imc(val); 2467 e1000e_clear_ims_bits(core, val); 2468 e1000e_update_interrupt_state(core); 2469 } 2470 2471 static void 2472 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2473 { 2474 static const uint32_t ims_ext_mask = 2475 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2476 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2477 E1000_IMS_OTHER; 2478 2479 static const uint32_t ims_valid_mask = 2480 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2481 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2482 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2483 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2484 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2485 E1000_IMS_OTHER; 2486 2487 uint32_t valid_val = val & ims_valid_mask; 2488 2489 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2490 core->mac[IMS] |= valid_val; 2491 2492 if ((valid_val & ims_ext_mask) && 2493 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2494 msix_enabled(core->owner)) { 2495 e1000e_msix_clear(core, valid_val); 2496 } 2497 2498 if ((valid_val == ims_valid_mask) && 2499 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2500 trace_e1000e_irq_fire_all_timers(val); 2501 e1000e_intrmgr_fire_all_timers(core); 2502 } 2503 2504 e1000e_update_interrupt_state(core); 2505 } 2506 2507 static void 2508 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2509 { 2510 e1000e_set_16bit(core, index, val); 2511 2512 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2513 trace_e1000e_irq_rdtr_fpd_running(); 2514 e1000e_intrmgr_fire_delayed_interrupts(core); 2515 } else { 2516 trace_e1000e_irq_rdtr_fpd_not_running(); 2517 } 2518 } 2519 2520 static void 2521 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2522 { 2523 e1000e_set_16bit(core, index, val); 2524 2525 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2526 trace_e1000e_irq_tidv_fpd_running(); 2527 e1000e_intrmgr_fire_delayed_interrupts(core); 2528 } else { 2529 trace_e1000e_irq_tidv_fpd_not_running(); 2530 } 2531 } 2532 2533 static uint32_t 2534 e1000e_mac_readreg(E1000ECore *core, int index) 2535 { 2536 return core->mac[index]; 2537 } 2538 2539 static uint32_t 2540 e1000e_mac_ics_read(E1000ECore *core, int index) 2541 { 2542 trace_e1000e_irq_read_ics(core->mac[ICS]); 2543 return core->mac[ICS]; 2544 } 2545 2546 static uint32_t 2547 e1000e_mac_ims_read(E1000ECore *core, int index) 2548 { 2549 trace_e1000e_irq_read_ims(core->mac[IMS]); 2550 return core->mac[IMS]; 2551 } 2552 2553 #define E1000E_LOW_BITS_READ_FUNC(num) \ 2554 static uint32_t \ 2555 e1000e_mac_low##num##_read(E1000ECore *core, int index) \ 2556 { \ 2557 return core->mac[index] & (BIT(num) - 1); \ 2558 } \ 2559 2560 #define E1000E_LOW_BITS_READ(num) \ 2561 e1000e_mac_low##num##_read 2562 2563 E1000E_LOW_BITS_READ_FUNC(4); 2564 E1000E_LOW_BITS_READ_FUNC(6); 2565 E1000E_LOW_BITS_READ_FUNC(11); 2566 E1000E_LOW_BITS_READ_FUNC(13); 2567 E1000E_LOW_BITS_READ_FUNC(16); 2568 2569 static uint32_t 2570 e1000e_mac_swsm_read(E1000ECore *core, int index) 2571 { 2572 uint32_t val = core->mac[SWSM]; 2573 core->mac[SWSM] = val | 1; 2574 return val; 2575 } 2576 2577 static uint32_t 2578 e1000e_mac_itr_read(E1000ECore *core, int index) 2579 { 2580 return core->itr_guest_value; 2581 } 2582 2583 static uint32_t 2584 e1000e_mac_eitr_read(E1000ECore *core, int index) 2585 { 2586 return core->eitr_guest_value[index - EITR]; 2587 } 2588 2589 static uint32_t 2590 e1000e_mac_icr_read(E1000ECore *core, int index) 2591 { 2592 uint32_t ret = core->mac[ICR]; 2593 trace_e1000e_irq_icr_read_entry(ret); 2594 2595 if (core->mac[IMS] == 0) { 2596 trace_e1000e_irq_icr_clear_zero_ims(); 2597 core->mac[ICR] = 0; 2598 } 2599 2600 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2601 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2602 trace_e1000e_irq_icr_clear_iame(); 2603 core->mac[ICR] = 0; 2604 trace_e1000e_irq_icr_process_iame(); 2605 e1000e_clear_ims_bits(core, core->mac[IAM]); 2606 } 2607 2608 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2609 e1000e_update_interrupt_state(core); 2610 return ret; 2611 } 2612 2613 static uint32_t 2614 e1000e_mac_read_clr4(E1000ECore *core, int index) 2615 { 2616 uint32_t ret = core->mac[index]; 2617 2618 core->mac[index] = 0; 2619 return ret; 2620 } 2621 2622 static uint32_t 2623 e1000e_mac_read_clr8(E1000ECore *core, int index) 2624 { 2625 uint32_t ret = core->mac[index]; 2626 2627 core->mac[index] = 0; 2628 core->mac[index - 1] = 0; 2629 return ret; 2630 } 2631 2632 static uint32_t 2633 e1000e_get_ctrl(E1000ECore *core, int index) 2634 { 2635 uint32_t val = core->mac[CTRL]; 2636 2637 trace_e1000e_link_read_params( 2638 !!(val & E1000_CTRL_ASDE), 2639 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2640 !!(val & E1000_CTRL_FRCSPD), 2641 !!(val & E1000_CTRL_FRCDPX), 2642 !!(val & E1000_CTRL_RFCE), 2643 !!(val & E1000_CTRL_TFCE)); 2644 2645 return val; 2646 } 2647 2648 static uint32_t 2649 e1000e_get_status(E1000ECore *core, int index) 2650 { 2651 uint32_t res = core->mac[STATUS]; 2652 2653 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2654 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2655 } 2656 2657 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2658 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2659 } else { 2660 res |= E1000_STATUS_FD; 2661 } 2662 2663 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2664 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2665 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2666 case E1000_CTRL_SPD_10: 2667 res |= E1000_STATUS_SPEED_10; 2668 break; 2669 case E1000_CTRL_SPD_100: 2670 res |= E1000_STATUS_SPEED_100; 2671 break; 2672 case E1000_CTRL_SPD_1000: 2673 default: 2674 res |= E1000_STATUS_SPEED_1000; 2675 break; 2676 } 2677 } else { 2678 res |= E1000_STATUS_SPEED_1000; 2679 } 2680 2681 trace_e1000e_link_status( 2682 !!(res & E1000_STATUS_LU), 2683 !!(res & E1000_STATUS_FD), 2684 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2685 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2686 2687 return res; 2688 } 2689 2690 static uint32_t 2691 e1000e_get_tarc(E1000ECore *core, int index) 2692 { 2693 return core->mac[index] & ((BIT(11) - 1) | 2694 BIT(27) | 2695 BIT(28) | 2696 BIT(29) | 2697 BIT(30)); 2698 } 2699 2700 static void 2701 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2702 { 2703 core->mac[index] = val; 2704 } 2705 2706 static void 2707 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2708 { 2709 uint32_t macaddr[2]; 2710 2711 core->mac[index] = val; 2712 2713 macaddr[0] = cpu_to_le32(core->mac[RA]); 2714 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2715 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2716 (uint8_t *) macaddr); 2717 2718 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2719 } 2720 2721 static void 2722 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2723 { 2724 static const uint32_t ro_bits = E1000_EECD_PRES | 2725 E1000_EECD_AUTO_RD | 2726 E1000_EECD_SIZE_EX_MASK; 2727 2728 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2729 } 2730 2731 static void 2732 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2733 { 2734 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2735 uint32_t flags = 0; 2736 uint32_t data = 0; 2737 2738 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2739 data = core->eeprom[addr]; 2740 flags = E1000_EERW_DONE; 2741 } 2742 2743 core->mac[EERD] = flags | 2744 (addr << E1000_EERW_ADDR_SHIFT) | 2745 (data << E1000_EERW_DATA_SHIFT); 2746 } 2747 2748 static void 2749 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2750 { 2751 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2752 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2753 uint32_t flags = 0; 2754 2755 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2756 core->eeprom[addr] = data; 2757 flags = E1000_EERW_DONE; 2758 } 2759 2760 core->mac[EERD] = flags | 2761 (addr << E1000_EERW_ADDR_SHIFT) | 2762 (data << E1000_EERW_DATA_SHIFT); 2763 } 2764 2765 static void 2766 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2767 { 2768 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2769 } 2770 2771 static void 2772 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2773 { 2774 uint32_t interval = val & 0xffff; 2775 2776 trace_e1000e_irq_itr_set(val); 2777 2778 core->itr_guest_value = interval; 2779 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2780 } 2781 2782 static void 2783 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2784 { 2785 uint32_t interval = val & 0xffff; 2786 uint32_t eitr_num = index - EITR; 2787 2788 trace_e1000e_irq_eitr_set(eitr_num, val); 2789 2790 core->eitr_guest_value[eitr_num] = interval; 2791 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2792 } 2793 2794 static void 2795 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2796 { 2797 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2798 hw_error("e1000e: PSRCTL.BSIZE0 cannot be zero"); 2799 } 2800 2801 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2802 hw_error("e1000e: PSRCTL.BSIZE1 cannot be zero"); 2803 } 2804 2805 core->mac[PSRCTL] = val; 2806 } 2807 2808 static void 2809 e1000e_update_rx_offloads(E1000ECore *core) 2810 { 2811 int cso_state = e1000e_rx_l4_cso_enabled(core); 2812 2813 trace_e1000e_rx_set_cso(cso_state); 2814 2815 if (core->has_vnet) { 2816 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2817 cso_state, 0, 0, 0, 0); 2818 } 2819 } 2820 2821 static void 2822 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2823 { 2824 core->mac[RXCSUM] = val; 2825 e1000e_update_rx_offloads(core); 2826 } 2827 2828 static void 2829 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2830 { 2831 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2832 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2833 } 2834 2835 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2836 static uint32_t (*e1000e_macreg_readops[])(E1000ECore *, int) = { 2837 e1000e_getreg(PBA), 2838 e1000e_getreg(WUFC), 2839 e1000e_getreg(MANC), 2840 e1000e_getreg(TOTL), 2841 e1000e_getreg(RDT0), 2842 e1000e_getreg(RDBAH0), 2843 e1000e_getreg(TDBAL1), 2844 e1000e_getreg(RDLEN0), 2845 e1000e_getreg(RDH1), 2846 e1000e_getreg(LATECOL), 2847 e1000e_getreg(SEC), 2848 e1000e_getreg(XONTXC), 2849 e1000e_getreg(WUS), 2850 e1000e_getreg(GORCL), 2851 e1000e_getreg(MGTPRC), 2852 e1000e_getreg(EERD), 2853 e1000e_getreg(EIAC), 2854 e1000e_getreg(PSRCTL), 2855 e1000e_getreg(MANC2H), 2856 e1000e_getreg(RXCSUM), 2857 e1000e_getreg(GSCL_3), 2858 e1000e_getreg(GSCN_2), 2859 e1000e_getreg(RSRPD), 2860 e1000e_getreg(RDBAL1), 2861 e1000e_getreg(FCAH), 2862 e1000e_getreg(FCRTH), 2863 e1000e_getreg(FLOP), 2864 e1000e_getreg(FLASHT), 2865 e1000e_getreg(RXSTMPH), 2866 e1000e_getreg(TXSTMPL), 2867 e1000e_getreg(TIMADJL), 2868 e1000e_getreg(TXDCTL), 2869 e1000e_getreg(RDH0), 2870 e1000e_getreg(TDT1), 2871 e1000e_getreg(TNCRS), 2872 e1000e_getreg(RJC), 2873 e1000e_getreg(IAM), 2874 e1000e_getreg(GSCL_2), 2875 e1000e_getreg(RDBAH1), 2876 e1000e_getreg(FLSWDATA), 2877 e1000e_getreg(RXSATRH), 2878 e1000e_getreg(TIPG), 2879 e1000e_getreg(FLMNGCTL), 2880 e1000e_getreg(FLMNGCNT), 2881 e1000e_getreg(TSYNCTXCTL), 2882 e1000e_getreg(EXTCNF_SIZE), 2883 e1000e_getreg(EXTCNF_CTRL), 2884 e1000e_getreg(EEMNGDATA), 2885 e1000e_getreg(CTRL_EXT), 2886 e1000e_getreg(SYSTIMH), 2887 e1000e_getreg(EEMNGCTL), 2888 e1000e_getreg(FLMNGDATA), 2889 e1000e_getreg(TSYNCRXCTL), 2890 e1000e_getreg(TDH), 2891 e1000e_getreg(LEDCTL), 2892 e1000e_getreg(STATUS), 2893 e1000e_getreg(TCTL), 2894 e1000e_getreg(TDBAL), 2895 e1000e_getreg(TDLEN), 2896 e1000e_getreg(TDH1), 2897 e1000e_getreg(RADV), 2898 e1000e_getreg(ECOL), 2899 e1000e_getreg(DC), 2900 e1000e_getreg(RLEC), 2901 e1000e_getreg(XOFFTXC), 2902 e1000e_getreg(RFC), 2903 e1000e_getreg(RNBC), 2904 e1000e_getreg(MGTPTC), 2905 e1000e_getreg(TIMINCA), 2906 e1000e_getreg(RXCFGL), 2907 e1000e_getreg(MFUTP01), 2908 e1000e_getreg(FACTPS), 2909 e1000e_getreg(GSCL_1), 2910 e1000e_getreg(GSCN_0), 2911 e1000e_getreg(GCR2), 2912 e1000e_getreg(RDT1), 2913 e1000e_getreg(PBACLR), 2914 e1000e_getreg(FCTTV), 2915 e1000e_getreg(EEWR), 2916 e1000e_getreg(FLSWCTL), 2917 e1000e_getreg(RXDCTL1), 2918 e1000e_getreg(RXSATRL), 2919 e1000e_getreg(SYSTIML), 2920 e1000e_getreg(RXUDP), 2921 e1000e_getreg(TORL), 2922 e1000e_getreg(TDLEN1), 2923 e1000e_getreg(MCC), 2924 e1000e_getreg(WUC), 2925 e1000e_getreg(EECD), 2926 e1000e_getreg(MFUTP23), 2927 e1000e_getreg(RAID), 2928 e1000e_getreg(FCRTV), 2929 e1000e_getreg(TXDCTL1), 2930 e1000e_getreg(RCTL), 2931 e1000e_getreg(TDT), 2932 e1000e_getreg(MDIC), 2933 e1000e_getreg(FCRUC), 2934 e1000e_getreg(VET), 2935 e1000e_getreg(RDBAL0), 2936 e1000e_getreg(TDBAH1), 2937 e1000e_getreg(RDTR), 2938 e1000e_getreg(SCC), 2939 e1000e_getreg(COLC), 2940 e1000e_getreg(CEXTERR), 2941 e1000e_getreg(XOFFRXC), 2942 e1000e_getreg(IPAV), 2943 e1000e_getreg(GOTCL), 2944 e1000e_getreg(MGTPDC), 2945 e1000e_getreg(GCR), 2946 e1000e_getreg(IVAR), 2947 e1000e_getreg(POEMB), 2948 e1000e_getreg(MFVAL), 2949 e1000e_getreg(FUNCTAG), 2950 e1000e_getreg(GSCL_4), 2951 e1000e_getreg(GSCN_3), 2952 e1000e_getreg(MRQC), 2953 e1000e_getreg(RDLEN1), 2954 e1000e_getreg(FCT), 2955 e1000e_getreg(FLA), 2956 e1000e_getreg(FLOL), 2957 e1000e_getreg(RXDCTL), 2958 e1000e_getreg(RXSTMPL), 2959 e1000e_getreg(TXSTMPH), 2960 e1000e_getreg(TIMADJH), 2961 e1000e_getreg(FCRTL), 2962 e1000e_getreg(TDBAH), 2963 e1000e_getreg(TADV), 2964 e1000e_getreg(XONRXC), 2965 e1000e_getreg(TSCTFC), 2966 e1000e_getreg(RFCTL), 2967 e1000e_getreg(GSCN_1), 2968 e1000e_getreg(FCAL), 2969 e1000e_getreg(FLSWCNT), 2970 2971 [TOTH] = e1000e_mac_read_clr8, 2972 [GOTCH] = e1000e_mac_read_clr8, 2973 [PRC64] = e1000e_mac_read_clr4, 2974 [PRC255] = e1000e_mac_read_clr4, 2975 [PRC1023] = e1000e_mac_read_clr4, 2976 [PTC64] = e1000e_mac_read_clr4, 2977 [PTC255] = e1000e_mac_read_clr4, 2978 [PTC1023] = e1000e_mac_read_clr4, 2979 [GPRC] = e1000e_mac_read_clr4, 2980 [TPT] = e1000e_mac_read_clr4, 2981 [RUC] = e1000e_mac_read_clr4, 2982 [BPRC] = e1000e_mac_read_clr4, 2983 [MPTC] = e1000e_mac_read_clr4, 2984 [IAC] = e1000e_mac_read_clr4, 2985 [ICR] = e1000e_mac_icr_read, 2986 [RDFH] = E1000E_LOW_BITS_READ(13), 2987 [RDFHS] = E1000E_LOW_BITS_READ(13), 2988 [RDFPC] = E1000E_LOW_BITS_READ(13), 2989 [TDFH] = E1000E_LOW_BITS_READ(13), 2990 [TDFHS] = E1000E_LOW_BITS_READ(13), 2991 [STATUS] = e1000e_get_status, 2992 [TARC0] = e1000e_get_tarc, 2993 [PBS] = E1000E_LOW_BITS_READ(6), 2994 [ICS] = e1000e_mac_ics_read, 2995 [AIT] = E1000E_LOW_BITS_READ(16), 2996 [TORH] = e1000e_mac_read_clr8, 2997 [GORCH] = e1000e_mac_read_clr8, 2998 [PRC127] = e1000e_mac_read_clr4, 2999 [PRC511] = e1000e_mac_read_clr4, 3000 [PRC1522] = e1000e_mac_read_clr4, 3001 [PTC127] = e1000e_mac_read_clr4, 3002 [PTC511] = e1000e_mac_read_clr4, 3003 [PTC1522] = e1000e_mac_read_clr4, 3004 [GPTC] = e1000e_mac_read_clr4, 3005 [TPR] = e1000e_mac_read_clr4, 3006 [ROC] = e1000e_mac_read_clr4, 3007 [MPRC] = e1000e_mac_read_clr4, 3008 [BPTC] = e1000e_mac_read_clr4, 3009 [TSCTC] = e1000e_mac_read_clr4, 3010 [ITR] = e1000e_mac_itr_read, 3011 [RDFT] = E1000E_LOW_BITS_READ(13), 3012 [RDFTS] = E1000E_LOW_BITS_READ(13), 3013 [TDFPC] = E1000E_LOW_BITS_READ(13), 3014 [TDFT] = E1000E_LOW_BITS_READ(13), 3015 [TDFTS] = E1000E_LOW_BITS_READ(13), 3016 [CTRL] = e1000e_get_ctrl, 3017 [TARC1] = e1000e_get_tarc, 3018 [SWSM] = e1000e_mac_swsm_read, 3019 [IMS] = e1000e_mac_ims_read, 3020 3021 [CRCERRS ... MPC] = e1000e_mac_readreg, 3022 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3023 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3024 [RA ... RA + 31] = e1000e_mac_readreg, 3025 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3026 [MTA ... MTA + 127] = e1000e_mac_readreg, 3027 [VFTA ... VFTA + 127] = e1000e_mac_readreg, 3028 [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4), 3029 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3030 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3031 [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11), 3032 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3033 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3034 [RETA ... RETA + 31] = e1000e_mac_readreg, 3035 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3036 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3037 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3038 }; 3039 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3040 3041 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3042 static void (*e1000e_macreg_writeops[])(E1000ECore *, int, uint32_t) = { 3043 e1000e_putreg(PBA), 3044 e1000e_putreg(SWSM), 3045 e1000e_putreg(WUFC), 3046 e1000e_putreg(RDBAH1), 3047 e1000e_putreg(TDBAH), 3048 e1000e_putreg(TXDCTL), 3049 e1000e_putreg(RDBAH0), 3050 e1000e_putreg(LEDCTL), 3051 e1000e_putreg(FCAL), 3052 e1000e_putreg(FCRUC), 3053 e1000e_putreg(AIT), 3054 e1000e_putreg(TDFH), 3055 e1000e_putreg(TDFT), 3056 e1000e_putreg(TDFHS), 3057 e1000e_putreg(TDFTS), 3058 e1000e_putreg(TDFPC), 3059 e1000e_putreg(WUC), 3060 e1000e_putreg(WUS), 3061 e1000e_putreg(RDFH), 3062 e1000e_putreg(RDFT), 3063 e1000e_putreg(RDFHS), 3064 e1000e_putreg(RDFTS), 3065 e1000e_putreg(RDFPC), 3066 e1000e_putreg(IPAV), 3067 e1000e_putreg(TDBAH1), 3068 e1000e_putreg(TIMINCA), 3069 e1000e_putreg(IAM), 3070 e1000e_putreg(EIAC), 3071 e1000e_putreg(IVAR), 3072 e1000e_putreg(TARC0), 3073 e1000e_putreg(TARC1), 3074 e1000e_putreg(FLSWDATA), 3075 e1000e_putreg(POEMB), 3076 e1000e_putreg(PBS), 3077 e1000e_putreg(MFUTP01), 3078 e1000e_putreg(MFUTP23), 3079 e1000e_putreg(MANC), 3080 e1000e_putreg(MANC2H), 3081 e1000e_putreg(MFVAL), 3082 e1000e_putreg(EXTCNF_CTRL), 3083 e1000e_putreg(FACTPS), 3084 e1000e_putreg(FUNCTAG), 3085 e1000e_putreg(GSCL_1), 3086 e1000e_putreg(GSCL_2), 3087 e1000e_putreg(GSCL_3), 3088 e1000e_putreg(GSCL_4), 3089 e1000e_putreg(GSCN_0), 3090 e1000e_putreg(GSCN_1), 3091 e1000e_putreg(GSCN_2), 3092 e1000e_putreg(GSCN_3), 3093 e1000e_putreg(GCR2), 3094 e1000e_putreg(MRQC), 3095 e1000e_putreg(FLOP), 3096 e1000e_putreg(FLOL), 3097 e1000e_putreg(FLSWCTL), 3098 e1000e_putreg(FLSWCNT), 3099 e1000e_putreg(FLA), 3100 e1000e_putreg(RXDCTL1), 3101 e1000e_putreg(TXDCTL1), 3102 e1000e_putreg(TIPG), 3103 e1000e_putreg(RXSTMPH), 3104 e1000e_putreg(RXSTMPL), 3105 e1000e_putreg(RXSATRL), 3106 e1000e_putreg(RXSATRH), 3107 e1000e_putreg(TXSTMPL), 3108 e1000e_putreg(TXSTMPH), 3109 e1000e_putreg(SYSTIML), 3110 e1000e_putreg(SYSTIMH), 3111 e1000e_putreg(TIMADJL), 3112 e1000e_putreg(TIMADJH), 3113 e1000e_putreg(RXUDP), 3114 e1000e_putreg(RXCFGL), 3115 e1000e_putreg(TSYNCRXCTL), 3116 e1000e_putreg(TSYNCTXCTL), 3117 e1000e_putreg(FLSWDATA), 3118 e1000e_putreg(EXTCNF_SIZE), 3119 e1000e_putreg(EEMNGCTL), 3120 e1000e_putreg(RA), 3121 3122 [TDH1] = e1000e_set_16bit, 3123 [TDT1] = e1000e_set_tdt, 3124 [TCTL] = e1000e_set_tctl, 3125 [TDT] = e1000e_set_tdt, 3126 [MDIC] = e1000e_set_mdic, 3127 [ICS] = e1000e_set_ics, 3128 [TDH] = e1000e_set_16bit, 3129 [RDH0] = e1000e_set_16bit, 3130 [RDT0] = e1000e_set_rdt, 3131 [IMC] = e1000e_set_imc, 3132 [IMS] = e1000e_set_ims, 3133 [ICR] = e1000e_set_icr, 3134 [EECD] = e1000e_set_eecd, 3135 [RCTL] = e1000e_set_rx_control, 3136 [CTRL] = e1000e_set_ctrl, 3137 [RDTR] = e1000e_set_rdtr, 3138 [RADV] = e1000e_set_16bit, 3139 [TADV] = e1000e_set_16bit, 3140 [ITR] = e1000e_set_itr, 3141 [EERD] = e1000e_set_eerd, 3142 [GCR] = e1000e_set_gcr, 3143 [PSRCTL] = e1000e_set_psrctl, 3144 [RXCSUM] = e1000e_set_rxcsum, 3145 [RAID] = e1000e_set_16bit, 3146 [RSRPD] = e1000e_set_12bit, 3147 [TIDV] = e1000e_set_tidv, 3148 [TDLEN1] = e1000e_set_dlen, 3149 [TDLEN] = e1000e_set_dlen, 3150 [RDLEN0] = e1000e_set_dlen, 3151 [RDLEN1] = e1000e_set_dlen, 3152 [TDBAL] = e1000e_set_dbal, 3153 [TDBAL1] = e1000e_set_dbal, 3154 [RDBAL0] = e1000e_set_dbal, 3155 [RDBAL1] = e1000e_set_dbal, 3156 [RDH1] = e1000e_set_16bit, 3157 [RDT1] = e1000e_set_rdt, 3158 [STATUS] = e1000e_set_status, 3159 [PBACLR] = e1000e_set_pbaclr, 3160 [CTRL_EXT] = e1000e_set_ctrlext, 3161 [FCAH] = e1000e_set_16bit, 3162 [FCT] = e1000e_set_16bit, 3163 [FCTTV] = e1000e_set_16bit, 3164 [FCRTV] = e1000e_set_16bit, 3165 [FCRTH] = e1000e_set_fcrth, 3166 [FCRTL] = e1000e_set_fcrtl, 3167 [VET] = e1000e_set_vet, 3168 [RXDCTL] = e1000e_set_rxdctl, 3169 [FLASHT] = e1000e_set_16bit, 3170 [EEWR] = e1000e_set_eewr, 3171 [CTRL_DUP] = e1000e_set_ctrl, 3172 [RFCTL] = e1000e_set_rfctl, 3173 [RA + 1] = e1000e_mac_setmacaddr, 3174 3175 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3176 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3177 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3178 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3179 [MTA ... MTA + 127] = e1000e_mac_writereg, 3180 [VFTA ... VFTA + 127] = e1000e_mac_writereg, 3181 [FFMT ... FFMT + 254] = e1000e_mac_writereg, 3182 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3183 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3184 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3185 [FFLT ... FFLT + 10] = e1000e_mac_writereg, 3186 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3187 [RETA ... RETA + 31] = e1000e_mac_writereg, 3188 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3189 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3190 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3191 }; 3192 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3193 3194 enum { MAC_ACCESS_PARTIAL = 1 }; 3195 3196 /* The array below combines alias offsets of the index values for the 3197 * MAC registers that have aliases, with the indication of not fully 3198 * implemented registers (lowest bit). This combination is possible 3199 * because all of the offsets are even. */ 3200 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3201 /* Alias index offsets */ 3202 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3203 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3204 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3205 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3206 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3207 [RA_A ... RA_A + 31] = 0x14f0, 3208 [VFTA_A ... VFTA_A + 127] = 0x1400, 3209 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3210 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3211 /* Access options */ 3212 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3213 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3214 [RDFPC] = MAC_ACCESS_PARTIAL, 3215 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3216 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3217 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3218 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3219 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3220 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3221 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3222 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3223 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3224 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3225 }; 3226 3227 void 3228 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3229 { 3230 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3231 3232 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3233 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3234 trace_e1000e_wrn_regs_write_trivial(index << 2); 3235 } 3236 trace_e1000e_core_write(index << 2, size, val); 3237 e1000e_macreg_writeops[index](core, index, val); 3238 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3239 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3240 } else { 3241 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3242 } 3243 } 3244 3245 uint64_t 3246 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3247 { 3248 uint64_t val; 3249 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3250 3251 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3252 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3253 trace_e1000e_wrn_regs_read_trivial(index << 2); 3254 } 3255 val = e1000e_macreg_readops[index](core, index); 3256 trace_e1000e_core_read(index << 2, size, val); 3257 return val; 3258 } else { 3259 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3260 } 3261 return 0; 3262 } 3263 3264 static inline void 3265 e1000e_autoneg_pause(E1000ECore *core) 3266 { 3267 timer_del(core->autoneg_timer); 3268 } 3269 3270 static void 3271 e1000e_autoneg_resume(E1000ECore *core) 3272 { 3273 if (e1000e_have_autoneg(core) && 3274 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { 3275 qemu_get_queue(core->owner_nic)->link_down = false; 3276 timer_mod(core->autoneg_timer, 3277 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3278 } 3279 } 3280 3281 static void 3282 e1000e_vm_state_change(void *opaque, int running, RunState state) 3283 { 3284 E1000ECore *core = opaque; 3285 3286 if (running) { 3287 trace_e1000e_vm_state_running(); 3288 e1000e_intrmgr_resume(core); 3289 e1000e_autoneg_resume(core); 3290 } else { 3291 trace_e1000e_vm_state_stopped(); 3292 e1000e_autoneg_pause(core); 3293 e1000e_intrmgr_pause(core); 3294 } 3295 } 3296 3297 void 3298 e1000e_core_pci_realize(E1000ECore *core, 3299 const uint16_t *eeprom_templ, 3300 uint32_t eeprom_size, 3301 const uint8_t *macaddr) 3302 { 3303 int i; 3304 3305 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3306 e1000e_autoneg_timer, core); 3307 e1000e_intrmgr_pci_realize(core); 3308 3309 core->vmstate = 3310 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3311 3312 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3313 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner, 3314 E1000E_MAX_TX_FRAGS, core->has_vnet); 3315 } 3316 3317 net_rx_pkt_init(&core->rx_pkt, core->has_vnet); 3318 3319 e1000x_core_prepare_eeprom(core->eeprom, 3320 eeprom_templ, 3321 eeprom_size, 3322 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3323 macaddr); 3324 e1000e_update_rx_offloads(core); 3325 } 3326 3327 void 3328 e1000e_core_pci_uninit(E1000ECore *core) 3329 { 3330 int i; 3331 3332 timer_del(core->autoneg_timer); 3333 timer_free(core->autoneg_timer); 3334 3335 e1000e_intrmgr_pci_unint(core); 3336 3337 qemu_del_vm_change_state_handler(core->vmstate); 3338 3339 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3340 net_tx_pkt_reset(core->tx[i].tx_pkt); 3341 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3342 } 3343 3344 net_rx_pkt_uninit(core->rx_pkt); 3345 } 3346 3347 static const uint16_t 3348 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3349 [0] = { 3350 [PHY_CTRL] = MII_CR_SPEED_SELECT_MSB | 3351 MII_CR_FULL_DUPLEX | 3352 MII_CR_AUTO_NEG_EN, 3353 3354 [PHY_STATUS] = MII_SR_EXTENDED_CAPS | 3355 MII_SR_LINK_STATUS | 3356 MII_SR_AUTONEG_CAPS | 3357 MII_SR_PREAMBLE_SUPPRESS | 3358 MII_SR_EXTENDED_STATUS | 3359 MII_SR_10T_HD_CAPS | 3360 MII_SR_10T_FD_CAPS | 3361 MII_SR_100X_HD_CAPS | 3362 MII_SR_100X_FD_CAPS, 3363 3364 [PHY_ID1] = 0x141, 3365 [PHY_ID2] = E1000_PHY_ID2_82574x, 3366 [PHY_AUTONEG_ADV] = 0xde1, 3367 [PHY_LP_ABILITY] = 0x7e0, 3368 [PHY_AUTONEG_EXP] = BIT(2), 3369 [PHY_NEXT_PAGE_TX] = BIT(0) | BIT(13), 3370 [PHY_1000T_CTRL] = BIT(8) | BIT(9) | BIT(10) | BIT(11), 3371 [PHY_1000T_STATUS] = 0x3c00, 3372 [PHY_EXT_STATUS] = BIT(12) | BIT(13), 3373 3374 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3375 BIT(12) | BIT(13), 3376 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3377 }, 3378 [2] = { 3379 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3380 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3381 }, 3382 [3] = { 3383 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3384 } 3385 }; 3386 3387 static const uint32_t e1000e_mac_reg_init[] = { 3388 [PBA] = 0x00140014, 3389 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3390 [EXTCNF_CTRL] = BIT(3), 3391 [EEMNGCTL] = BIT(31), 3392 [FLASHT] = 0x2, 3393 [FLSWCTL] = BIT(30) | BIT(31), 3394 [FLOL] = BIT(0), 3395 [RXDCTL] = BIT(16), 3396 [RXDCTL1] = BIT(16), 3397 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3398 [RXCFGL] = 0x88F7, 3399 [RXUDP] = 0x319, 3400 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3401 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3402 E1000_CTRL_ADVD3WUC, 3403 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3404 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3405 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3406 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3407 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3408 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3409 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3410 [EERD] = E1000_EERW_DONE, 3411 [EEWR] = E1000_EERW_DONE, 3412 [GCR] = E1000_L0S_ADJUST | 3413 E1000_L1_ENTRY_LATENCY_MSB | 3414 E1000_L1_ENTRY_LATENCY_LSB, 3415 [TDFH] = 0x600, 3416 [TDFT] = 0x600, 3417 [TDFHS] = 0x600, 3418 [TDFTS] = 0x600, 3419 [POEMB] = 0x30D, 3420 [PBS] = 0x028, 3421 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3422 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3423 [SWSM] = 1, 3424 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3425 [ITR] = E1000E_MIN_XITR, 3426 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3427 }; 3428 3429 void 3430 e1000e_core_reset(E1000ECore *core) 3431 { 3432 int i; 3433 3434 timer_del(core->autoneg_timer); 3435 3436 e1000e_intrmgr_reset(core); 3437 3438 memset(core->phy, 0, sizeof core->phy); 3439 memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3440 memset(core->mac, 0, sizeof core->mac); 3441 memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init); 3442 3443 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3444 3445 if (qemu_get_queue(core->owner_nic)->link_down) { 3446 e1000e_link_down(core); 3447 } 3448 3449 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3450 3451 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3452 net_tx_pkt_reset(core->tx[i].tx_pkt); 3453 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3454 core->tx[i].skip_cp = false; 3455 } 3456 } 3457 3458 void e1000e_core_pre_save(E1000ECore *core) 3459 { 3460 int i; 3461 NetClientState *nc = qemu_get_queue(core->owner_nic); 3462 3463 /* 3464 * If link is down and auto-negotiation is supported and ongoing, 3465 * complete auto-negotiation immediately. This allows us to look 3466 * at MII_SR_AUTONEG_COMPLETE to infer link status on load. 3467 */ 3468 if (nc->link_down && e1000e_have_autoneg(core)) { 3469 core->phy[0][PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE; 3470 e1000e_update_flowctl_status(core); 3471 } 3472 3473 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3474 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3475 core->tx[i].skip_cp = true; 3476 } 3477 } 3478 } 3479 3480 int 3481 e1000e_core_post_load(E1000ECore *core) 3482 { 3483 NetClientState *nc = qemu_get_queue(core->owner_nic); 3484 3485 /* nc.link_down can't be migrated, so infer link_down according 3486 * to link status bit in core.mac[STATUS]. 3487 */ 3488 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3489 3490 return 0; 3491 } 3492