xref: /qemu/hw/net/fsl_etsec/etsec.h (revision abff1abf)
1 /*
2  * QEMU Freescale eTSEC Emulator
3  *
4  * Copyright (c) 2011-2013 AdaCore
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #ifndef ETSEC_H
26 #define ETSEC_H
27 
28 #include "hw/sysbus.h"
29 #include "net/net.h"
30 #include "hw/ptimer.h"
31 
32 /* Buffer Descriptors */
33 
34 typedef struct eTSEC_rxtx_bd {
35     uint16_t flags;
36     uint16_t length;
37     uint32_t bufptr;
38 } eTSEC_rxtx_bd;
39 
40 #define BD_WRAP       (1 << 13)
41 #define BD_INTERRUPT  (1 << 12)
42 #define BD_LAST       (1 << 11)
43 
44 #define BD_TX_READY     (1 << 15)
45 #define BD_TX_PADCRC    (1 << 14)
46 #define BD_TX_TC        (1 << 10)
47 #define BD_TX_PREDEF    (1 << 9)
48 #define BD_TX_HFELC     (1 << 7)
49 #define BD_TX_CFRL      (1 << 6)
50 #define BD_TX_RC_MASK   0xF
51 #define BD_TX_RC_OFFSET 0x2
52 #define BD_TX_TOEUN     (1 << 1)
53 #define BD_TX_TR        (1 << 0)
54 
55 #define BD_RX_EMPTY     (1 << 15)
56 #define BD_RX_RO1       (1 << 14)
57 #define BD_RX_FIRST     (1 << 10)
58 #define BD_RX_MISS      (1 << 8)
59 #define BD_RX_BROADCAST (1 << 7)
60 #define BD_RX_MULTICAST (1 << 6)
61 #define BD_RX_LG        (1 << 5)
62 #define BD_RX_NO        (1 << 4)
63 #define BD_RX_SH        (1 << 3)
64 #define BD_RX_CR        (1 << 2)
65 #define BD_RX_OV        (1 << 1)
66 #define BD_RX_TR        (1 << 0)
67 
68 /* Tx FCB flags */
69 #define FCB_TX_VLN     (1 << 7)
70 #define FCB_TX_IP      (1 << 6)
71 #define FCB_TX_IP6     (1 << 5)
72 #define FCB_TX_TUP     (1 << 4)
73 #define FCB_TX_UDP     (1 << 3)
74 #define FCB_TX_CIP     (1 << 2)
75 #define FCB_TX_CTU     (1 << 1)
76 #define FCB_TX_NPH     (1 << 0)
77 
78 /* PHY Status Register */
79 #define MII_SR_EXTENDED_CAPS     0x0001    /* Extended register capabilities */
80 #define MII_SR_JABBER_DETECT     0x0002    /* Jabber Detected */
81 #define MII_SR_LINK_STATUS       0x0004    /* Link Status 1 = link */
82 #define MII_SR_AUTONEG_CAPS      0x0008    /* Auto Neg Capable */
83 #define MII_SR_REMOTE_FAULT      0x0010    /* Remote Fault Detect */
84 #define MII_SR_AUTONEG_COMPLETE  0x0020    /* Auto Neg Complete */
85 #define MII_SR_PREAMBLE_SUPPRESS 0x0040    /* Preamble may be suppressed */
86 #define MII_SR_EXTENDED_STATUS   0x0100    /* Ext. status info in Reg 0x0F */
87 #define MII_SR_100T2_HD_CAPS     0x0200    /* 100T2 Half Duplex Capable */
88 #define MII_SR_100T2_FD_CAPS     0x0400    /* 100T2 Full Duplex Capable */
89 #define MII_SR_10T_HD_CAPS       0x0800    /* 10T   Half Duplex Capable */
90 #define MII_SR_10T_FD_CAPS       0x1000    /* 10T   Full Duplex Capable */
91 #define MII_SR_100X_HD_CAPS      0x2000    /* 100X  Half Duplex Capable */
92 #define MII_SR_100X_FD_CAPS      0x4000    /* 100X  Full Duplex Capable */
93 #define MII_SR_100T4_CAPS        0x8000    /* 100T4 Capable */
94 
95 /* eTSEC */
96 
97 /* Number of register in the device */
98 #define ETSEC_REG_NUMBER 1024
99 
100 typedef struct eTSEC_Register {
101     const char *name;
102     const char *desc;
103     uint32_t    access;
104     uint32_t    value;
105 } eTSEC_Register;
106 
107 typedef struct eTSEC {
108     SysBusDevice  busdev;
109 
110     MemoryRegion  io_area;
111 
112     eTSEC_Register regs[ETSEC_REG_NUMBER];
113 
114     NICState *nic;
115     NICConf   conf;
116 
117     /* Tx */
118 
119     uint8_t       *tx_buffer;
120     uint32_t       tx_buffer_len;
121     eTSEC_rxtx_bd  first_bd;
122 
123     /* Rx */
124 
125     uint8_t       *rx_buffer;
126     uint32_t       rx_buffer_len;
127     uint32_t       rx_remaining_data;
128     uint8_t        rx_first_in_frame;
129     uint8_t        rx_fcb_size;
130     eTSEC_rxtx_bd  rx_first_bd;
131     uint8_t        rx_fcb[10];
132     uint32_t       rx_padding;
133 
134     /* IRQs */
135     qemu_irq     tx_irq;
136     qemu_irq     rx_irq;
137     qemu_irq     err_irq;
138 
139 
140     uint16_t phy_status;
141     uint16_t phy_control;
142 
143     /* Polling */
144     struct ptimer_state *ptimer;
145 
146     /* Whether we should flush the rx queue when buffer becomes available. */
147     bool need_flush;
148 } eTSEC;
149 
150 #define TYPE_ETSEC_COMMON "eTSEC"
151 #define ETSEC_COMMON(obj) \
152      OBJECT_CHECK(eTSEC, (obj), TYPE_ETSEC_COMMON)
153 
154 #define eTSEC_TRANSMIT 1
155 #define eTSEC_RECEIVE  2
156 
157 DeviceState *etsec_create(hwaddr        base,
158                           MemoryRegion *mr,
159                           NICInfo      *nd,
160                           qemu_irq      tx_irq,
161                           qemu_irq      rx_irq,
162                           qemu_irq      err_irq);
163 
164 void etsec_update_irq(eTSEC *etsec);
165 
166 void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr);
167 void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr);
168 ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size);
169 
170 void etsec_write_miim(eTSEC          *etsec,
171                       eTSEC_Register *reg,
172                       uint32_t        reg_index,
173                       uint32_t        value);
174 
175 void etsec_miim_link_status(eTSEC *etsec, NetClientState *nc);
176 
177 #endif /* ETSEC_H */
178