xref: /qemu/hw/net/igb_regs.h (revision 651ccdfa)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * This is copied + edited from kernel header files in
4  * drivers/net/ethernet/intel/igb
5  */
6 
7 #ifndef HW_IGB_REGS_H_
8 #define HW_IGB_REGS_H_
9 
10 #include "e1000x_regs.h"
11 
12 /* from igb/e1000_hw.h */
13 
14 #define E1000_DEV_ID_82576                 0x10C9
15 #define E1000_DEV_ID_82576_FIBER           0x10E6
16 #define E1000_DEV_ID_82576_SERDES          0x10E7
17 #define E1000_DEV_ID_82576_QUAD_COPPER             0x10E8
18 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
19 #define E1000_DEV_ID_82576_NS                      0x150A
20 #define E1000_DEV_ID_82576_NS_SERDES               0x1518
21 #define E1000_DEV_ID_82576_SERDES_QUAD             0x150D
22 
23 /* Context Descriptor */
24 struct e1000_adv_tx_context_desc {
25     uint32_t vlan_macip_lens;
26     uint32_t seqnum_seed;
27     uint32_t type_tucmd_mlhl;
28     uint32_t mss_l4len_idx;
29 };
30 
31 /* Advanced Transmit Descriptor */
32 union e1000_adv_tx_desc {
33     struct {
34         uint64_t buffer_addr;     /* Address of descriptor's data buffer */
35         uint32_t cmd_type_len;
36         uint32_t olinfo_status;
37     } read;
38     struct {
39         uint64_t rsvd;            /* Reserved */
40         uint32_t nxtseq_seed;
41         uint32_t status;
42     } wb;
43 };
44 
45 #define E1000_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Descriptor */
46 #define E1000_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
47 #define E1000_ADVTXD_DCMD_DEXT  0x20000000 /* Descriptor Extension (1=Adv) */
48 #define E1000_ADVTXD_DCMD_TSE   0x80000000 /* TCP/UDP Segmentation Enable */
49 
50 #define E1000_ADVTXD_POTS_IXSM  0x00000100 /* Insert TCP/UDP Checksum */
51 #define E1000_ADVTXD_POTS_TXSM  0x00000200 /* Insert TCP/UDP Checksum */
52 
53 #define E1000_TXD_POPTS_IXSM 0x00000001 /* Insert IP checksum */
54 #define E1000_TXD_POPTS_TXSM 0x00000002 /* Insert TCP/UDP checksum */
55 
56 /* Receive Descriptor - Advanced */
57 union e1000_adv_rx_desc {
58     struct {
59         uint64_t pkt_addr;                /* Packet Buffer Address */
60         uint64_t hdr_addr;                /* Header Buffer Address */
61     } read;
62     struct {
63         struct {
64             struct {
65                 uint16_t pkt_info;        /* RSS Type, Packet Type */
66                 uint16_t hdr_info;        /* Split Head, Buffer Length */
67             } lo_dword;
68             union {
69                 uint32_t rss;             /* RSS Hash */
70                 struct {
71                         uint16_t ip_id;   /* IP Id */
72                         uint16_t csum;    /* Packet Checksum */
73                 } csum_ip;
74             } hi_dword;
75         } lower;
76         struct {
77             uint32_t status_error;        /* Ext Status/Error */
78             uint16_t length;              /* Packet Length */
79             uint16_t vlan;                /* VLAN tag */
80         } upper;
81     } wb;  /* writeback */
82 };
83 
84 /* from igb/e1000_phy.h */
85 
86 /* IGP01E1000 Specific Registers */
87 #define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
88 #define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
89 #define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
90 #define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
91 #define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
92 #define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
93 #define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
94 #define IGP01E1000_PHY_POLARITY_MASK      0x0078
95 #define IGP01E1000_PSCR_AUTO_MDIX         0x1000
96 #define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
97 #define IGP01E1000_PSCFR_SMART_SPEED      0x0080
98 
99 /* Enable flexible speed on link-up */
100 #define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
101 #define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
102 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
103 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
104 #define IGP01E1000_PSSR_MDIX              0x0800
105 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
106 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
107 #define IGP02E1000_PHY_CHANNEL_NUM        4
108 #define IGP02E1000_PHY_AGC_A              0x11B1
109 #define IGP02E1000_PHY_AGC_B              0x12B1
110 #define IGP02E1000_PHY_AGC_C              0x14B1
111 #define IGP02E1000_PHY_AGC_D              0x18B1
112 #define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
113 #define IGP02E1000_AGC_LENGTH_MASK        0x7F
114 #define IGP02E1000_AGC_RANGE              15
115 
116 /* from igb/igb.h */
117 
118 #define E1000_PCS_CFG_IGN_SD     1
119 
120 /* Interrupt defines */
121 #define IGB_START_ITR            648 /* ~6000 ints/sec */
122 #define IGB_4K_ITR               980
123 #define IGB_20K_ITR              196
124 #define IGB_70K_ITR              56
125 
126 /* TX/RX descriptor defines */
127 #define IGB_DEFAULT_TXD          256
128 #define IGB_DEFAULT_TX_WORK      128
129 #define IGB_MIN_TXD              80
130 #define IGB_MAX_TXD              4096
131 
132 #define IGB_DEFAULT_RXD          256
133 #define IGB_MIN_RXD              80
134 #define IGB_MAX_RXD              4096
135 
136 #define IGB_DEFAULT_ITR           3 /* dynamic */
137 #define IGB_MAX_ITR_USECS         10000
138 #define IGB_MIN_ITR_USECS         10
139 #define NON_Q_VECTORS             1
140 #define MAX_Q_VECTORS             8
141 #define MAX_MSIX_ENTRIES          10
142 
143 /* Transmit and receive queues */
144 #define IGB_MAX_RX_QUEUES          8
145 #define IGB_MAX_RX_QUEUES_82575    4
146 #define IGB_MAX_RX_QUEUES_I211     2
147 #define IGB_MAX_TX_QUEUES          8
148 #define IGB_MAX_VF_MC_ENTRIES      30
149 #define IGB_MAX_VF_FUNCTIONS       8
150 #define IGB_MAX_VFTA_ENTRIES       128
151 #define IGB_82576_VF_DEV_ID        0x10CA
152 #define IGB_I350_VF_DEV_ID         0x1520
153 
154 /* from igb/e1000_82575.h */
155 
156 #define E1000_MRQC_ENABLE_RSS_MQ            0x00000002
157 #define E1000_MRQC_ENABLE_VMDQ              0x00000003
158 #define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
159 #define E1000_MRQC_ENABLE_VMDQ_RSS_MQ       0x00000005
160 #define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
161 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
162 
163 /* Additional Receive Descriptor Control definitions */
164 #define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
165 
166 /* Direct Cache Access (DCA) definitions */
167 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
168 #define E1000_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */
169 
170 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
171 #define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
172 #define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
173 #define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
174 #define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
175 
176 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
177 #define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
178 #define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
179 #define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
180 #define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
181 
182 /* Additional DCA related definitions, note change in position of CPUID */
183 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
184 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
185 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
186 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
187 
188 #define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
189 #define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
190 #define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
191 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
192 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31)  /* global VF LB enable */
193 
194 /* Easy defines for setting default pool, would normally be left a zero */
195 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
196 #define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
197 
198 /* Other useful VMD_CTL register defines */
199 #define E1000_VT_CTL_IGNORE_MAC         BIT(28)
200 #define E1000_VT_CTL_DISABLE_DEF_POOL   BIT(29)
201 #define E1000_VT_CTL_VM_REPL_EN         BIT(30)
202 
203 /* Per VM Offload register setup */
204 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
205 #define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
206 #define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
207 #define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
208 #define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
209 #define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
210 #define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
211 #define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
212 #define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
213 #define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
214 
215 #define E1000_DVMOLR_HIDEVLAN  0x20000000 /* Hide vlan enable */
216 #define E1000_DVMOLR_STRVLAN   0x40000000 /* Vlan stripping enable */
217 #define E1000_DVMOLR_STRCRC    0x80000000 /* CRC stripping enable */
218 
219 #define E1000_VLVF_ARRAY_SIZE     32
220 #define E1000_VLVF_VLANID_MASK    0x00000FFF
221 #define E1000_VLVF_POOLSEL_SHIFT  12
222 #define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
223 #define E1000_VLVF_LVLAN          0x00100000
224 #define E1000_VLVF_VLANID_ENABLE  0x80000000
225 
226 #define E1000_VMVIR_VLANA_DEFAULT      0x40000000 /* Always use default VLAN */
227 #define E1000_VMVIR_VLANA_NEVER        0x80000000 /* Never insert VLAN tag */
228 
229 #define E1000_IOVCTL 0x05BBC
230 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
231 
232 #define E1000_RPLOLR_STRVLAN   0x40000000
233 #define E1000_RPLOLR_STRCRC    0x80000000
234 
235 #define E1000_DTXCTL_8023LL     0x0004
236 #define E1000_DTXCTL_VLAN_ADDED 0x0008
237 #define E1000_DTXCTL_OOS_ENABLE 0x0010
238 #define E1000_DTXCTL_MDP_EN     0x0020
239 #define E1000_DTXCTL_SPOOF_INT  0x0040
240 
241 /* from igb/e1000_defines.h */
242 
243 #define E1000_IVAR_VALID     0x80
244 #define E1000_GPIE_NSICR     0x00000001
245 #define E1000_GPIE_MSIX_MODE 0x00000010
246 #define E1000_GPIE_EIAME     0x40000000
247 #define E1000_GPIE_PBA       0x80000000
248 
249 /* Transmit Control */
250 #define E1000_TCTL_EN     0x00000002    /* enable tx */
251 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
252 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
253 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
254 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
255 
256 /* Collision related configuration parameters */
257 #define E1000_COLLISION_THRESHOLD       15
258 #define E1000_CT_SHIFT                  4
259 #define E1000_COLLISION_DISTANCE        63
260 #define E1000_COLD_SHIFT                12
261 
262 #define E1000_RAH_POOL_MASK 0x03FC0000
263 #define E1000_RAH_POOL_1 0x00040000
264 
265 #define E1000_ICR_VMMB         0x00000100 /* VM MB event */
266 #define E1000_ICR_TS           0x00080000 /* Time Sync Interrupt */
267 #define E1000_ICR_DRSTA        0x40000000 /* Device Reset Asserted */
268 /* If this bit asserted, the driver should claim the interrupt */
269 #define E1000_ICR_INT_ASSERTED 0x80000000
270 /* LAN connected device generates an interrupt */
271 #define E1000_ICR_DOUTSYNC     0x10000000 /* NIC DMA out of sync */
272 
273 /* Extended Interrupt Cause Read */
274 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
275 #define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
276 #define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
277 #define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
278 #define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
279 #define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
280 #define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
281 #define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
282 #define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
283 
284 /* Extended Interrupt Cause Set */
285 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
286 #define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */
287 
288 /* PCI Express Control */
289 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
290 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
291 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
292 #define E1000_GCR_CAP_VER2              0x00040000
293 
294 #define PHY_REVISION_MASK      0xFFFFFFF0
295 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
296 #define MAX_PHY_MULTI_PAGE_REG 0xF
297 
298 #define IGP03E1000_E_PHY_ID 0x02A80390
299 
300 /* from igb/e1000_mbox.h */
301 
302 #define E1000_P2VMAILBOX_STS  0x00000001 /* Initiate message send to VF */
303 #define E1000_P2VMAILBOX_ACK  0x00000002 /* Ack message recv'd from VF */
304 #define E1000_P2VMAILBOX_VFU  0x00000004 /* VF owns the mailbox buffer */
305 #define E1000_P2VMAILBOX_PFU  0x00000008 /* PF owns the mailbox buffer */
306 #define E1000_P2VMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */
307 
308 #define E1000_MBVFICR_VFREQ_MASK 0x000000FF /* bits for VF messages */
309 #define E1000_MBVFICR_VFREQ_VF1  0x00000001 /* bit for VF 1 message */
310 #define E1000_MBVFICR_VFACK_MASK 0x00FF0000 /* bits for VF acks */
311 #define E1000_MBVFICR_VFACK_VF1  0x00010000 /* bit for VF 1 ack */
312 
313 #define E1000_V2PMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
314 
315 /*
316  * If it's a E1000_VF_* msg then it originates in the VF and is sent to the
317  * PF.  The reverse is true if it is E1000_PF_*.
318  * Message ACK's are the value or'd with 0xF0000000
319  */
320 /* Messages below or'd with this are the ACK */
321 #define E1000_VT_MSGTYPE_ACK 0x80000000
322 /* Messages below or'd with this are the NACK */
323 #define E1000_VT_MSGTYPE_NACK 0x40000000
324 /* Indicates that VF is still clear to send requests */
325 #define E1000_VT_MSGTYPE_CTS 0x20000000
326 #define E1000_VT_MSGINFO_SHIFT 16
327 /* bits 23:16 are used for exra info for certain messages */
328 #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT)
329 
330 #define E1000_VF_RESET                 0x01 /* VF requests reset */
331 #define E1000_VF_SET_MAC_ADDR          0x02 /* VF requests to set MAC addr */
332 /* VF requests to clear all unicast MAC filters */
333 #define E1000_VF_MAC_FILTER_CLR        (0x01 << E1000_VT_MSGINFO_SHIFT)
334 /* VF requests to add unicast MAC filter */
335 #define E1000_VF_MAC_FILTER_ADD        (0x02 << E1000_VT_MSGINFO_SHIFT)
336 #define E1000_VF_SET_MULTICAST         0x03 /* VF requests to set MC addr */
337 #define E1000_VF_SET_VLAN              0x04 /* VF requests to set VLAN */
338 #define E1000_VF_SET_LPE               0x05 /* VF requests to set VMOLR.LPE */
339 #define E1000_VF_SET_PROMISC           0x06 /*VF requests to clear VMOLR.ROPE/MPME*/
340 #define E1000_VF_SET_PROMISC_MULTICAST (0x02 << E1000_VT_MSGINFO_SHIFT)
341 
342 #define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */
343 
344 /* from igb/e1000_regs.h */
345 
346 #define E1000_EICR      0x01580  /* Ext. Interrupt Cause Read - R/clr */
347 #define E1000_EITR(_n)  (0x01680 + (0x4 * (_n)))
348 #define E1000_EICS      0x01520  /* Ext. Interrupt Cause Set - W0 */
349 #define E1000_EIMS      0x01524  /* Ext. Interrupt Mask Set/Read - RW */
350 #define E1000_EIMC      0x01528  /* Ext. Interrupt Mask Clear - WO */
351 #define E1000_EIAC      0x0152C  /* Ext. Interrupt Auto Clear - RW */
352 #define E1000_EIAM      0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
353 #define E1000_GPIE      0x01514  /* General Purpose Interrupt Enable; RW */
354 #define E1000_IVAR0     0x01700  /* Interrupt Vector Allocation Register - RW */
355 #define E1000_IVAR_MISC 0x01740  /* Interrupt Vector Allocation Register (last) - RW */
356 #define E1000_FRTIMER   0x01048  /* Free Running Timer - RW */
357 #define E1000_FCRTV     0x02460  /* Flow Control Refresh Timer Value - RW */
358 
359 #define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40))
360 
361 #define E1000_RXPBS 0x02404  /* Rx Packet Buffer Size - RW */
362 #define E1000_TXPBS 0x03404  /* Tx Packet Buffer Size - RW */
363 
364 #define E1000_DTXCTL 0x03590  /* DMA TX Control - RW */
365 
366 #define E1000_HTCBDPC     0x04124  /* Host TX Circuit Breaker Dropped Count */
367 #define E1000_RLPML       0x05004  /* RX Long Packet Max Length */
368 #define E1000_RA2         0x054E0  /* 2nd half of Rx address array - RW Array */
369 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
370 #define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
371 
372 /* VT Registers */
373 #define E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */
374 #define E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */
375 #define E1000_VFLRE     0x00C88 /* VF Register Events - RWC */
376 #define E1000_VFRE      0x00C8C /* VF Receive Enables */
377 #define E1000_VFTE      0x00C90 /* VF Transmit Enables */
378 #define E1000_QDE       0x02408 /* Queue Drop Enable - RW */
379 #define E1000_DTXSWC    0x03500 /* DMA Tx Switch Control - RW */
380 #define E1000_WVBR      0x03554 /* VM Wrong Behavior - RWS */
381 #define E1000_RPLOLR    0x05AF0 /* Replication Offload - RW */
382 #define E1000_UTA       0x0A000 /* Unicast Table Array - RW */
383 #define E1000_IOVTCL    0x05BBC /* IOV Control Register */
384 #define E1000_TXSWC     0x05ACC /* Tx Switch Control */
385 #define E1000_LVMMC     0x03548 /* Last VM Misbehavior cause */
386 /* These act per VF so an array friendly macro is used */
387 #define E1000_P2VMAILBOX(_n)   (0x00C00 + (4 * (_n)))
388 #define E1000_VMBMEM(_n)       (0x00800 + (64 * (_n)))
389 #define E1000_VMOLR(_n)        (0x05AD0 + (4 * (_n)))
390 #define E1000_DVMOLR(_n)       (0x0C038 + (64 * (_n)))
391 #define E1000_VLVF(_n)         (0x05D00 + (4 * (_n))) /* VLAN VM Filter */
392 #define E1000_VMVIR(_n)        (0x03700 + (4 * (_n)))
393 
394 /* from igbvf/defines.h */
395 
396 /* SRRCTL bit definitions */
397 #define E1000_SRRCTL_BSIZEPKT_SHIFT            10 /* Shift _right_ */
398 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK         0x00000F00
399 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT        2  /* Shift _left_ */
400 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF       0x02000000
401 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
402 #define E1000_SRRCTL_DESCTYPE_MASK             0x0E000000
403 #define E1000_SRRCTL_DROP_EN                   0x80000000
404 
405 #define E1000_SRRCTL_BSIZEPKT_MASK             0x0000007F
406 #define E1000_SRRCTL_BSIZEHDR_MASK             0x00003F00
407 
408 /* from igbvf/mbox.h */
409 
410 #define E1000_V2PMAILBOX_REQ      0x00000001 /* Request for PF Ready bit */
411 #define E1000_V2PMAILBOX_ACK      0x00000002 /* Ack PF message received */
412 #define E1000_V2PMAILBOX_VFU      0x00000004 /* VF owns the mailbox buffer */
413 #define E1000_V2PMAILBOX_PFU      0x00000008 /* PF owns the mailbox buffer */
414 #define E1000_V2PMAILBOX_PFSTS    0x00000010 /* PF wrote a message in the MB */
415 #define E1000_V2PMAILBOX_PFACK    0x00000020 /* PF ack the previous VF msg */
416 #define E1000_V2PMAILBOX_RSTI     0x00000040 /* PF has reset indication */
417 #define E1000_V2PMAILBOX_RSTD     0x00000080 /* PF has indicated reset done */
418 #define E1000_V2PMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */
419 
420 #define E1000_VFMAILBOX_SIZE      16 /* 16 32 bit words - 64 bytes */
421 
422 /*
423  * If it's a E1000_VF_* msg then it originates in the VF and is sent to the
424  * PF.  The reverse is true if it is E1000_PF_*.
425  * Message ACK's are the value or'd with 0xF0000000
426  */
427 /* Messages below or'd with this are the ACK */
428 #define E1000_VT_MSGTYPE_ACK      0x80000000
429 /* Messages below or'd with this are the NACK */
430 #define E1000_VT_MSGTYPE_NACK     0x40000000
431 /* Indicates that VF is still clear to send requests */
432 #define E1000_VT_MSGTYPE_CTS      0x20000000
433 
434 /* We have a total wait time of 1s for vf mailbox posted messages */
435 #define E1000_VF_MBX_INIT_TIMEOUT 2000 /* retry count for mbx timeout */
436 #define E1000_VF_MBX_INIT_DELAY   500  /* usec delay between retries */
437 
438 #define E1000_VT_MSGINFO_SHIFT    16
439 /* bits 23:16 are used for exra info for certain messages */
440 #define E1000_VT_MSGINFO_MASK     (0xFF << E1000_VT_MSGINFO_SHIFT)
441 
442 #define E1000_VF_RESET            0x01 /* VF requests reset */
443 #define E1000_VF_SET_MAC_ADDR     0x02 /* VF requests PF to set MAC addr */
444 /* VF requests PF to clear all unicast MAC filters */
445 #define E1000_VF_MAC_FILTER_CLR   (0x01 << E1000_VT_MSGINFO_SHIFT)
446 /* VF requests PF to add unicast MAC filter */
447 #define E1000_VF_MAC_FILTER_ADD   (0x02 << E1000_VT_MSGINFO_SHIFT)
448 #define E1000_VF_SET_MULTICAST    0x03 /* VF requests PF to set MC addr */
449 #define E1000_VF_SET_VLAN         0x04 /* VF requests PF to set VLAN */
450 #define E1000_VF_SET_LPE          0x05 /* VF requests PF to set VMOLR.LPE */
451 
452 #define E1000_PF_CONTROL_MSG      0x0100 /* PF control message */
453 
454 /* from igbvf/regs.h */
455 
456 /* Statistics registers */
457 #define E1000_VFGPRC   0x00F10
458 #define E1000_VFGORC   0x00F18
459 #define E1000_VFMPRC   0x00F3C
460 #define E1000_VFGPTC   0x00F14
461 #define E1000_VFGOTC   0x00F34
462 #define E1000_VFGOTLBC 0x00F50
463 #define E1000_VFGPTLBC 0x00F44
464 #define E1000_VFGORLBC 0x00F48
465 #define E1000_VFGPRLBC 0x00F40
466 
467 /* These act per VF so an array friendly macro is used */
468 #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
469 #define E1000_VMBMEM(_n)     (0x00800 + (64 * (_n)))
470 
471 /* from igbvf/vf.h */
472 
473 #define E1000_DEV_ID_82576_VF 0x10CA
474 
475 /* new */
476 
477 /* Receive Registers */
478 
479 /* RX Descriptor Base Low; RW */
480 #define E1000_RDBAL(_n)    (0x0C000 + (0x40  * (_n)))
481 #define E1000_RDBAL_A(_n)  (0x02800 + (0x100 * (_n)))
482 
483 /* RX Descriptor Base High; RW */
484 #define E1000_RDBAH(_n)    (0x0C004 + (0x40  * (_n)))
485 #define E1000_RDBAH_A(_n)  (0x02804 + (0x100 * (_n)))
486 
487 /* RX Descriptor Ring Length; RW */
488 #define E1000_RDLEN(_n)    (0x0C008 + (0x40  * (_n)))
489 #define E1000_RDLEN_A(_n)  (0x02808 + (0x100 * (_n)))
490 
491 /* Split and Replication Receive Control; RW */
492 #define E1000_SRRCTL(_n)   (0x0C00C + (0x40  * (_n)))
493 #define E1000_SRRCTL_A(_n) (0x0280C + (0x100 * (_n)))
494 
495 /* RX Descriptor Head; RW */
496 #define E1000_RDH(_n)      (0x0C010 + (0x40  * (_n)))
497 #define E1000_RDH_A(_n)    (0x02810 + (0x100 * (_n)))
498 
499 /* RX DCA Control; RW */
500 #define E1000_RXCTL(_n)    (0x0C014 + (0x40  * (_n)))
501 #define E1000_RXCTL_A(_n)  (0x02814 + (0x100 * (_n)))
502 
503 /* RX Descriptor Tail; RW */
504 #define E1000_RDT(_n)      (0x0C018 + (0x40  * (_n)))
505 #define E1000_RDT_A(_n)    (0x02818 + (0x100 * (_n)))
506 
507 /* RX Descriptor Control; RW */
508 #define E1000_RXDCTL(_n)   (0x0C028 + (0x40  * (_n)))
509 #define E1000_RXDCTL_A(_n) (0x02828 + (0x100 * (_n)))
510 
511 /* RX Queue Drop Packet Count; RC */
512 #define E1000_RQDPC_A(_n)  (0x02830 + (0x100 * (_n)))
513 
514 /* Transmit Registers */
515 
516 /* TX Descriptor Base Low; RW */
517 #define E1000_TDBAL(_n)    (0x0E000 + (0x40  * (_n)))
518 #define E1000_TDBAL_A(_n)  (0x03800 + (0x100 * (_n)))
519 
520 /* TX Descriptor Base High; RW */
521 #define E1000_TDBAH(_n)    (0x0E004 + (0x40  * (_n)))
522 #define E1000_TDBAH_A(_n)  (0x03804 + (0x100 * (_n)))
523 
524 /* TX Descriptor Ring Length; RW */
525 #define E1000_TDLEN(_n)    (0x0E008 + (0x40  * (_n)))
526 #define E1000_TDLEN_A(_n)  (0x03808 + (0x100 * (_n)))
527 
528 /* TX Descriptor Head; RW */
529 #define E1000_TDH(_n)      (0x0E010 + (0x40  * (_n)))
530 #define E1000_TDH_A(_n)    (0x03810 + (0x100 * (_n)))
531 
532 /* TX DCA Control; RW */
533 #define E1000_TXCTL(_n)    (0x0E014 + (0x40  * (_n)))
534 #define E1000_TXCTL_A(_n)  (0x03814 + (0x100 * (_n)))
535 
536 /* TX Descriptor Tail; RW */
537 #define E1000_TDT(_n)      (0x0E018 + (0x40  * (_n)))
538 #define E1000_TDT_A(_n)    (0x03818 + (0x100 * (_n)))
539 
540 /* TX Descriptor Control; RW */
541 #define E1000_TXDCTL(_n)   (0x0E028 + (0x40  * (_n)))
542 #define E1000_TXDCTL_A(_n) (0x03828 + (0x100 * (_n)))
543 
544 /* TX Descriptor Completion Write–Back Address Low; RW */
545 #define E1000_TDWBAL(_n)   (0x0E038 + (0x40  * (_n)))
546 #define E1000_TDWBAL_A(_n) (0x03838 + (0x100 * (_n)))
547 
548 /* TX Descriptor Completion Write–Back Address High; RW */
549 #define E1000_TDWBAH(_n)   (0x0E03C + (0x40  * (_n)))
550 #define E1000_TDWBAH_A(_n) (0x0383C + (0x100 * (_n)))
551 
552 #define E1000_MTA_A        0x0200
553 
554 #define E1000_XDBAL_MASK (~(BIT(5) - 1)) /* TDBAL and RDBAL Registers Mask */
555 
556 #define E1000_ICR_MACSEC   0x00000020 /* MACSec */
557 #define E1000_ICR_RX0      0x00000040 /* Receiver Overrun */
558 #define E1000_ICR_GPI_SDP0 0x00000800 /* General Purpose, SDP0 pin */
559 #define E1000_ICR_GPI_SDP1 0x00001000 /* General Purpose, SDP1 pin */
560 #define E1000_ICR_GPI_SDP2 0x00002000 /* General Purpose, SDP2 pin */
561 #define E1000_ICR_GPI_SDP3 0x00004000 /* General Purpose, SDP3 pin */
562 #define E1000_ICR_PTRAP    0x00008000 /* Probe Trap */
563 #define E1000_ICR_MNG      0x00040000 /* Management Event */
564 #define E1000_ICR_OMED     0x00100000 /* Other Media Energy Detected */
565 #define E1000_ICR_FER      0x00400000 /* Fatal Error */
566 #define E1000_ICR_NFER     0x00800000 /* Non Fatal Error */
567 #define E1000_ICR_CSRTO    0x01000000 /* CSR access Time Out Indication */
568 #define E1000_ICR_SCE      0x02000000 /* Storm Control Event */
569 #define E1000_ICR_SW_WD    0x04000000 /* Software Watchdog */
570 
571 /* Extended Interrupts */
572 
573 #define E1000_EICR_MSIX_MASK   0x01FFFFFF /* Bits used in MSI-X mode */
574 #define E1000_EICR_LEGACY_MASK 0x4000FFFF /* Bits used in non MSI-X mode */
575 
576 /* Mirror VF Control (only RST bit); RW */
577 #define E1000_PVTCTRL(_n) (0x10000 + (_n) * 0x100)
578 
579 /* Mirror Good Packets Received Count; RO */
580 #define E1000_PVFGPRC(_n) (0x10010 + (_n) * 0x100)
581 
582 /* Mirror Good Packets Transmitted Count; RO */
583 #define E1000_PVFGPTC(_n) (0x10014 + (_n) * 0x100)
584 
585 /* Mirror Good Octets Received Count; RO */
586 #define E1000_PVFGORC(_n) (0x10018 + (_n) * 0x100)
587 
588 /* Mirror Extended Interrupt Cause Set; WO */
589 #define E1000_PVTEICS(_n) (0x10020 + (_n) * 0x100)
590 
591 /* Mirror Extended Interrupt Mask Set/Read; RW */
592 #define E1000_PVTEIMS(_n) (0x10024 + (_n) * 0x100)
593 
594 /* Mirror Extended Interrupt Mask Clear; WO */
595 #define E1000_PVTEIMC(_n) (0x10028 + (_n) * 0x100)
596 
597 /* Mirror Extended Interrupt Auto Clear; RW */
598 #define E1000_PVTEIAC(_n) (0x1002C + (_n) * 0x100)
599 
600 /* Mirror Extended Interrupt Auto Mask Enable; RW */
601 #define E1000_PVTEIAM(_n) (0x10030 + (_n) * 0x100)
602 
603 /* Mirror Good Octets Transmitted Count; RO */
604 #define E1000_PVFGOTC(_n) (0x10034 + (_n) * 0x100)
605 
606 /* Mirror Multicast Packets Received Count; RO */
607 #define E1000_PVFMPRC(_n) (0x1003C + (_n) * 0x100)
608 
609 /* Mirror Good RX Packets loopback Count; RO */
610 #define E1000_PVFGPRLBC(_n) (0x10040 + (_n) * 0x100)
611 
612 /* Mirror Good TX packets loopback Count; RO */
613 #define E1000_PVFGPTLBC(_n) (0x10044 + (_n) * 0x100)
614 
615 /* Mirror Good RX Octets loopback Count; RO */
616 #define E1000_PVFGORLBC(_n) (0x10048 + (_n) * 0x100)
617 
618 /* Mirror Good TX Octets loopback Count; RO */
619 #define E1000_PVFGOTLBC(_n) (0x10050 + (_n) * 0x100)
620 
621 /* Mirror Extended Interrupt Cause Set; RC/W1C */
622 #define E1000_PVTEICR(_n) (0x10080 + (_n) * 0x100)
623 
624 /*
625  * These are fake addresses that, according to the specification, the device
626  * is not using. They are used to distinguish between the PF and the VFs
627  * accessing their VTIVAR register (which is the same address, 0x1700)
628  */
629 #define E1000_VTIVAR      0x11700
630 #define E1000_VTIVAR_MISC 0x11720
631 
632 #define E1000_RSS_QUEUE(reta, hash) (E1000_RETA_VAL(reta, hash) & 0x0F)
633 
634 #define E1000_STATUS_IOV_MODE 0x00040000
635 
636 #define E1000_STATUS_NUM_VFS_SHIFT 14
637 
638 static inline uint8_t igb_ivar_entry_rx(uint8_t i)
639 {
640     return i < 8 ? i * 4 : (i - 8) * 4 + 2;
641 }
642 
643 static inline uint8_t igb_ivar_entry_tx(uint8_t i)
644 {
645     return i < 8 ? i * 4 + 1 : (i - 8) * 4 + 3;
646 }
647 
648 #endif
649