1 /* 2 * QEMU NE2000 emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "net/net.h" 27 #include "ne2000.h" 28 #include "hw/loader.h" 29 #include "sysemu/sysemu.h" 30 31 /* debug NE2000 card */ 32 //#define DEBUG_NE2000 33 34 #define MAX_ETH_FRAME_SIZE 1514 35 36 #define E8390_CMD 0x00 /* The command register (for all pages) */ 37 /* Page 0 register offsets. */ 38 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ 39 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ 40 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ 41 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ 42 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ 43 #define EN0_TSR 0x04 /* Transmit status reg RD */ 44 #define EN0_TPSR 0x04 /* Transmit starting page WR */ 45 #define EN0_NCR 0x05 /* Number of collision reg RD */ 46 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ 47 #define EN0_FIFO 0x06 /* FIFO RD */ 48 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ 49 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ 50 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ 51 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ 52 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ 53 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ 54 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ 55 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ 56 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ 57 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ 58 #define EN0_RSR 0x0c /* rx status reg RD */ 59 #define EN0_RXCR 0x0c /* RX configuration reg WR */ 60 #define EN0_TXCR 0x0d /* TX configuration reg WR */ 61 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ 62 #define EN0_DCFG 0x0e /* Data configuration reg WR */ 63 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ 64 #define EN0_IMR 0x0f /* Interrupt mask reg WR */ 65 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ 66 67 #define EN1_PHYS 0x11 68 #define EN1_CURPAG 0x17 69 #define EN1_MULT 0x18 70 71 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ 72 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ 73 74 #define EN3_CONFIG0 0x33 75 #define EN3_CONFIG1 0x34 76 #define EN3_CONFIG2 0x35 77 #define EN3_CONFIG3 0x36 78 79 /* Register accessed at EN_CMD, the 8390 base addr. */ 80 #define E8390_STOP 0x01 /* Stop and reset the chip */ 81 #define E8390_START 0x02 /* Start the chip, clear reset */ 82 #define E8390_TRANS 0x04 /* Transmit a frame */ 83 #define E8390_RREAD 0x08 /* Remote read */ 84 #define E8390_RWRITE 0x10 /* Remote write */ 85 #define E8390_NODMA 0x20 /* Remote DMA */ 86 #define E8390_PAGE0 0x00 /* Select page chip registers */ 87 #define E8390_PAGE1 0x40 /* using the two high-order bits */ 88 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ 89 90 /* Bits in EN0_ISR - Interrupt status register */ 91 #define ENISR_RX 0x01 /* Receiver, no error */ 92 #define ENISR_TX 0x02 /* Transmitter, no error */ 93 #define ENISR_RX_ERR 0x04 /* Receiver, with error */ 94 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ 95 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ 96 #define ENISR_COUNTERS 0x20 /* Counters need emptying */ 97 #define ENISR_RDC 0x40 /* remote dma complete */ 98 #define ENISR_RESET 0x80 /* Reset completed */ 99 #define ENISR_ALL 0x3f /* Interrupts we will enable */ 100 101 /* Bits in received packet status byte and EN0_RSR*/ 102 #define ENRSR_RXOK 0x01 /* Received a good packet */ 103 #define ENRSR_CRC 0x02 /* CRC error */ 104 #define ENRSR_FAE 0x04 /* frame alignment error */ 105 #define ENRSR_FO 0x08 /* FIFO overrun */ 106 #define ENRSR_MPA 0x10 /* missed pkt */ 107 #define ENRSR_PHY 0x20 /* physical/multicast address */ 108 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ 109 #define ENRSR_DEF 0x80 /* deferring */ 110 111 /* Transmitted packet status, EN0_TSR. */ 112 #define ENTSR_PTX 0x01 /* Packet transmitted without error */ 113 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ 114 #define ENTSR_COL 0x04 /* The transmit collided at least once. */ 115 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ 116 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ 117 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ 118 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ 119 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ 120 121 typedef struct PCINE2000State { 122 PCIDevice dev; 123 NE2000State ne2000; 124 } PCINE2000State; 125 126 void ne2000_reset(NE2000State *s) 127 { 128 int i; 129 130 s->isr = ENISR_RESET; 131 memcpy(s->mem, &s->c.macaddr, 6); 132 s->mem[14] = 0x57; 133 s->mem[15] = 0x57; 134 135 /* duplicate prom data */ 136 for(i = 15;i >= 0; i--) { 137 s->mem[2 * i] = s->mem[i]; 138 s->mem[2 * i + 1] = s->mem[i]; 139 } 140 } 141 142 static void ne2000_update_irq(NE2000State *s) 143 { 144 int isr; 145 isr = (s->isr & s->imr) & 0x7f; 146 #if defined(DEBUG_NE2000) 147 printf("NE2000: Set IRQ to %d (%02x %02x)\n", 148 isr ? 1 : 0, s->isr, s->imr); 149 #endif 150 qemu_set_irq(s->irq, (isr != 0)); 151 } 152 153 static int ne2000_buffer_full(NE2000State *s) 154 { 155 int avail, index, boundary; 156 157 index = s->curpag << 8; 158 boundary = s->boundary << 8; 159 if (index < boundary) 160 avail = boundary - index; 161 else 162 avail = (s->stop - s->start) - (index - boundary); 163 if (avail < (MAX_ETH_FRAME_SIZE + 4)) 164 return 1; 165 return 0; 166 } 167 168 int ne2000_can_receive(NetClientState *nc) 169 { 170 NE2000State *s = qemu_get_nic_opaque(nc); 171 172 if (s->cmd & E8390_STOP) 173 return 1; 174 return !ne2000_buffer_full(s); 175 } 176 177 #define MIN_BUF_SIZE 60 178 179 ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_) 180 { 181 NE2000State *s = qemu_get_nic_opaque(nc); 182 int size = size_; 183 uint8_t *p; 184 unsigned int total_len, next, avail, len, index, mcast_idx; 185 uint8_t buf1[60]; 186 static const uint8_t broadcast_macaddr[6] = 187 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 188 189 #if defined(DEBUG_NE2000) 190 printf("NE2000: received len=%d\n", size); 191 #endif 192 193 if (s->cmd & E8390_STOP || ne2000_buffer_full(s)) 194 return -1; 195 196 /* XXX: check this */ 197 if (s->rxcr & 0x10) { 198 /* promiscuous: receive all */ 199 } else { 200 if (!memcmp(buf, broadcast_macaddr, 6)) { 201 /* broadcast address */ 202 if (!(s->rxcr & 0x04)) 203 return size; 204 } else if (buf[0] & 0x01) { 205 /* multicast */ 206 if (!(s->rxcr & 0x08)) 207 return size; 208 mcast_idx = compute_mcast_idx(buf); 209 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 210 return size; 211 } else if (s->mem[0] == buf[0] && 212 s->mem[2] == buf[1] && 213 s->mem[4] == buf[2] && 214 s->mem[6] == buf[3] && 215 s->mem[8] == buf[4] && 216 s->mem[10] == buf[5]) { 217 /* match */ 218 } else { 219 return size; 220 } 221 } 222 223 224 /* if too small buffer, then expand it */ 225 if (size < MIN_BUF_SIZE) { 226 memcpy(buf1, buf, size); 227 memset(buf1 + size, 0, MIN_BUF_SIZE - size); 228 buf = buf1; 229 size = MIN_BUF_SIZE; 230 } 231 232 index = s->curpag << 8; 233 /* 4 bytes for header */ 234 total_len = size + 4; 235 /* address for next packet (4 bytes for CRC) */ 236 next = index + ((total_len + 4 + 255) & ~0xff); 237 if (next >= s->stop) 238 next -= (s->stop - s->start); 239 /* prepare packet header */ 240 p = s->mem + index; 241 s->rsr = ENRSR_RXOK; /* receive status */ 242 /* XXX: check this */ 243 if (buf[0] & 0x01) 244 s->rsr |= ENRSR_PHY; 245 p[0] = s->rsr; 246 p[1] = next >> 8; 247 p[2] = total_len; 248 p[3] = total_len >> 8; 249 index += 4; 250 251 /* write packet data */ 252 while (size > 0) { 253 if (index <= s->stop) 254 avail = s->stop - index; 255 else 256 avail = 0; 257 len = size; 258 if (len > avail) 259 len = avail; 260 memcpy(s->mem + index, buf, len); 261 buf += len; 262 index += len; 263 if (index == s->stop) 264 index = s->start; 265 size -= len; 266 } 267 s->curpag = next >> 8; 268 269 /* now we can signal we have received something */ 270 s->isr |= ENISR_RX; 271 ne2000_update_irq(s); 272 273 return size_; 274 } 275 276 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) 277 { 278 NE2000State *s = opaque; 279 int offset, page, index; 280 281 addr &= 0xf; 282 #ifdef DEBUG_NE2000 283 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val); 284 #endif 285 if (addr == E8390_CMD) { 286 /* control register */ 287 s->cmd = val; 288 if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ 289 s->isr &= ~ENISR_RESET; 290 /* test specific case: zero length transfer */ 291 if ((val & (E8390_RREAD | E8390_RWRITE)) && 292 s->rcnt == 0) { 293 s->isr |= ENISR_RDC; 294 ne2000_update_irq(s); 295 } 296 if (val & E8390_TRANS) { 297 index = (s->tpsr << 8); 298 /* XXX: next 2 lines are a hack to make netware 3.11 work */ 299 if (index >= NE2000_PMEM_END) 300 index -= NE2000_PMEM_SIZE; 301 /* fail safe: check range on the transmitted length */ 302 if (index + s->tcnt <= NE2000_PMEM_END) { 303 qemu_send_packet(qemu_get_queue(s->nic), s->mem + index, 304 s->tcnt); 305 } 306 /* signal end of transfer */ 307 s->tsr = ENTSR_PTX; 308 s->isr |= ENISR_TX; 309 s->cmd &= ~E8390_TRANS; 310 ne2000_update_irq(s); 311 } 312 } 313 } else { 314 page = s->cmd >> 6; 315 offset = addr | (page << 4); 316 switch(offset) { 317 case EN0_STARTPG: 318 s->start = val << 8; 319 break; 320 case EN0_STOPPG: 321 s->stop = val << 8; 322 break; 323 case EN0_BOUNDARY: 324 s->boundary = val; 325 break; 326 case EN0_IMR: 327 s->imr = val; 328 ne2000_update_irq(s); 329 break; 330 case EN0_TPSR: 331 s->tpsr = val; 332 break; 333 case EN0_TCNTLO: 334 s->tcnt = (s->tcnt & 0xff00) | val; 335 break; 336 case EN0_TCNTHI: 337 s->tcnt = (s->tcnt & 0x00ff) | (val << 8); 338 break; 339 case EN0_RSARLO: 340 s->rsar = (s->rsar & 0xff00) | val; 341 break; 342 case EN0_RSARHI: 343 s->rsar = (s->rsar & 0x00ff) | (val << 8); 344 break; 345 case EN0_RCNTLO: 346 s->rcnt = (s->rcnt & 0xff00) | val; 347 break; 348 case EN0_RCNTHI: 349 s->rcnt = (s->rcnt & 0x00ff) | (val << 8); 350 break; 351 case EN0_RXCR: 352 s->rxcr = val; 353 break; 354 case EN0_DCFG: 355 s->dcfg = val; 356 break; 357 case EN0_ISR: 358 s->isr &= ~(val & 0x7f); 359 ne2000_update_irq(s); 360 break; 361 case EN1_PHYS ... EN1_PHYS + 5: 362 s->phys[offset - EN1_PHYS] = val; 363 break; 364 case EN1_CURPAG: 365 s->curpag = val; 366 break; 367 case EN1_MULT ... EN1_MULT + 7: 368 s->mult[offset - EN1_MULT] = val; 369 break; 370 } 371 } 372 } 373 374 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) 375 { 376 NE2000State *s = opaque; 377 int offset, page, ret; 378 379 addr &= 0xf; 380 if (addr == E8390_CMD) { 381 ret = s->cmd; 382 } else { 383 page = s->cmd >> 6; 384 offset = addr | (page << 4); 385 switch(offset) { 386 case EN0_TSR: 387 ret = s->tsr; 388 break; 389 case EN0_BOUNDARY: 390 ret = s->boundary; 391 break; 392 case EN0_ISR: 393 ret = s->isr; 394 break; 395 case EN0_RSARLO: 396 ret = s->rsar & 0x00ff; 397 break; 398 case EN0_RSARHI: 399 ret = s->rsar >> 8; 400 break; 401 case EN1_PHYS ... EN1_PHYS + 5: 402 ret = s->phys[offset - EN1_PHYS]; 403 break; 404 case EN1_CURPAG: 405 ret = s->curpag; 406 break; 407 case EN1_MULT ... EN1_MULT + 7: 408 ret = s->mult[offset - EN1_MULT]; 409 break; 410 case EN0_RSR: 411 ret = s->rsr; 412 break; 413 case EN2_STARTPG: 414 ret = s->start >> 8; 415 break; 416 case EN2_STOPPG: 417 ret = s->stop >> 8; 418 break; 419 case EN0_RTL8029ID0: 420 ret = 0x50; 421 break; 422 case EN0_RTL8029ID1: 423 ret = 0x43; 424 break; 425 case EN3_CONFIG0: 426 ret = 0; /* 10baseT media */ 427 break; 428 case EN3_CONFIG2: 429 ret = 0x40; /* 10baseT active */ 430 break; 431 case EN3_CONFIG3: 432 ret = 0x40; /* Full duplex */ 433 break; 434 default: 435 ret = 0x00; 436 break; 437 } 438 } 439 #ifdef DEBUG_NE2000 440 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret); 441 #endif 442 return ret; 443 } 444 445 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, 446 uint32_t val) 447 { 448 if (addr < 32 || 449 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 450 s->mem[addr] = val; 451 } 452 } 453 454 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, 455 uint32_t val) 456 { 457 addr &= ~1; /* XXX: check exact behaviour if not even */ 458 if (addr < 32 || 459 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 460 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); 461 } 462 } 463 464 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, 465 uint32_t val) 466 { 467 addr &= ~1; /* XXX: check exact behaviour if not even */ 468 if (addr < 32 || 469 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 470 stl_le_p(s->mem + addr, val); 471 } 472 } 473 474 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) 475 { 476 if (addr < 32 || 477 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 478 return s->mem[addr]; 479 } else { 480 return 0xff; 481 } 482 } 483 484 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) 485 { 486 addr &= ~1; /* XXX: check exact behaviour if not even */ 487 if (addr < 32 || 488 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 489 return le16_to_cpu(*(uint16_t *)(s->mem + addr)); 490 } else { 491 return 0xffff; 492 } 493 } 494 495 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) 496 { 497 addr &= ~1; /* XXX: check exact behaviour if not even */ 498 if (addr < 32 || 499 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 500 return ldl_le_p(s->mem + addr); 501 } else { 502 return 0xffffffff; 503 } 504 } 505 506 static inline void ne2000_dma_update(NE2000State *s, int len) 507 { 508 s->rsar += len; 509 /* wrap */ 510 /* XXX: check what to do if rsar > stop */ 511 if (s->rsar == s->stop) 512 s->rsar = s->start; 513 514 if (s->rcnt <= len) { 515 s->rcnt = 0; 516 /* signal end of transfer */ 517 s->isr |= ENISR_RDC; 518 ne2000_update_irq(s); 519 } else { 520 s->rcnt -= len; 521 } 522 } 523 524 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) 525 { 526 NE2000State *s = opaque; 527 528 #ifdef DEBUG_NE2000 529 printf("NE2000: asic write val=0x%04x\n", val); 530 #endif 531 if (s->rcnt == 0) 532 return; 533 if (s->dcfg & 0x01) { 534 /* 16 bit access */ 535 ne2000_mem_writew(s, s->rsar, val); 536 ne2000_dma_update(s, 2); 537 } else { 538 /* 8 bit access */ 539 ne2000_mem_writeb(s, s->rsar, val); 540 ne2000_dma_update(s, 1); 541 } 542 } 543 544 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) 545 { 546 NE2000State *s = opaque; 547 int ret; 548 549 if (s->dcfg & 0x01) { 550 /* 16 bit access */ 551 ret = ne2000_mem_readw(s, s->rsar); 552 ne2000_dma_update(s, 2); 553 } else { 554 /* 8 bit access */ 555 ret = ne2000_mem_readb(s, s->rsar); 556 ne2000_dma_update(s, 1); 557 } 558 #ifdef DEBUG_NE2000 559 printf("NE2000: asic read val=0x%04x\n", ret); 560 #endif 561 return ret; 562 } 563 564 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 565 { 566 NE2000State *s = opaque; 567 568 #ifdef DEBUG_NE2000 569 printf("NE2000: asic writel val=0x%04x\n", val); 570 #endif 571 if (s->rcnt == 0) 572 return; 573 /* 32 bit access */ 574 ne2000_mem_writel(s, s->rsar, val); 575 ne2000_dma_update(s, 4); 576 } 577 578 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) 579 { 580 NE2000State *s = opaque; 581 int ret; 582 583 /* 32 bit access */ 584 ret = ne2000_mem_readl(s, s->rsar); 585 ne2000_dma_update(s, 4); 586 #ifdef DEBUG_NE2000 587 printf("NE2000: asic readl val=0x%04x\n", ret); 588 #endif 589 return ret; 590 } 591 592 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) 593 { 594 /* nothing to do (end of reset pulse) */ 595 } 596 597 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) 598 { 599 NE2000State *s = opaque; 600 ne2000_reset(s); 601 return 0; 602 } 603 604 static int ne2000_post_load(void* opaque, int version_id) 605 { 606 NE2000State* s = opaque; 607 608 if (version_id < 2) { 609 s->rxcr = 0x0c; 610 } 611 return 0; 612 } 613 614 const VMStateDescription vmstate_ne2000 = { 615 .name = "ne2000", 616 .version_id = 2, 617 .minimum_version_id = 0, 618 .post_load = ne2000_post_load, 619 .fields = (VMStateField[]) { 620 VMSTATE_UINT8_V(rxcr, NE2000State, 2), 621 VMSTATE_UINT8(cmd, NE2000State), 622 VMSTATE_UINT32(start, NE2000State), 623 VMSTATE_UINT32(stop, NE2000State), 624 VMSTATE_UINT8(boundary, NE2000State), 625 VMSTATE_UINT8(tsr, NE2000State), 626 VMSTATE_UINT8(tpsr, NE2000State), 627 VMSTATE_UINT16(tcnt, NE2000State), 628 VMSTATE_UINT16(rcnt, NE2000State), 629 VMSTATE_UINT32(rsar, NE2000State), 630 VMSTATE_UINT8(rsr, NE2000State), 631 VMSTATE_UINT8(isr, NE2000State), 632 VMSTATE_UINT8(dcfg, NE2000State), 633 VMSTATE_UINT8(imr, NE2000State), 634 VMSTATE_BUFFER(phys, NE2000State), 635 VMSTATE_UINT8(curpag, NE2000State), 636 VMSTATE_BUFFER(mult, NE2000State), 637 VMSTATE_UNUSED(4), /* was irq */ 638 VMSTATE_BUFFER(mem, NE2000State), 639 VMSTATE_END_OF_LIST() 640 } 641 }; 642 643 static const VMStateDescription vmstate_pci_ne2000 = { 644 .name = "ne2000", 645 .version_id = 3, 646 .minimum_version_id = 3, 647 .fields = (VMStateField[]) { 648 VMSTATE_PCI_DEVICE(dev, PCINE2000State), 649 VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State), 650 VMSTATE_END_OF_LIST() 651 } 652 }; 653 654 static uint64_t ne2000_read(void *opaque, hwaddr addr, 655 unsigned size) 656 { 657 NE2000State *s = opaque; 658 659 if (addr < 0x10 && size == 1) { 660 return ne2000_ioport_read(s, addr); 661 } else if (addr == 0x10) { 662 if (size <= 2) { 663 return ne2000_asic_ioport_read(s, addr); 664 } else { 665 return ne2000_asic_ioport_readl(s, addr); 666 } 667 } else if (addr == 0x1f && size == 1) { 668 return ne2000_reset_ioport_read(s, addr); 669 } 670 return ((uint64_t)1 << (size * 8)) - 1; 671 } 672 673 static void ne2000_write(void *opaque, hwaddr addr, 674 uint64_t data, unsigned size) 675 { 676 NE2000State *s = opaque; 677 678 if (addr < 0x10 && size == 1) { 679 ne2000_ioport_write(s, addr, data); 680 } else if (addr == 0x10) { 681 if (size <= 2) { 682 ne2000_asic_ioport_write(s, addr, data); 683 } else { 684 ne2000_asic_ioport_writel(s, addr, data); 685 } 686 } else if (addr == 0x1f && size == 1) { 687 ne2000_reset_ioport_write(s, addr, data); 688 } 689 } 690 691 static const MemoryRegionOps ne2000_ops = { 692 .read = ne2000_read, 693 .write = ne2000_write, 694 .endianness = DEVICE_LITTLE_ENDIAN, 695 }; 696 697 /***********************************************************/ 698 /* PCI NE2000 definitions */ 699 700 void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size) 701 { 702 memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size); 703 } 704 705 static void ne2000_cleanup(NetClientState *nc) 706 { 707 NE2000State *s = qemu_get_nic_opaque(nc); 708 709 s->nic = NULL; 710 } 711 712 static NetClientInfo net_ne2000_info = { 713 .type = NET_CLIENT_OPTIONS_KIND_NIC, 714 .size = sizeof(NICState), 715 .can_receive = ne2000_can_receive, 716 .receive = ne2000_receive, 717 .cleanup = ne2000_cleanup, 718 }; 719 720 static int pci_ne2000_init(PCIDevice *pci_dev) 721 { 722 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); 723 NE2000State *s; 724 uint8_t *pci_conf; 725 726 pci_conf = d->dev.config; 727 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 728 729 s = &d->ne2000; 730 ne2000_setup_io(s, DEVICE(pci_dev), 0x100); 731 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 732 s->irq = pci_allocate_irq(&d->dev); 733 734 qemu_macaddr_default_if_unset(&s->c.macaddr); 735 ne2000_reset(s); 736 737 s->nic = qemu_new_nic(&net_ne2000_info, &s->c, 738 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s); 739 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a); 740 741 add_boot_device_path(s->c.bootindex, &pci_dev->qdev, "/ethernet-phy@0"); 742 743 return 0; 744 } 745 746 static void pci_ne2000_exit(PCIDevice *pci_dev) 747 { 748 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); 749 NE2000State *s = &d->ne2000; 750 751 memory_region_destroy(&s->io); 752 qemu_del_nic(s->nic); 753 qemu_free_irq(s->irq); 754 } 755 756 static Property ne2000_properties[] = { 757 DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c), 758 DEFINE_PROP_END_OF_LIST(), 759 }; 760 761 static void ne2000_class_init(ObjectClass *klass, void *data) 762 { 763 DeviceClass *dc = DEVICE_CLASS(klass); 764 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 765 766 k->init = pci_ne2000_init; 767 k->exit = pci_ne2000_exit; 768 k->romfile = "efi-ne2k_pci.rom", 769 k->vendor_id = PCI_VENDOR_ID_REALTEK; 770 k->device_id = PCI_DEVICE_ID_REALTEK_8029; 771 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 772 dc->vmsd = &vmstate_pci_ne2000; 773 dc->props = ne2000_properties; 774 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 775 } 776 777 static const TypeInfo ne2000_info = { 778 .name = "ne2k_pci", 779 .parent = TYPE_PCI_DEVICE, 780 .instance_size = sizeof(PCINE2000State), 781 .class_init = ne2000_class_init, 782 }; 783 784 static void ne2000_register_types(void) 785 { 786 type_register_static(&ne2000_info); 787 } 788 789 type_init(ne2000_register_types) 790