1 /* 2 * Nuvoton NPCM7xx/8xx GMAC Module 3 * 4 * Copyright 2024 Google LLC 5 * Authors: 6 * Hao Wu <wuhaotsh@google.com> 7 * Nabih Estefan <nabihestefan@google.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * Unsupported/unimplemented features: 20 * - MII is not implemented, MII_ADDR.BUSY and MII_DATA always return zero 21 * - Precision timestamp (PTP) is not implemented. 22 */ 23 24 #include "qemu/osdep.h" 25 26 #include "hw/registerfields.h" 27 #include "hw/net/mii.h" 28 #include "hw/net/npcm_gmac.h" 29 #include "migration/vmstate.h" 30 #include "qemu/log.h" 31 #include "qemu/units.h" 32 #include "sysemu/dma.h" 33 #include "trace.h" 34 35 REG32(NPCM_DMA_BUS_MODE, 0x1000) 36 REG32(NPCM_DMA_XMT_POLL_DEMAND, 0x1004) 37 REG32(NPCM_DMA_RCV_POLL_DEMAND, 0x1008) 38 REG32(NPCM_DMA_RX_BASE_ADDR, 0x100c) 39 REG32(NPCM_DMA_TX_BASE_ADDR, 0x1010) 40 REG32(NPCM_DMA_STATUS, 0x1014) 41 REG32(NPCM_DMA_CONTROL, 0x1018) 42 REG32(NPCM_DMA_INTR_ENA, 0x101c) 43 REG32(NPCM_DMA_MISSED_FRAME_CTR, 0x1020) 44 REG32(NPCM_DMA_HOST_TX_DESC, 0x1048) 45 REG32(NPCM_DMA_HOST_RX_DESC, 0x104c) 46 REG32(NPCM_DMA_CUR_TX_BUF_ADDR, 0x1050) 47 REG32(NPCM_DMA_CUR_RX_BUF_ADDR, 0x1054) 48 REG32(NPCM_DMA_HW_FEATURE, 0x1058) 49 50 REG32(NPCM_GMAC_MAC_CONFIG, 0x0) 51 REG32(NPCM_GMAC_FRAME_FILTER, 0x4) 52 REG32(NPCM_GMAC_HASH_HIGH, 0x8) 53 REG32(NPCM_GMAC_HASH_LOW, 0xc) 54 REG32(NPCM_GMAC_MII_ADDR, 0x10) 55 REG32(NPCM_GMAC_MII_DATA, 0x14) 56 REG32(NPCM_GMAC_FLOW_CTRL, 0x18) 57 REG32(NPCM_GMAC_VLAN_FLAG, 0x1c) 58 REG32(NPCM_GMAC_VERSION, 0x20) 59 REG32(NPCM_GMAC_WAKEUP_FILTER, 0x28) 60 REG32(NPCM_GMAC_PMT, 0x2c) 61 REG32(NPCM_GMAC_LPI_CTRL, 0x30) 62 REG32(NPCM_GMAC_TIMER_CTRL, 0x34) 63 REG32(NPCM_GMAC_INT_STATUS, 0x38) 64 REG32(NPCM_GMAC_INT_MASK, 0x3c) 65 REG32(NPCM_GMAC_MAC0_ADDR_HI, 0x40) 66 REG32(NPCM_GMAC_MAC0_ADDR_LO, 0x44) 67 REG32(NPCM_GMAC_MAC1_ADDR_HI, 0x48) 68 REG32(NPCM_GMAC_MAC1_ADDR_LO, 0x4c) 69 REG32(NPCM_GMAC_MAC2_ADDR_HI, 0x50) 70 REG32(NPCM_GMAC_MAC2_ADDR_LO, 0x54) 71 REG32(NPCM_GMAC_MAC3_ADDR_HI, 0x58) 72 REG32(NPCM_GMAC_MAC3_ADDR_LO, 0x5c) 73 REG32(NPCM_GMAC_RGMII_STATUS, 0xd8) 74 REG32(NPCM_GMAC_WATCHDOG, 0xdc) 75 REG32(NPCM_GMAC_PTP_TCR, 0x700) 76 REG32(NPCM_GMAC_PTP_SSIR, 0x704) 77 REG32(NPCM_GMAC_PTP_STSR, 0x708) 78 REG32(NPCM_GMAC_PTP_STNSR, 0x70c) 79 REG32(NPCM_GMAC_PTP_STSUR, 0x710) 80 REG32(NPCM_GMAC_PTP_STNSUR, 0x714) 81 REG32(NPCM_GMAC_PTP_TAR, 0x718) 82 REG32(NPCM_GMAC_PTP_TTSR, 0x71c) 83 84 /* Register Fields */ 85 #define NPCM_GMAC_MII_ADDR_BUSY BIT(0) 86 #define NPCM_GMAC_MII_ADDR_WRITE BIT(1) 87 #define NPCM_GMAC_MII_ADDR_GR(rv) extract16((rv), 6, 5) 88 #define NPCM_GMAC_MII_ADDR_PA(rv) extract16((rv), 11, 5) 89 90 #define NPCM_GMAC_INT_MASK_LPIIM BIT(10) 91 #define NPCM_GMAC_INT_MASK_PMTM BIT(3) 92 #define NPCM_GMAC_INT_MASK_RGIM BIT(0) 93 94 #define NPCM_DMA_BUS_MODE_SWR BIT(0) 95 96 static const uint32_t npcm_gmac_cold_reset_values[NPCM_GMAC_NR_REGS] = { 97 /* Reduce version to 3.2 so that the kernel can enable interrupt. */ 98 [R_NPCM_GMAC_VERSION] = 0x00001032, 99 [R_NPCM_GMAC_TIMER_CTRL] = 0x03e80000, 100 [R_NPCM_GMAC_MAC0_ADDR_HI] = 0x8000ffff, 101 [R_NPCM_GMAC_MAC0_ADDR_LO] = 0xffffffff, 102 [R_NPCM_GMAC_MAC1_ADDR_HI] = 0x0000ffff, 103 [R_NPCM_GMAC_MAC1_ADDR_LO] = 0xffffffff, 104 [R_NPCM_GMAC_MAC2_ADDR_HI] = 0x0000ffff, 105 [R_NPCM_GMAC_MAC2_ADDR_LO] = 0xffffffff, 106 [R_NPCM_GMAC_MAC3_ADDR_HI] = 0x0000ffff, 107 [R_NPCM_GMAC_MAC3_ADDR_LO] = 0xffffffff, 108 [R_NPCM_GMAC_PTP_TCR] = 0x00002000, 109 [R_NPCM_DMA_BUS_MODE] = 0x00020101, 110 [R_NPCM_DMA_HW_FEATURE] = 0x100d4f37, 111 }; 112 113 static const uint16_t phy_reg_init[] = { 114 [MII_BMCR] = MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000, 115 [MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | 116 MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_AUTONEG | 117 MII_BMSR_LINK_ST | MII_BMSR_EXTCAP, 118 [MII_PHYID1] = 0x0362, 119 [MII_PHYID2] = 0x5e6a, 120 [MII_ANAR] = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | 121 MII_ANAR_10 | MII_ANAR_CSMACD, 122 [MII_ANLPAR] = MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | 123 MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | 124 MII_ANLPAR_10 | MII_ANLPAR_CSMACD, 125 [MII_ANER] = 0x64 | MII_ANER_NWAY, 126 [MII_ANNP] = 0x2001, 127 [MII_CTRL1000] = MII_CTRL1000_FULL, 128 [MII_STAT1000] = MII_STAT1000_FULL, 129 [MII_EXTSTAT] = 0x3000, /* 1000BASTE_T full-duplex capable */ 130 }; 131 132 static void npcm_gmac_soft_reset(NPCMGMACState *gmac) 133 { 134 memcpy(gmac->regs, npcm_gmac_cold_reset_values, 135 NPCM_GMAC_NR_REGS * sizeof(uint32_t)); 136 /* Clear reset bits */ 137 gmac->regs[R_NPCM_DMA_BUS_MODE] &= ~NPCM_DMA_BUS_MODE_SWR; 138 } 139 140 static void gmac_phy_set_link(NPCMGMACState *gmac, bool active) 141 { 142 /* Autonegotiation status mirrors link status. */ 143 if (active) { 144 gmac->phy_regs[0][MII_BMSR] |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); 145 } else { 146 gmac->phy_regs[0][MII_BMSR] &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); 147 } 148 } 149 150 static bool gmac_can_receive(NetClientState *nc) 151 { 152 return true; 153 } 154 155 /* 156 * Function that updates the GMAC IRQ 157 * It find the logical OR of the enabled bits for NIS (if enabled) 158 * It find the logical OR of the enabled bits for AIS (if enabled) 159 */ 160 static void gmac_update_irq(NPCMGMACState *gmac) 161 { 162 /* 163 * Check if the normal interrupts summary is enabled 164 * if so, add the bits for the summary that are enabled 165 */ 166 if (gmac->regs[R_NPCM_DMA_INTR_ENA] & gmac->regs[R_NPCM_DMA_STATUS] & 167 (NPCM_DMA_INTR_ENAB_NIE_BITS)) { 168 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_NIS; 169 } 170 /* 171 * Check if the abnormal interrupts summary is enabled 172 * if so, add the bits for the summary that are enabled 173 */ 174 if (gmac->regs[R_NPCM_DMA_INTR_ENA] & gmac->regs[R_NPCM_DMA_STATUS] & 175 (NPCM_DMA_INTR_ENAB_AIE_BITS)) { 176 gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_AIS; 177 } 178 179 /* Get the logical OR of both normal and abnormal interrupts */ 180 int level = !!((gmac->regs[R_NPCM_DMA_STATUS] & 181 gmac->regs[R_NPCM_DMA_INTR_ENA] & 182 NPCM_DMA_STATUS_NIS) | 183 (gmac->regs[R_NPCM_DMA_STATUS] & 184 gmac->regs[R_NPCM_DMA_INTR_ENA] & 185 NPCM_DMA_STATUS_AIS)); 186 187 /* Set the IRQ */ 188 trace_npcm_gmac_update_irq(DEVICE(gmac)->canonical_path, 189 gmac->regs[R_NPCM_DMA_STATUS], 190 gmac->regs[R_NPCM_DMA_INTR_ENA], 191 level); 192 qemu_set_irq(gmac->irq, level); 193 } 194 195 static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t len) 196 { 197 /* Placeholder. Function will be filled in following patches */ 198 return 0; 199 } 200 201 static void gmac_cleanup(NetClientState *nc) 202 { 203 /* Nothing to do yet. */ 204 } 205 206 static void gmac_set_link(NetClientState *nc) 207 { 208 NPCMGMACState *gmac = qemu_get_nic_opaque(nc); 209 210 trace_npcm_gmac_set_link(!nc->link_down); 211 gmac_phy_set_link(gmac, !nc->link_down); 212 } 213 214 static void npcm_gmac_mdio_access(NPCMGMACState *gmac, uint16_t v) 215 { 216 bool busy = v & NPCM_GMAC_MII_ADDR_BUSY; 217 uint8_t is_write; 218 uint8_t pa, gr; 219 uint16_t data; 220 221 if (busy) { 222 is_write = v & NPCM_GMAC_MII_ADDR_WRITE; 223 pa = NPCM_GMAC_MII_ADDR_PA(v); 224 gr = NPCM_GMAC_MII_ADDR_GR(v); 225 /* Both pa and gr are 5 bits, so they are less than 32. */ 226 g_assert(pa < NPCM_GMAC_MAX_PHYS); 227 g_assert(gr < NPCM_GMAC_MAX_PHY_REGS); 228 229 230 if (v & NPCM_GMAC_MII_ADDR_WRITE) { 231 data = gmac->regs[R_NPCM_GMAC_MII_DATA]; 232 /* Clear reset bit for BMCR register */ 233 switch (gr) { 234 case MII_BMCR: 235 data &= ~MII_BMCR_RESET; 236 /* Autonegotiation is a W1C bit*/ 237 if (data & MII_BMCR_ANRESTART) { 238 /* Tells autonegotiation to not restart again */ 239 data &= ~MII_BMCR_ANRESTART; 240 } 241 if ((data & MII_BMCR_AUTOEN) && 242 !(gmac->phy_regs[pa][MII_BMSR] & MII_BMSR_AN_COMP)) { 243 /* sets autonegotiation as complete */ 244 gmac->phy_regs[pa][MII_BMSR] |= MII_BMSR_AN_COMP; 245 /* Resolve AN automatically->need to set this */ 246 gmac->phy_regs[0][MII_ANLPAR] = 0x0000; 247 } 248 } 249 gmac->phy_regs[pa][gr] = data; 250 } else { 251 data = gmac->phy_regs[pa][gr]; 252 gmac->regs[R_NPCM_GMAC_MII_DATA] = data; 253 } 254 trace_npcm_gmac_mdio_access(DEVICE(gmac)->canonical_path, is_write, pa, 255 gr, data); 256 } 257 gmac->regs[R_NPCM_GMAC_MII_ADDR] = v & ~NPCM_GMAC_MII_ADDR_BUSY; 258 } 259 260 static uint64_t npcm_gmac_read(void *opaque, hwaddr offset, unsigned size) 261 { 262 NPCMGMACState *gmac = opaque; 263 uint32_t v = 0; 264 265 switch (offset) { 266 /* Write only registers */ 267 case A_NPCM_DMA_XMT_POLL_DEMAND: 268 case A_NPCM_DMA_RCV_POLL_DEMAND: 269 qemu_log_mask(LOG_GUEST_ERROR, 270 "%s: Read of write-only reg: offset: 0x%04" HWADDR_PRIx 271 "\n", DEVICE(gmac)->canonical_path, offset); 272 break; 273 274 default: 275 v = gmac->regs[offset / sizeof(uint32_t)]; 276 } 277 278 trace_npcm_gmac_reg_read(DEVICE(gmac)->canonical_path, offset, v); 279 return v; 280 } 281 282 static void npcm_gmac_write(void *opaque, hwaddr offset, 283 uint64_t v, unsigned size) 284 { 285 NPCMGMACState *gmac = opaque; 286 287 trace_npcm_gmac_reg_write(DEVICE(gmac)->canonical_path, offset, v); 288 289 switch (offset) { 290 /* Read only registers */ 291 case A_NPCM_GMAC_VERSION: 292 case A_NPCM_GMAC_INT_STATUS: 293 case A_NPCM_GMAC_RGMII_STATUS: 294 case A_NPCM_GMAC_PTP_STSR: 295 case A_NPCM_GMAC_PTP_STNSR: 296 case A_NPCM_DMA_MISSED_FRAME_CTR: 297 case A_NPCM_DMA_HOST_TX_DESC: 298 case A_NPCM_DMA_HOST_RX_DESC: 299 case A_NPCM_DMA_CUR_TX_BUF_ADDR: 300 case A_NPCM_DMA_CUR_RX_BUF_ADDR: 301 case A_NPCM_DMA_HW_FEATURE: 302 qemu_log_mask(LOG_GUEST_ERROR, 303 "%s: Write of read-only reg: offset: 0x%04" HWADDR_PRIx 304 ", value: 0x%04" PRIx64 "\n", 305 DEVICE(gmac)->canonical_path, offset, v); 306 break; 307 308 case A_NPCM_GMAC_MAC_CONFIG: 309 break; 310 311 case A_NPCM_GMAC_MII_ADDR: 312 npcm_gmac_mdio_access(gmac, v); 313 break; 314 315 case A_NPCM_GMAC_MAC0_ADDR_HI: 316 gmac->regs[offset / sizeof(uint32_t)] = v; 317 gmac->conf.macaddr.a[0] = v >> 8; 318 gmac->conf.macaddr.a[1] = v >> 0; 319 break; 320 321 case A_NPCM_GMAC_MAC0_ADDR_LO: 322 gmac->regs[offset / sizeof(uint32_t)] = v; 323 gmac->conf.macaddr.a[2] = v >> 24; 324 gmac->conf.macaddr.a[3] = v >> 16; 325 gmac->conf.macaddr.a[4] = v >> 8; 326 gmac->conf.macaddr.a[5] = v >> 0; 327 break; 328 329 case A_NPCM_GMAC_MAC1_ADDR_HI: 330 case A_NPCM_GMAC_MAC1_ADDR_LO: 331 case A_NPCM_GMAC_MAC2_ADDR_HI: 332 case A_NPCM_GMAC_MAC2_ADDR_LO: 333 case A_NPCM_GMAC_MAC3_ADDR_HI: 334 case A_NPCM_GMAC_MAC3_ADDR_LO: 335 gmac->regs[offset / sizeof(uint32_t)] = v; 336 qemu_log_mask(LOG_UNIMP, 337 "%s: Only MAC Address 0 is supported. This request " 338 "is ignored.\n", DEVICE(gmac)->canonical_path); 339 break; 340 341 case A_NPCM_DMA_BUS_MODE: 342 gmac->regs[offset / sizeof(uint32_t)] = v; 343 if (v & NPCM_DMA_BUS_MODE_SWR) { 344 npcm_gmac_soft_reset(gmac); 345 } 346 break; 347 348 case A_NPCM_DMA_RCV_POLL_DEMAND: 349 /* We dont actually care about the value */ 350 break; 351 352 case A_NPCM_DMA_STATUS: 353 /* Check that RO bits are not written to */ 354 if (NPCM_DMA_STATUS_RO_MASK(v)) { 355 qemu_log_mask(LOG_GUEST_ERROR, 356 "%s: Write of read-only bits of reg: offset: 0x%04" 357 HWADDR_PRIx ", value: 0x%04" PRIx64 "\n", 358 DEVICE(gmac)->canonical_path, offset, v); 359 } 360 break; 361 362 default: 363 gmac->regs[offset / sizeof(uint32_t)] = v; 364 break; 365 } 366 367 gmac_update_irq(gmac); 368 } 369 370 static void npcm_gmac_reset(DeviceState *dev) 371 { 372 NPCMGMACState *gmac = NPCM_GMAC(dev); 373 374 npcm_gmac_soft_reset(gmac); 375 memcpy(gmac->phy_regs[0], phy_reg_init, sizeof(phy_reg_init)); 376 377 trace_npcm_gmac_reset(DEVICE(gmac)->canonical_path, 378 gmac->phy_regs[0][MII_BMSR]); 379 } 380 381 static NetClientInfo net_npcm_gmac_info = { 382 .type = NET_CLIENT_DRIVER_NIC, 383 .size = sizeof(NICState), 384 .can_receive = gmac_can_receive, 385 .receive = gmac_receive, 386 .cleanup = gmac_cleanup, 387 .link_status_changed = gmac_set_link, 388 }; 389 390 static const struct MemoryRegionOps npcm_gmac_ops = { 391 .read = npcm_gmac_read, 392 .write = npcm_gmac_write, 393 .endianness = DEVICE_LITTLE_ENDIAN, 394 .valid = { 395 .min_access_size = 4, 396 .max_access_size = 4, 397 .unaligned = false, 398 }, 399 }; 400 401 static void npcm_gmac_realize(DeviceState *dev, Error **errp) 402 { 403 NPCMGMACState *gmac = NPCM_GMAC(dev); 404 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 405 406 memory_region_init_io(&gmac->iomem, OBJECT(gmac), &npcm_gmac_ops, gmac, 407 TYPE_NPCM_GMAC, 8 * KiB); 408 sysbus_init_mmio(sbd, &gmac->iomem); 409 sysbus_init_irq(sbd, &gmac->irq); 410 411 qemu_macaddr_default_if_unset(&gmac->conf.macaddr); 412 413 gmac->nic = qemu_new_nic(&net_npcm_gmac_info, &gmac->conf, TYPE_NPCM_GMAC, 414 dev->id, &dev->mem_reentrancy_guard, gmac); 415 qemu_format_nic_info_str(qemu_get_queue(gmac->nic), gmac->conf.macaddr.a); 416 gmac->regs[R_NPCM_GMAC_MAC0_ADDR_HI] = (gmac->conf.macaddr.a[0] << 8) + \ 417 gmac->conf.macaddr.a[1]; 418 gmac->regs[R_NPCM_GMAC_MAC0_ADDR_LO] = (gmac->conf.macaddr.a[2] << 24) + \ 419 (gmac->conf.macaddr.a[3] << 16) + \ 420 (gmac->conf.macaddr.a[4] << 8) + \ 421 gmac->conf.macaddr.a[5]; 422 } 423 424 static void npcm_gmac_unrealize(DeviceState *dev) 425 { 426 NPCMGMACState *gmac = NPCM_GMAC(dev); 427 428 qemu_del_nic(gmac->nic); 429 } 430 431 static const VMStateDescription vmstate_npcm_gmac = { 432 .name = TYPE_NPCM_GMAC, 433 .version_id = 0, 434 .minimum_version_id = 0, 435 .fields = (VMStateField[]) { 436 VMSTATE_UINT32_ARRAY(regs, NPCMGMACState, NPCM_GMAC_NR_REGS), 437 VMSTATE_END_OF_LIST(), 438 }, 439 }; 440 441 static Property npcm_gmac_properties[] = { 442 DEFINE_NIC_PROPERTIES(NPCMGMACState, conf), 443 DEFINE_PROP_END_OF_LIST(), 444 }; 445 446 static void npcm_gmac_class_init(ObjectClass *klass, void *data) 447 { 448 DeviceClass *dc = DEVICE_CLASS(klass); 449 450 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 451 dc->desc = "NPCM GMAC Controller"; 452 dc->realize = npcm_gmac_realize; 453 dc->unrealize = npcm_gmac_unrealize; 454 dc->reset = npcm_gmac_reset; 455 dc->vmsd = &vmstate_npcm_gmac; 456 device_class_set_props(dc, npcm_gmac_properties); 457 } 458 459 static const TypeInfo npcm_gmac_types[] = { 460 { 461 .name = TYPE_NPCM_GMAC, 462 .parent = TYPE_SYS_BUS_DEVICE, 463 .instance_size = sizeof(NPCMGMACState), 464 .class_init = npcm_gmac_class_init, 465 }, 466 }; 467 DEFINE_TYPES(npcm_gmac_types) 468