1 /* 2 * QEMU AMD PC-Net II (Am79C970A) PCI emulation 3 * 4 * Copyright (c) 2004 Antony T Curtis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* This software was written to be compatible with the specification: 26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/irq.h" 32 #include "hw/pci/pci.h" 33 #include "net/net.h" 34 #include "qemu/module.h" 35 #include "qemu/timer.h" 36 #include "sysemu/dma.h" 37 #include "sysemu/sysemu.h" 38 #include "trace.h" 39 40 #include "pcnet.h" 41 42 //#define PCNET_DEBUG 43 //#define PCNET_DEBUG_IO 44 //#define PCNET_DEBUG_BCR 45 //#define PCNET_DEBUG_CSR 46 //#define PCNET_DEBUG_RMD 47 //#define PCNET_DEBUG_TMD 48 //#define PCNET_DEBUG_MATCH 49 50 #define TYPE_PCI_PCNET "pcnet" 51 52 #define PCI_PCNET(obj) \ 53 OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET) 54 55 typedef struct { 56 /*< private >*/ 57 PCIDevice parent_obj; 58 /*< public >*/ 59 60 PCNetState state; 61 MemoryRegion io_bar; 62 } PCIPCNetState; 63 64 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) 65 { 66 PCNetState *s = opaque; 67 68 trace_pcnet_aprom_writeb(opaque, addr, val); 69 if (BCR_APROMWE(s)) { 70 s->prom[addr & 15] = val; 71 } 72 } 73 74 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr) 75 { 76 PCNetState *s = opaque; 77 uint32_t val = s->prom[addr & 15]; 78 79 trace_pcnet_aprom_readb(opaque, addr, val); 80 return val; 81 } 82 83 static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr, 84 unsigned size) 85 { 86 PCNetState *d = opaque; 87 88 trace_pcnet_ioport_read(opaque, addr, size); 89 if (addr < 0x10) { 90 if (!BCR_DWIO(d) && size == 1) { 91 return pcnet_aprom_readb(d, addr); 92 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 93 return pcnet_aprom_readb(d, addr) | 94 (pcnet_aprom_readb(d, addr + 1) << 8); 95 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 96 return pcnet_aprom_readb(d, addr) | 97 (pcnet_aprom_readb(d, addr + 1) << 8) | 98 (pcnet_aprom_readb(d, addr + 2) << 16) | 99 (pcnet_aprom_readb(d, addr + 3) << 24); 100 } 101 } else { 102 if (size == 2) { 103 return pcnet_ioport_readw(d, addr); 104 } else if (size == 4) { 105 return pcnet_ioport_readl(d, addr); 106 } 107 } 108 return ((uint64_t)1 << (size * 8)) - 1; 109 } 110 111 static void pcnet_ioport_write(void *opaque, hwaddr addr, 112 uint64_t data, unsigned size) 113 { 114 PCNetState *d = opaque; 115 116 trace_pcnet_ioport_write(opaque, addr, data, size); 117 if (addr < 0x10) { 118 if (!BCR_DWIO(d) && size == 1) { 119 pcnet_aprom_writeb(d, addr, data); 120 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 121 pcnet_aprom_writeb(d, addr, data & 0xff); 122 pcnet_aprom_writeb(d, addr + 1, data >> 8); 123 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 124 pcnet_aprom_writeb(d, addr, data & 0xff); 125 pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff); 126 pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff); 127 pcnet_aprom_writeb(d, addr + 3, data >> 24); 128 } 129 } else { 130 if (size == 2) { 131 pcnet_ioport_writew(d, addr, data); 132 } else if (size == 4) { 133 pcnet_ioport_writel(d, addr, data); 134 } 135 } 136 } 137 138 static const MemoryRegionOps pcnet_io_ops = { 139 .read = pcnet_ioport_read, 140 .write = pcnet_ioport_write, 141 .endianness = DEVICE_LITTLE_ENDIAN, 142 }; 143 144 static const VMStateDescription vmstate_pci_pcnet = { 145 .name = "pcnet", 146 .version_id = 3, 147 .minimum_version_id = 2, 148 .fields = (VMStateField[]) { 149 VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState), 150 VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), 151 VMSTATE_END_OF_LIST() 152 } 153 }; 154 155 /* PCI interface */ 156 157 static const MemoryRegionOps pcnet_mmio_ops = { 158 .read = pcnet_ioport_read, 159 .write = pcnet_ioport_write, 160 .valid.min_access_size = 1, 161 .valid.max_access_size = 4, 162 .impl.min_access_size = 1, 163 .impl.max_access_size = 4, 164 .endianness = DEVICE_LITTLE_ENDIAN, 165 }; 166 167 static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, 168 uint8_t *buf, int len, int do_bswap) 169 { 170 pci_dma_write(dma_opaque, addr, buf, len); 171 } 172 173 static void pci_physical_memory_read(void *dma_opaque, hwaddr addr, 174 uint8_t *buf, int len, int do_bswap) 175 { 176 pci_dma_read(dma_opaque, addr, buf, len); 177 } 178 179 static void pci_pcnet_uninit(PCIDevice *dev) 180 { 181 PCIPCNetState *d = PCI_PCNET(dev); 182 183 qemu_free_irq(d->state.irq); 184 timer_del(d->state.poll_timer); 185 timer_free(d->state.poll_timer); 186 qemu_del_nic(d->state.nic); 187 } 188 189 static NetClientInfo net_pci_pcnet_info = { 190 .type = NET_CLIENT_DRIVER_NIC, 191 .size = sizeof(NICState), 192 .receive = pcnet_receive, 193 .link_status_changed = pcnet_set_link_status, 194 }; 195 196 static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp) 197 { 198 PCIPCNetState *d = PCI_PCNET(pci_dev); 199 PCNetState *s = &d->state; 200 uint8_t *pci_conf; 201 202 #if 0 203 printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", 204 sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD)); 205 #endif 206 207 pci_conf = pci_dev->config; 208 209 pci_set_word(pci_conf + PCI_STATUS, 210 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 211 212 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); 213 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); 214 215 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 216 pci_conf[PCI_MIN_GNT] = 0x06; 217 pci_conf[PCI_MAX_LAT] = 0xff; 218 219 /* Handler for memory-mapped I/O */ 220 memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s, 221 "pcnet-mmio", PCNET_PNPMMIO_SIZE); 222 223 memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io", 224 PCNET_IOPORT_SIZE); 225 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); 226 227 pci_register_bar(pci_dev, 1, 0, &s->mmio); 228 229 s->irq = pci_allocate_irq(pci_dev); 230 s->phys_mem_read = pci_physical_memory_read; 231 s->phys_mem_write = pci_physical_memory_write; 232 s->dma_opaque = pci_dev; 233 234 pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info); 235 } 236 237 static void pci_reset(DeviceState *dev) 238 { 239 PCIPCNetState *d = PCI_PCNET(dev); 240 241 pcnet_h_reset(&d->state); 242 } 243 244 static void pcnet_instance_init(Object *obj) 245 { 246 PCIPCNetState *d = PCI_PCNET(obj); 247 PCNetState *s = &d->state; 248 249 device_add_bootindex_property(obj, &s->conf.bootindex, 250 "bootindex", "/ethernet-phy@0", 251 DEVICE(obj), NULL); 252 } 253 254 static Property pcnet_properties[] = { 255 DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), 256 DEFINE_PROP_END_OF_LIST(), 257 }; 258 259 static void pcnet_class_init(ObjectClass *klass, void *data) 260 { 261 DeviceClass *dc = DEVICE_CLASS(klass); 262 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 263 264 k->realize = pci_pcnet_realize; 265 k->exit = pci_pcnet_uninit; 266 k->romfile = "efi-pcnet.rom", 267 k->vendor_id = PCI_VENDOR_ID_AMD; 268 k->device_id = PCI_DEVICE_ID_AMD_LANCE; 269 k->revision = 0x10; 270 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 271 dc->reset = pci_reset; 272 dc->vmsd = &vmstate_pci_pcnet; 273 dc->props = pcnet_properties; 274 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 275 } 276 277 static const TypeInfo pcnet_info = { 278 .name = TYPE_PCI_PCNET, 279 .parent = TYPE_PCI_DEVICE, 280 .instance_size = sizeof(PCIPCNetState), 281 .class_init = pcnet_class_init, 282 .instance_init = pcnet_instance_init, 283 .interfaces = (InterfaceInfo[]) { 284 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 285 { }, 286 }, 287 }; 288 289 static void pci_pcnet_register_types(void) 290 { 291 type_register_static(&pcnet_info); 292 } 293 294 type_init(pci_pcnet_register_types) 295