1 /* 2 * QEMU AMD PC-Net II (Am79C970A) PCI emulation 3 * 4 * Copyright (c) 2004 Antony T Curtis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* This software was written to be compatible with the specification: 26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 28 */ 29 30 #include "hw/pci/pci.h" 31 #include "net/net.h" 32 #include "hw/loader.h" 33 #include "qemu/timer.h" 34 #include "sysemu/dma.h" 35 36 #include "pcnet.h" 37 38 //#define PCNET_DEBUG 39 //#define PCNET_DEBUG_IO 40 //#define PCNET_DEBUG_BCR 41 //#define PCNET_DEBUG_CSR 42 //#define PCNET_DEBUG_RMD 43 //#define PCNET_DEBUG_TMD 44 //#define PCNET_DEBUG_MATCH 45 46 #define TYPE_PCI_PCNET "pcnet" 47 48 #define PCI_PCNET(obj) \ 49 OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET) 50 51 typedef struct { 52 /*< private >*/ 53 PCIDevice parent_obj; 54 /*< public >*/ 55 56 PCNetState state; 57 MemoryRegion io_bar; 58 } PCIPCNetState; 59 60 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) 61 { 62 PCNetState *s = opaque; 63 #ifdef PCNET_DEBUG 64 printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val); 65 #endif 66 if (BCR_APROMWE(s)) { 67 s->prom[addr & 15] = val; 68 } 69 } 70 71 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr) 72 { 73 PCNetState *s = opaque; 74 uint32_t val = s->prom[addr & 15]; 75 #ifdef PCNET_DEBUG 76 printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val); 77 #endif 78 return val; 79 } 80 81 static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr, 82 unsigned size) 83 { 84 PCNetState *d = opaque; 85 86 if (addr < 0x10) { 87 if (!BCR_DWIO(d) && size == 1) { 88 return pcnet_aprom_readb(d, addr); 89 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 90 return pcnet_aprom_readb(d, addr) | 91 (pcnet_aprom_readb(d, addr + 1) << 8); 92 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 93 return pcnet_aprom_readb(d, addr) | 94 (pcnet_aprom_readb(d, addr + 1) << 8) | 95 (pcnet_aprom_readb(d, addr + 2) << 16) | 96 (pcnet_aprom_readb(d, addr + 3) << 24); 97 } 98 } else { 99 if (size == 2) { 100 return pcnet_ioport_readw(d, addr); 101 } else if (size == 4) { 102 return pcnet_ioport_readl(d, addr); 103 } 104 } 105 return ((uint64_t)1 << (size * 8)) - 1; 106 } 107 108 static void pcnet_ioport_write(void *opaque, hwaddr addr, 109 uint64_t data, unsigned size) 110 { 111 PCNetState *d = opaque; 112 113 if (addr < 0x10) { 114 if (!BCR_DWIO(d) && size == 1) { 115 pcnet_aprom_writeb(d, addr, data); 116 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 117 pcnet_aprom_writeb(d, addr, data & 0xff); 118 pcnet_aprom_writeb(d, addr + 1, data >> 8); 119 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 120 pcnet_aprom_writeb(d, addr, data & 0xff); 121 pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff); 122 pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff); 123 pcnet_aprom_writeb(d, addr + 3, data >> 24); 124 } 125 } else { 126 if (size == 2) { 127 pcnet_ioport_writew(d, addr, data); 128 } else if (size == 4) { 129 pcnet_ioport_writel(d, addr, data); 130 } 131 } 132 } 133 134 static const MemoryRegionOps pcnet_io_ops = { 135 .read = pcnet_ioport_read, 136 .write = pcnet_ioport_write, 137 .endianness = DEVICE_LITTLE_ENDIAN, 138 }; 139 140 static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) 141 { 142 PCNetState *d = opaque; 143 #ifdef PCNET_DEBUG_IO 144 printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr, 145 val); 146 #endif 147 if (!(addr & 0x10)) 148 pcnet_aprom_writeb(d, addr & 0x0f, val); 149 } 150 151 static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr) 152 { 153 PCNetState *d = opaque; 154 uint32_t val = -1; 155 if (!(addr & 0x10)) 156 val = pcnet_aprom_readb(d, addr & 0x0f); 157 #ifdef PCNET_DEBUG_IO 158 printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, 159 val & 0xff); 160 #endif 161 return val; 162 } 163 164 static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val) 165 { 166 PCNetState *d = opaque; 167 #ifdef PCNET_DEBUG_IO 168 printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, 169 val); 170 #endif 171 if (addr & 0x10) 172 pcnet_ioport_writew(d, addr & 0x0f, val); 173 else { 174 addr &= 0x0f; 175 pcnet_aprom_writeb(d, addr, val & 0xff); 176 pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); 177 } 178 } 179 180 static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr) 181 { 182 PCNetState *d = opaque; 183 uint32_t val = -1; 184 if (addr & 0x10) 185 val = pcnet_ioport_readw(d, addr & 0x0f); 186 else { 187 addr &= 0x0f; 188 val = pcnet_aprom_readb(d, addr+1); 189 val <<= 8; 190 val |= pcnet_aprom_readb(d, addr); 191 } 192 #ifdef PCNET_DEBUG_IO 193 printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr, 194 val & 0xffff); 195 #endif 196 return val; 197 } 198 199 static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val) 200 { 201 PCNetState *d = opaque; 202 #ifdef PCNET_DEBUG_IO 203 printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr, 204 val); 205 #endif 206 if (addr & 0x10) 207 pcnet_ioport_writel(d, addr & 0x0f, val); 208 else { 209 addr &= 0x0f; 210 pcnet_aprom_writeb(d, addr, val & 0xff); 211 pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); 212 pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16); 213 pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24); 214 } 215 } 216 217 static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr) 218 { 219 PCNetState *d = opaque; 220 uint32_t val; 221 if (addr & 0x10) 222 val = pcnet_ioport_readl(d, addr & 0x0f); 223 else { 224 addr &= 0x0f; 225 val = pcnet_aprom_readb(d, addr+3); 226 val <<= 8; 227 val |= pcnet_aprom_readb(d, addr+2); 228 val <<= 8; 229 val |= pcnet_aprom_readb(d, addr+1); 230 val <<= 8; 231 val |= pcnet_aprom_readb(d, addr); 232 } 233 #ifdef PCNET_DEBUG_IO 234 printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, 235 val); 236 #endif 237 return val; 238 } 239 240 static const VMStateDescription vmstate_pci_pcnet = { 241 .name = "pcnet", 242 .version_id = 3, 243 .minimum_version_id = 2, 244 .fields = (VMStateField[]) { 245 VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState), 246 VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), 247 VMSTATE_END_OF_LIST() 248 } 249 }; 250 251 /* PCI interface */ 252 253 static const MemoryRegionOps pcnet_mmio_ops = { 254 .old_mmio = { 255 .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl }, 256 .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel }, 257 }, 258 .endianness = DEVICE_LITTLE_ENDIAN, 259 }; 260 261 static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, 262 uint8_t *buf, int len, int do_bswap) 263 { 264 pci_dma_write(dma_opaque, addr, buf, len); 265 } 266 267 static void pci_physical_memory_read(void *dma_opaque, hwaddr addr, 268 uint8_t *buf, int len, int do_bswap) 269 { 270 pci_dma_read(dma_opaque, addr, buf, len); 271 } 272 273 static void pci_pcnet_cleanup(NetClientState *nc) 274 { 275 PCNetState *d = qemu_get_nic_opaque(nc); 276 277 pcnet_common_cleanup(d); 278 } 279 280 static void pci_pcnet_uninit(PCIDevice *dev) 281 { 282 PCIPCNetState *d = PCI_PCNET(dev); 283 284 qemu_free_irq(d->state.irq); 285 timer_del(d->state.poll_timer); 286 timer_free(d->state.poll_timer); 287 qemu_del_nic(d->state.nic); 288 } 289 290 static NetClientInfo net_pci_pcnet_info = { 291 .type = NET_CLIENT_OPTIONS_KIND_NIC, 292 .size = sizeof(NICState), 293 .can_receive = pcnet_can_receive, 294 .receive = pcnet_receive, 295 .link_status_changed = pcnet_set_link_status, 296 .cleanup = pci_pcnet_cleanup, 297 }; 298 299 static int pci_pcnet_init(PCIDevice *pci_dev) 300 { 301 PCIPCNetState *d = PCI_PCNET(pci_dev); 302 PCNetState *s = &d->state; 303 uint8_t *pci_conf; 304 305 #if 0 306 printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", 307 sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD)); 308 #endif 309 310 pci_conf = pci_dev->config; 311 312 pci_set_word(pci_conf + PCI_STATUS, 313 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 314 315 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); 316 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); 317 318 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 319 pci_conf[PCI_MIN_GNT] = 0x06; 320 pci_conf[PCI_MAX_LAT] = 0xff; 321 322 /* Handler for memory-mapped I/O */ 323 memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s, 324 "pcnet-mmio", PCNET_PNPMMIO_SIZE); 325 326 memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io", 327 PCNET_IOPORT_SIZE); 328 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); 329 330 pci_register_bar(pci_dev, 1, 0, &s->mmio); 331 332 s->irq = pci_allocate_irq(pci_dev); 333 s->phys_mem_read = pci_physical_memory_read; 334 s->phys_mem_write = pci_physical_memory_write; 335 s->dma_opaque = pci_dev; 336 337 return pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info); 338 } 339 340 static void pci_reset(DeviceState *dev) 341 { 342 PCIPCNetState *d = PCI_PCNET(dev); 343 344 pcnet_h_reset(&d->state); 345 } 346 347 static Property pcnet_properties[] = { 348 DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), 349 DEFINE_PROP_END_OF_LIST(), 350 }; 351 352 static void pcnet_class_init(ObjectClass *klass, void *data) 353 { 354 DeviceClass *dc = DEVICE_CLASS(klass); 355 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 356 357 k->init = pci_pcnet_init; 358 k->exit = pci_pcnet_uninit; 359 k->romfile = "efi-pcnet.rom", 360 k->vendor_id = PCI_VENDOR_ID_AMD; 361 k->device_id = PCI_DEVICE_ID_AMD_LANCE; 362 k->revision = 0x10; 363 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 364 dc->reset = pci_reset; 365 dc->vmsd = &vmstate_pci_pcnet; 366 dc->props = pcnet_properties; 367 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 368 } 369 370 static const TypeInfo pcnet_info = { 371 .name = TYPE_PCI_PCNET, 372 .parent = TYPE_PCI_DEVICE, 373 .instance_size = sizeof(PCIPCNetState), 374 .class_init = pcnet_class_init, 375 }; 376 377 static void pci_pcnet_register_types(void) 378 { 379 type_register_static(&pcnet_info); 380 } 381 382 type_init(pci_pcnet_register_types) 383