1 /* 2 * QEMU VMWARE VMXNET3 paravirtual NIC 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Tamir Shomer <tamirs@daynix.com> 11 * Yan Vugenfirer <yan@daynix.com> 12 * 13 * This work is licensed under the terms of the GNU GPL, version 2. 14 * See the COPYING file in the top-level directory. 15 * 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/hw.h" 20 #include "hw/pci/pci.h" 21 #include "net/net.h" 22 #include "net/tap.h" 23 #include "net/checksum.h" 24 #include "sysemu/sysemu.h" 25 #include "qemu-common.h" 26 #include "qemu/bswap.h" 27 #include "hw/pci/msix.h" 28 #include "hw/pci/msi.h" 29 30 #include "vmxnet3.h" 31 #include "vmxnet_debug.h" 32 #include "vmware_utils.h" 33 #include "net_tx_pkt.h" 34 #include "net_rx_pkt.h" 35 36 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1 37 #define VMXNET3_MSIX_BAR_SIZE 0x2000 38 #define MIN_BUF_SIZE 60 39 40 /* Compatibility flags for migration */ 41 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0 42 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \ 43 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT) 44 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1 45 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \ 46 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT) 47 48 #define VMXNET3_EXP_EP_OFFSET (0x48) 49 #define VMXNET3_MSI_OFFSET(s) \ 50 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84) 51 #define VMXNET3_MSIX_OFFSET(s) \ 52 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c) 53 #define VMXNET3_DSN_OFFSET (0x100) 54 55 #define VMXNET3_BAR0_IDX (0) 56 #define VMXNET3_BAR1_IDX (1) 57 #define VMXNET3_MSIX_BAR_IDX (2) 58 59 #define VMXNET3_OFF_MSIX_TABLE (0x000) 60 #define VMXNET3_OFF_MSIX_PBA(s) \ 61 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000) 62 63 /* Link speed in Mbps should be shifted by 16 */ 64 #define VMXNET3_LINK_SPEED (1000 << 16) 65 66 /* Link status: 1 - up, 0 - down. */ 67 #define VMXNET3_LINK_STATUS_UP 0x1 68 69 /* Least significant bit should be set for revision and version */ 70 #define VMXNET3_UPT_REVISION 0x1 71 #define VMXNET3_DEVICE_REVISION 0x1 72 73 /* Number of interrupt vectors for non-MSIx modes */ 74 #define VMXNET3_MAX_NMSIX_INTRS (1) 75 76 /* Macros for rings descriptors access */ 77 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \ 78 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 79 80 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \ 81 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value))) 82 83 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \ 84 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 85 86 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \ 87 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 88 89 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \ 90 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 91 92 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \ 93 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 94 95 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \ 96 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 97 98 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \ 99 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 100 101 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \ 102 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 103 104 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \ 105 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 106 107 /* Macros for guest driver shared area access */ 108 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \ 109 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field))) 110 111 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \ 112 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field))) 113 114 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \ 115 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val)) 116 117 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \ 118 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field))) 119 120 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \ 121 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field))) 122 123 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \ 124 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l)) 125 126 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag)) 127 128 typedef struct VMXNET3Class { 129 PCIDeviceClass parent_class; 130 DeviceRealize parent_dc_realize; 131 } VMXNET3Class; 132 133 #define TYPE_VMXNET3 "vmxnet3" 134 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3) 135 136 #define VMXNET3_DEVICE_CLASS(klass) \ 137 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3) 138 #define VMXNET3_DEVICE_GET_CLASS(obj) \ 139 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3) 140 141 /* Cyclic ring abstraction */ 142 typedef struct { 143 hwaddr pa; 144 size_t size; 145 size_t cell_size; 146 size_t next; 147 uint8_t gen; 148 } Vmxnet3Ring; 149 150 static inline void vmxnet3_ring_init(Vmxnet3Ring *ring, 151 hwaddr pa, 152 size_t size, 153 size_t cell_size, 154 bool zero_region) 155 { 156 ring->pa = pa; 157 ring->size = size; 158 ring->cell_size = cell_size; 159 ring->gen = VMXNET3_INIT_GEN; 160 ring->next = 0; 161 162 if (zero_region) { 163 vmw_shmem_set(pa, 0, size * cell_size); 164 } 165 } 166 167 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \ 168 macro("%s#%d: base %" PRIx64 " size %zu cell_size %zu gen %d next %zu", \ 169 (ring_name), (ridx), \ 170 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next) 171 172 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring) 173 { 174 if (++ring->next >= ring->size) { 175 ring->next = 0; 176 ring->gen ^= 1; 177 } 178 } 179 180 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring) 181 { 182 if (ring->next-- == 0) { 183 ring->next = ring->size - 1; 184 ring->gen ^= 1; 185 } 186 } 187 188 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring) 189 { 190 return ring->pa + ring->next * ring->cell_size; 191 } 192 193 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring *ring, void *buff) 194 { 195 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 196 } 197 198 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring *ring, void *buff) 199 { 200 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 201 } 202 203 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring) 204 { 205 return ring->next; 206 } 207 208 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring) 209 { 210 return ring->gen; 211 } 212 213 /* Debug trace-related functions */ 214 static inline void 215 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr) 216 { 217 VMW_PKPRN("TX DESCR: " 218 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 219 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, " 220 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d", 221 le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd, 222 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om, 223 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci); 224 } 225 226 static inline void 227 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr) 228 { 229 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, " 230 "csum_start: %d, csum_offset: %d", 231 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size, 232 vhdr->csum_start, vhdr->csum_offset); 233 } 234 235 static inline void 236 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr) 237 { 238 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 239 "dtype: %d, ext1: %d, btype: %d", 240 le64_to_cpu(descr->addr), descr->len, descr->gen, 241 descr->rsvd, descr->dtype, descr->ext1, descr->btype); 242 } 243 244 /* Device state and helper functions */ 245 #define VMXNET3_RX_RINGS_PER_QUEUE (2) 246 247 typedef struct { 248 Vmxnet3Ring tx_ring; 249 Vmxnet3Ring comp_ring; 250 251 uint8_t intr_idx; 252 hwaddr tx_stats_pa; 253 struct UPT1_TxStats txq_stats; 254 } Vmxnet3TxqDescr; 255 256 typedef struct { 257 Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE]; 258 Vmxnet3Ring comp_ring; 259 uint8_t intr_idx; 260 hwaddr rx_stats_pa; 261 struct UPT1_RxStats rxq_stats; 262 } Vmxnet3RxqDescr; 263 264 typedef struct { 265 bool is_masked; 266 bool is_pending; 267 bool is_asserted; 268 } Vmxnet3IntState; 269 270 typedef struct { 271 PCIDevice parent_obj; 272 NICState *nic; 273 NICConf conf; 274 MemoryRegion bar0; 275 MemoryRegion bar1; 276 MemoryRegion msix_bar; 277 278 Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES]; 279 Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES]; 280 281 /* Whether MSI-X support was installed successfully */ 282 bool msix_used; 283 /* Whether MSI support was installed successfully */ 284 bool msi_used; 285 hwaddr drv_shmem; 286 hwaddr temp_shared_guest_driver_memory; 287 288 uint8_t txq_num; 289 290 /* This boolean tells whether RX packet being indicated has to */ 291 /* be split into head and body chunks from different RX rings */ 292 bool rx_packets_compound; 293 294 bool rx_vlan_stripping; 295 bool lro_supported; 296 297 uint8_t rxq_num; 298 299 /* Network MTU */ 300 uint32_t mtu; 301 302 /* Maximum number of fragments for indicated TX packets */ 303 uint32_t max_tx_frags; 304 305 /* Maximum number of fragments for indicated RX packets */ 306 uint16_t max_rx_frags; 307 308 /* Index for events interrupt */ 309 uint8_t event_int_idx; 310 311 /* Whether automatic interrupts masking enabled */ 312 bool auto_int_masking; 313 314 bool peer_has_vhdr; 315 316 /* TX packets to QEMU interface */ 317 struct NetTxPkt *tx_pkt; 318 uint32_t offload_mode; 319 uint32_t cso_or_gso_size; 320 uint16_t tci; 321 bool needs_vlan; 322 323 struct NetRxPkt *rx_pkt; 324 325 bool tx_sop; 326 bool skip_current_tx_pkt; 327 328 uint32_t device_active; 329 uint32_t last_command; 330 331 uint32_t link_status_and_speed; 332 333 Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS]; 334 335 uint32_t temp_mac; /* To store the low part first */ 336 337 MACAddr perm_mac; 338 uint32_t vlan_table[VMXNET3_VFT_SIZE]; 339 uint32_t rx_mode; 340 MACAddr *mcast_list; 341 uint32_t mcast_list_len; 342 uint32_t mcast_list_buff_size; /* needed for live migration. */ 343 344 /* Compatibility flags for migration */ 345 uint32_t compat_flags; 346 } VMXNET3State; 347 348 /* Interrupt management */ 349 350 /* 351 * This function returns sign whether interrupt line is in asserted state 352 * This depends on the type of interrupt used. For INTX interrupt line will 353 * be asserted until explicit deassertion, for MSI(X) interrupt line will 354 * be deasserted automatically due to notification semantics of the MSI(X) 355 * interrupts 356 */ 357 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx) 358 { 359 PCIDevice *d = PCI_DEVICE(s); 360 361 if (s->msix_used && msix_enabled(d)) { 362 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx); 363 msix_notify(d, int_idx); 364 return false; 365 } 366 if (s->msi_used && msi_enabled(d)) { 367 VMW_IRPRN("Sending MSI notification for vector %u", int_idx); 368 msi_notify(d, int_idx); 369 return false; 370 } 371 372 VMW_IRPRN("Asserting line for interrupt %u", int_idx); 373 pci_irq_assert(d); 374 return true; 375 } 376 377 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx) 378 { 379 PCIDevice *d = PCI_DEVICE(s); 380 381 /* 382 * This function should never be called for MSI(X) interrupts 383 * because deassertion never required for message interrupts 384 */ 385 assert(!s->msix_used || !msix_enabled(d)); 386 /* 387 * This function should never be called for MSI(X) interrupts 388 * because deassertion never required for message interrupts 389 */ 390 assert(!s->msi_used || !msi_enabled(d)); 391 392 VMW_IRPRN("Deasserting line for interrupt %u", lidx); 393 pci_irq_deassert(d); 394 } 395 396 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx) 397 { 398 if (!s->interrupt_states[lidx].is_pending && 399 s->interrupt_states[lidx].is_asserted) { 400 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx); 401 _vmxnet3_deassert_interrupt_line(s, lidx); 402 s->interrupt_states[lidx].is_asserted = false; 403 return; 404 } 405 406 if (s->interrupt_states[lidx].is_pending && 407 !s->interrupt_states[lidx].is_masked && 408 !s->interrupt_states[lidx].is_asserted) { 409 VMW_IRPRN("New interrupt line state for index %d is UP", lidx); 410 s->interrupt_states[lidx].is_asserted = 411 _vmxnet3_assert_interrupt_line(s, lidx); 412 s->interrupt_states[lidx].is_pending = false; 413 return; 414 } 415 } 416 417 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx) 418 { 419 PCIDevice *d = PCI_DEVICE(s); 420 s->interrupt_states[lidx].is_pending = true; 421 vmxnet3_update_interrupt_line_state(s, lidx); 422 423 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) { 424 goto do_automask; 425 } 426 427 if (s->msi_used && msi_enabled(d) && s->auto_int_masking) { 428 goto do_automask; 429 } 430 431 return; 432 433 do_automask: 434 s->interrupt_states[lidx].is_masked = true; 435 vmxnet3_update_interrupt_line_state(s, lidx); 436 } 437 438 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx) 439 { 440 return s->interrupt_states[lidx].is_asserted; 441 } 442 443 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx) 444 { 445 s->interrupt_states[int_idx].is_pending = false; 446 if (s->auto_int_masking) { 447 s->interrupt_states[int_idx].is_masked = true; 448 } 449 vmxnet3_update_interrupt_line_state(s, int_idx); 450 } 451 452 static void 453 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked) 454 { 455 s->interrupt_states[lidx].is_masked = is_masked; 456 vmxnet3_update_interrupt_line_state(s, lidx); 457 } 458 459 static bool vmxnet3_verify_driver_magic(hwaddr dshmem) 460 { 461 return (VMXNET3_READ_DRV_SHARED32(dshmem, magic) == VMXNET3_REV1_MAGIC); 462 } 463 464 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF) 465 #define VMXNET3_MAKE_BYTE(byte_num, val) \ 466 (((uint32_t)((val) & 0xFF)) << (byte_num)*8) 467 468 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l) 469 { 470 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0); 471 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1); 472 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2); 473 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3); 474 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0); 475 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1); 476 477 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 478 479 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 480 } 481 482 static uint64_t vmxnet3_get_mac_low(MACAddr *addr) 483 { 484 return VMXNET3_MAKE_BYTE(0, addr->a[0]) | 485 VMXNET3_MAKE_BYTE(1, addr->a[1]) | 486 VMXNET3_MAKE_BYTE(2, addr->a[2]) | 487 VMXNET3_MAKE_BYTE(3, addr->a[3]); 488 } 489 490 static uint64_t vmxnet3_get_mac_high(MACAddr *addr) 491 { 492 return VMXNET3_MAKE_BYTE(0, addr->a[4]) | 493 VMXNET3_MAKE_BYTE(1, addr->a[5]); 494 } 495 496 static void 497 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx) 498 { 499 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring); 500 } 501 502 static inline void 503 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx) 504 { 505 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]); 506 } 507 508 static inline void 509 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx) 510 { 511 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring); 512 } 513 514 static void 515 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx) 516 { 517 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring); 518 } 519 520 static void 521 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx) 522 { 523 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring); 524 } 525 526 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx) 527 { 528 struct Vmxnet3_TxCompDesc txcq_descr; 529 530 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring); 531 532 txcq_descr.txdIdx = tx_ridx; 533 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring); 534 535 vmxnet3_ring_write_curr_cell(&s->txq_descr[qidx].comp_ring, &txcq_descr); 536 537 /* Flush changes in TX descriptor before changing the counter value */ 538 smp_wmb(); 539 540 vmxnet3_inc_tx_completion_counter(s, qidx); 541 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx); 542 } 543 544 static bool 545 vmxnet3_setup_tx_offloads(VMXNET3State *s) 546 { 547 switch (s->offload_mode) { 548 case VMXNET3_OM_NONE: 549 net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0); 550 break; 551 552 case VMXNET3_OM_CSUM: 553 net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0); 554 VMW_PKPRN("L4 CSO requested\n"); 555 break; 556 557 case VMXNET3_OM_TSO: 558 net_tx_pkt_build_vheader(s->tx_pkt, true, true, 559 s->cso_or_gso_size); 560 net_tx_pkt_update_ip_checksums(s->tx_pkt); 561 VMW_PKPRN("GSO offload requested."); 562 break; 563 564 default: 565 g_assert_not_reached(); 566 return false; 567 } 568 569 return true; 570 } 571 572 static void 573 vmxnet3_tx_retrieve_metadata(VMXNET3State *s, 574 const struct Vmxnet3_TxDesc *txd) 575 { 576 s->offload_mode = txd->om; 577 s->cso_or_gso_size = txd->msscof; 578 s->tci = txd->tci; 579 s->needs_vlan = txd->ti; 580 } 581 582 typedef enum { 583 VMXNET3_PKT_STATUS_OK, 584 VMXNET3_PKT_STATUS_ERROR, 585 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */ 586 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */ 587 } Vmxnet3PktStatus; 588 589 static void 590 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx, 591 Vmxnet3PktStatus status) 592 { 593 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt); 594 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats; 595 596 switch (status) { 597 case VMXNET3_PKT_STATUS_OK: 598 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) { 599 case ETH_PKT_BCAST: 600 stats->bcastPktsTxOK++; 601 stats->bcastBytesTxOK += tot_len; 602 break; 603 case ETH_PKT_MCAST: 604 stats->mcastPktsTxOK++; 605 stats->mcastBytesTxOK += tot_len; 606 break; 607 case ETH_PKT_UCAST: 608 stats->ucastPktsTxOK++; 609 stats->ucastBytesTxOK += tot_len; 610 break; 611 default: 612 g_assert_not_reached(); 613 } 614 615 if (s->offload_mode == VMXNET3_OM_TSO) { 616 /* 617 * According to VMWARE headers this statistic is a number 618 * of packets after segmentation but since we don't have 619 * this information in QEMU model, the best we can do is to 620 * provide number of non-segmented packets 621 */ 622 stats->TSOPktsTxOK++; 623 stats->TSOBytesTxOK += tot_len; 624 } 625 break; 626 627 case VMXNET3_PKT_STATUS_DISCARD: 628 stats->pktsTxDiscard++; 629 break; 630 631 case VMXNET3_PKT_STATUS_ERROR: 632 stats->pktsTxError++; 633 break; 634 635 default: 636 g_assert_not_reached(); 637 } 638 } 639 640 static void 641 vmxnet3_on_rx_done_update_stats(VMXNET3State *s, 642 int qidx, 643 Vmxnet3PktStatus status) 644 { 645 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats; 646 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt); 647 648 switch (status) { 649 case VMXNET3_PKT_STATUS_OUT_OF_BUF: 650 stats->pktsRxOutOfBuf++; 651 break; 652 653 case VMXNET3_PKT_STATUS_ERROR: 654 stats->pktsRxError++; 655 break; 656 case VMXNET3_PKT_STATUS_OK: 657 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 658 case ETH_PKT_BCAST: 659 stats->bcastPktsRxOK++; 660 stats->bcastBytesRxOK += tot_len; 661 break; 662 case ETH_PKT_MCAST: 663 stats->mcastPktsRxOK++; 664 stats->mcastBytesRxOK += tot_len; 665 break; 666 case ETH_PKT_UCAST: 667 stats->ucastPktsRxOK++; 668 stats->ucastBytesRxOK += tot_len; 669 break; 670 default: 671 g_assert_not_reached(); 672 } 673 674 if (tot_len > s->mtu) { 675 stats->LROPktsRxOK++; 676 stats->LROBytesRxOK += tot_len; 677 } 678 break; 679 default: 680 g_assert_not_reached(); 681 } 682 } 683 684 static inline bool 685 vmxnet3_pop_next_tx_descr(VMXNET3State *s, 686 int qidx, 687 struct Vmxnet3_TxDesc *txd, 688 uint32_t *descr_idx) 689 { 690 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring; 691 692 vmxnet3_ring_read_curr_cell(ring, txd); 693 if (txd->gen == vmxnet3_ring_curr_gen(ring)) { 694 /* Only read after generation field verification */ 695 smp_rmb(); 696 /* Re-read to be sure we got the latest version */ 697 vmxnet3_ring_read_curr_cell(ring, txd); 698 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring); 699 *descr_idx = vmxnet3_ring_curr_cell_idx(ring); 700 vmxnet3_inc_tx_consumption_counter(s, qidx); 701 return true; 702 } 703 704 return false; 705 } 706 707 static bool 708 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx) 709 { 710 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK; 711 712 if (!vmxnet3_setup_tx_offloads(s)) { 713 status = VMXNET3_PKT_STATUS_ERROR; 714 goto func_exit; 715 } 716 717 /* debug prints */ 718 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt)); 719 net_tx_pkt_dump(s->tx_pkt); 720 721 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) { 722 status = VMXNET3_PKT_STATUS_DISCARD; 723 goto func_exit; 724 } 725 726 func_exit: 727 vmxnet3_on_tx_done_update_stats(s, qidx, status); 728 return (status == VMXNET3_PKT_STATUS_OK); 729 } 730 731 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx) 732 { 733 struct Vmxnet3_TxDesc txd; 734 uint32_t txd_idx; 735 uint32_t data_len; 736 hwaddr data_pa; 737 738 for (;;) { 739 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) { 740 break; 741 } 742 743 vmxnet3_dump_tx_descr(&txd); 744 745 if (!s->skip_current_tx_pkt) { 746 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE; 747 data_pa = le64_to_cpu(txd.addr); 748 749 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt, 750 data_pa, 751 data_len)) { 752 s->skip_current_tx_pkt = true; 753 } 754 } 755 756 if (s->tx_sop) { 757 vmxnet3_tx_retrieve_metadata(s, &txd); 758 s->tx_sop = false; 759 } 760 761 if (txd.eop) { 762 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) { 763 if (s->needs_vlan) { 764 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci); 765 } 766 767 vmxnet3_send_packet(s, qidx); 768 } else { 769 vmxnet3_on_tx_done_update_stats(s, qidx, 770 VMXNET3_PKT_STATUS_ERROR); 771 } 772 773 vmxnet3_complete_packet(s, qidx, txd_idx); 774 s->tx_sop = true; 775 s->skip_current_tx_pkt = false; 776 net_tx_pkt_reset(s->tx_pkt); 777 } 778 } 779 } 780 781 static inline void 782 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx, 783 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx) 784 { 785 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx]; 786 *didx = vmxnet3_ring_curr_cell_idx(ring); 787 vmxnet3_ring_read_curr_cell(ring, dbuf); 788 } 789 790 static inline uint8_t 791 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx) 792 { 793 return s->rxq_descr[qidx].rx_ring[ridx].gen; 794 } 795 796 static inline hwaddr 797 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen) 798 { 799 uint8_t ring_gen; 800 struct Vmxnet3_RxCompDesc rxcd; 801 802 hwaddr daddr = 803 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring); 804 805 pci_dma_read(PCI_DEVICE(s), daddr, 806 &rxcd, sizeof(struct Vmxnet3_RxCompDesc)); 807 808 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring); 809 810 if (rxcd.gen != ring_gen) { 811 *descr_gen = ring_gen; 812 vmxnet3_inc_rx_completion_counter(s, qidx); 813 return daddr; 814 } 815 816 return 0; 817 } 818 819 static inline void 820 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx) 821 { 822 vmxnet3_dec_rx_completion_counter(s, qidx); 823 } 824 825 #define RXQ_IDX (0) 826 #define RX_HEAD_BODY_RING (0) 827 #define RX_BODY_ONLY_RING (1) 828 829 static bool 830 vmxnet3_get_next_head_rx_descr(VMXNET3State *s, 831 struct Vmxnet3_RxDesc *descr_buf, 832 uint32_t *descr_idx, 833 uint32_t *ridx) 834 { 835 for (;;) { 836 uint32_t ring_gen; 837 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 838 descr_buf, descr_idx); 839 840 /* If no more free descriptors - return */ 841 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING); 842 if (descr_buf->gen != ring_gen) { 843 return false; 844 } 845 846 /* Only read after generation field verification */ 847 smp_rmb(); 848 /* Re-read to be sure we got the latest version */ 849 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 850 descr_buf, descr_idx); 851 852 /* Mark current descriptor as used/skipped */ 853 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 854 855 /* If this is what we are looking for - return */ 856 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) { 857 *ridx = RX_HEAD_BODY_RING; 858 return true; 859 } 860 } 861 } 862 863 static bool 864 vmxnet3_get_next_body_rx_descr(VMXNET3State *s, 865 struct Vmxnet3_RxDesc *d, 866 uint32_t *didx, 867 uint32_t *ridx) 868 { 869 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 870 871 /* Try to find corresponding descriptor in head/body ring */ 872 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) { 873 /* Only read after generation field verification */ 874 smp_rmb(); 875 /* Re-read to be sure we got the latest version */ 876 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 877 if (d->btype == VMXNET3_RXD_BTYPE_BODY) { 878 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 879 *ridx = RX_HEAD_BODY_RING; 880 return true; 881 } 882 } 883 884 /* 885 * If there is no free descriptors on head/body ring or next free 886 * descriptor is a head descriptor switch to body only ring 887 */ 888 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 889 890 /* If no more free descriptors - return */ 891 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) { 892 /* Only read after generation field verification */ 893 smp_rmb(); 894 /* Re-read to be sure we got the latest version */ 895 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 896 assert(d->btype == VMXNET3_RXD_BTYPE_BODY); 897 *ridx = RX_BODY_ONLY_RING; 898 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING); 899 return true; 900 } 901 902 return false; 903 } 904 905 static inline bool 906 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head, 907 struct Vmxnet3_RxDesc *descr_buf, 908 uint32_t *descr_idx, 909 uint32_t *ridx) 910 { 911 if (is_head || !s->rx_packets_compound) { 912 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx); 913 } else { 914 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx); 915 } 916 } 917 918 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID), 919 * the implementation always passes an RxCompDesc with a "Checksum 920 * calculated and found correct" to the OS (cnc=0 and tuc=1, see 921 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior. 922 * 923 * Therefore, if packet has the NEEDS_CSUM set, we must calculate 924 * and place a fully computed checksum into the tcp/udp header. 925 * Otherwise, the OS driver will receive a checksum-correct indication 926 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field 927 * having just the pseudo header csum value. 928 * 929 * While this is not a problem if packet is destined for local delivery, 930 * in the case the host OS performs forwarding, it will forward an 931 * incorrectly checksummed packet. 932 */ 933 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt, 934 const void *pkt_data, 935 size_t pkt_len) 936 { 937 struct virtio_net_hdr *vhdr; 938 bool isip4, isip6, istcp, isudp; 939 uint8_t *data; 940 int len; 941 942 if (!net_rx_pkt_has_virt_hdr(pkt)) { 943 return; 944 } 945 946 vhdr = net_rx_pkt_get_vhdr(pkt); 947 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 948 return; 949 } 950 951 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 952 if (!(isip4 || isip6) || !(istcp || isudp)) { 953 return; 954 } 955 956 vmxnet3_dump_virt_hdr(vhdr); 957 958 /* Validate packet len: csum_start + scum_offset + length of csum field */ 959 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) { 960 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, " 961 "cannot calculate checksum", 962 pkt_len, vhdr->csum_start, vhdr->csum_offset); 963 return; 964 } 965 966 data = (uint8_t *)pkt_data + vhdr->csum_start; 967 len = pkt_len - vhdr->csum_start; 968 /* Put the checksum obtained into the packet */ 969 stw_be_p(data + vhdr->csum_offset, net_raw_checksum(data, len)); 970 971 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM; 972 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID; 973 } 974 975 static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt, 976 struct Vmxnet3_RxCompDesc *rxcd) 977 { 978 int csum_ok, is_gso; 979 bool isip4, isip6, istcp, isudp; 980 struct virtio_net_hdr *vhdr; 981 uint8_t offload_type; 982 983 if (net_rx_pkt_is_vlan_stripped(pkt)) { 984 rxcd->ts = 1; 985 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt); 986 } 987 988 if (!net_rx_pkt_has_virt_hdr(pkt)) { 989 goto nocsum; 990 } 991 992 vhdr = net_rx_pkt_get_vhdr(pkt); 993 /* 994 * Checksum is valid when lower level tell so or when lower level 995 * requires checksum offload telling that packet produced/bridged 996 * locally and did travel over network after last checksum calculation 997 * or production 998 */ 999 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) || 1000 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM); 1001 1002 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN; 1003 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0; 1004 1005 if (!csum_ok && !is_gso) { 1006 goto nocsum; 1007 } 1008 1009 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1010 if ((!istcp && !isudp) || (!isip4 && !isip6)) { 1011 goto nocsum; 1012 } 1013 1014 rxcd->cnc = 0; 1015 rxcd->v4 = isip4 ? 1 : 0; 1016 rxcd->v6 = isip6 ? 1 : 0; 1017 rxcd->tcp = istcp ? 1 : 0; 1018 rxcd->udp = isudp ? 1 : 0; 1019 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1; 1020 return; 1021 1022 nocsum: 1023 rxcd->cnc = 1; 1024 return; 1025 } 1026 1027 static void 1028 vmxnet3_pci_dma_writev(PCIDevice *pci_dev, 1029 const struct iovec *iov, 1030 size_t start_iov_off, 1031 hwaddr target_addr, 1032 size_t bytes_to_copy) 1033 { 1034 size_t curr_off = 0; 1035 size_t copied = 0; 1036 1037 while (bytes_to_copy) { 1038 if (start_iov_off < (curr_off + iov->iov_len)) { 1039 size_t chunk_len = 1040 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy); 1041 1042 pci_dma_write(pci_dev, target_addr + copied, 1043 iov->iov_base + start_iov_off - curr_off, 1044 chunk_len); 1045 1046 copied += chunk_len; 1047 start_iov_off += chunk_len; 1048 curr_off = start_iov_off; 1049 bytes_to_copy -= chunk_len; 1050 } else { 1051 curr_off += iov->iov_len; 1052 } 1053 iov++; 1054 } 1055 } 1056 1057 static bool 1058 vmxnet3_indicate_packet(VMXNET3State *s) 1059 { 1060 struct Vmxnet3_RxDesc rxd; 1061 bool is_head = true; 1062 uint32_t rxd_idx; 1063 uint32_t rx_ridx = 0; 1064 1065 struct Vmxnet3_RxCompDesc rxcd; 1066 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN; 1067 hwaddr new_rxcd_pa = 0; 1068 hwaddr ready_rxcd_pa = 0; 1069 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt); 1070 size_t bytes_copied = 0; 1071 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt); 1072 uint16_t num_frags = 0; 1073 size_t chunk_size; 1074 1075 net_rx_pkt_dump(s->rx_pkt); 1076 1077 while (bytes_left > 0) { 1078 1079 /* cannot add more frags to packet */ 1080 if (num_frags == s->max_rx_frags) { 1081 break; 1082 } 1083 1084 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen); 1085 if (!new_rxcd_pa) { 1086 break; 1087 } 1088 1089 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) { 1090 break; 1091 } 1092 1093 chunk_size = MIN(bytes_left, rxd.len); 1094 vmxnet3_pci_dma_writev(PCI_DEVICE(s), data, bytes_copied, 1095 le64_to_cpu(rxd.addr), chunk_size); 1096 bytes_copied += chunk_size; 1097 bytes_left -= chunk_size; 1098 1099 vmxnet3_dump_rx_descr(&rxd); 1100 1101 if (ready_rxcd_pa != 0) { 1102 pci_dma_write(PCI_DEVICE(s), ready_rxcd_pa, &rxcd, sizeof(rxcd)); 1103 } 1104 1105 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc)); 1106 rxcd.rxdIdx = rxd_idx; 1107 rxcd.len = chunk_size; 1108 rxcd.sop = is_head; 1109 rxcd.gen = new_rxcd_gen; 1110 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num; 1111 1112 if (bytes_left == 0) { 1113 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd); 1114 } 1115 1116 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu " 1117 "sop %d csum_correct %lu", 1118 (unsigned long) rx_ridx, 1119 (unsigned long) rxcd.rxdIdx, 1120 (unsigned long) rxcd.len, 1121 (int) rxcd.sop, 1122 (unsigned long) rxcd.tuc); 1123 1124 is_head = false; 1125 ready_rxcd_pa = new_rxcd_pa; 1126 new_rxcd_pa = 0; 1127 num_frags++; 1128 } 1129 1130 if (ready_rxcd_pa != 0) { 1131 rxcd.eop = 1; 1132 rxcd.err = (bytes_left != 0); 1133 1134 pci_dma_write(PCI_DEVICE(s), ready_rxcd_pa, &rxcd, sizeof(rxcd)); 1135 1136 /* Flush RX descriptor changes */ 1137 smp_wmb(); 1138 } 1139 1140 if (new_rxcd_pa != 0) { 1141 vmxnet3_revert_rxc_descr(s, RXQ_IDX); 1142 } 1143 1144 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx); 1145 1146 if (bytes_left == 0) { 1147 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK); 1148 return true; 1149 } else if (num_frags == s->max_rx_frags) { 1150 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR); 1151 return false; 1152 } else { 1153 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, 1154 VMXNET3_PKT_STATUS_OUT_OF_BUF); 1155 return false; 1156 } 1157 } 1158 1159 static void 1160 vmxnet3_io_bar0_write(void *opaque, hwaddr addr, 1161 uint64_t val, unsigned size) 1162 { 1163 VMXNET3State *s = opaque; 1164 1165 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD, 1166 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) { 1167 int tx_queue_idx = 1168 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD, 1169 VMXNET3_REG_ALIGN); 1170 assert(tx_queue_idx <= s->txq_num); 1171 vmxnet3_process_tx_queue(s, tx_queue_idx); 1172 return; 1173 } 1174 1175 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1176 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1177 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1178 VMXNET3_REG_ALIGN); 1179 1180 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val); 1181 1182 vmxnet3_on_interrupt_mask_changed(s, l, val); 1183 return; 1184 } 1185 1186 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD, 1187 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) || 1188 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2, 1189 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) { 1190 return; 1191 } 1192 1193 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d", 1194 (uint64_t) addr, val, size); 1195 } 1196 1197 static uint64_t 1198 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) 1199 { 1200 VMXNET3State *s = opaque; 1201 1202 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1203 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1204 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1205 VMXNET3_REG_ALIGN); 1206 return s->interrupt_states[l].is_masked; 1207 } 1208 1209 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); 1210 return 0; 1211 } 1212 1213 static void vmxnet3_reset_interrupt_states(VMXNET3State *s) 1214 { 1215 int i; 1216 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) { 1217 s->interrupt_states[i].is_asserted = false; 1218 s->interrupt_states[i].is_pending = false; 1219 s->interrupt_states[i].is_masked = true; 1220 } 1221 } 1222 1223 static void vmxnet3_reset_mac(VMXNET3State *s) 1224 { 1225 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a)); 1226 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 1227 } 1228 1229 static void vmxnet3_deactivate_device(VMXNET3State *s) 1230 { 1231 if (s->device_active) { 1232 VMW_CBPRN("Deactivating vmxnet3..."); 1233 net_tx_pkt_reset(s->tx_pkt); 1234 net_tx_pkt_uninit(s->tx_pkt); 1235 net_rx_pkt_uninit(s->rx_pkt); 1236 s->device_active = false; 1237 } 1238 } 1239 1240 static void vmxnet3_reset(VMXNET3State *s) 1241 { 1242 VMW_CBPRN("Resetting vmxnet3..."); 1243 1244 vmxnet3_deactivate_device(s); 1245 vmxnet3_reset_interrupt_states(s); 1246 s->drv_shmem = 0; 1247 s->tx_sop = true; 1248 s->skip_current_tx_pkt = false; 1249 } 1250 1251 static void vmxnet3_update_rx_mode(VMXNET3State *s) 1252 { 1253 s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, 1254 devRead.rxFilterConf.rxMode); 1255 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode); 1256 } 1257 1258 static void vmxnet3_update_vlan_filters(VMXNET3State *s) 1259 { 1260 int i; 1261 1262 /* Copy configuration from shared memory */ 1263 VMXNET3_READ_DRV_SHARED(s->drv_shmem, 1264 devRead.rxFilterConf.vfTable, 1265 s->vlan_table, 1266 sizeof(s->vlan_table)); 1267 1268 /* Invert byte order when needed */ 1269 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) { 1270 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]); 1271 } 1272 1273 /* Dump configuration for debugging purposes */ 1274 VMW_CFPRN("Configured VLANs:"); 1275 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) { 1276 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) { 1277 VMW_CFPRN("\tVLAN %d is present", i); 1278 } 1279 } 1280 } 1281 1282 static void vmxnet3_update_mcast_filters(VMXNET3State *s) 1283 { 1284 uint16_t list_bytes = 1285 VMXNET3_READ_DRV_SHARED16(s->drv_shmem, 1286 devRead.rxFilterConf.mfTableLen); 1287 1288 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]); 1289 1290 s->mcast_list = g_realloc(s->mcast_list, list_bytes); 1291 if (!s->mcast_list) { 1292 if (s->mcast_list_len == 0) { 1293 VMW_CFPRN("Current multicast list is empty"); 1294 } else { 1295 VMW_ERPRN("Failed to allocate multicast list of %d elements", 1296 s->mcast_list_len); 1297 } 1298 s->mcast_list_len = 0; 1299 } else { 1300 int i; 1301 hwaddr mcast_list_pa = 1302 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, 1303 devRead.rxFilterConf.mfTablePA); 1304 1305 pci_dma_read(PCI_DEVICE(s), mcast_list_pa, s->mcast_list, list_bytes); 1306 1307 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len); 1308 for (i = 0; i < s->mcast_list_len; i++) { 1309 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a)); 1310 } 1311 } 1312 } 1313 1314 static void vmxnet3_setup_rx_filtering(VMXNET3State *s) 1315 { 1316 vmxnet3_update_rx_mode(s); 1317 vmxnet3_update_vlan_filters(s); 1318 vmxnet3_update_mcast_filters(s); 1319 } 1320 1321 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s) 1322 { 1323 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2); 1324 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode); 1325 return interrupt_mode; 1326 } 1327 1328 static void vmxnet3_fill_stats(VMXNET3State *s) 1329 { 1330 int i; 1331 1332 if (!s->device_active) 1333 return; 1334 1335 for (i = 0; i < s->txq_num; i++) { 1336 pci_dma_write(PCI_DEVICE(s), 1337 s->txq_descr[i].tx_stats_pa, 1338 &s->txq_descr[i].txq_stats, 1339 sizeof(s->txq_descr[i].txq_stats)); 1340 } 1341 1342 for (i = 0; i < s->rxq_num; i++) { 1343 pci_dma_write(PCI_DEVICE(s), 1344 s->rxq_descr[i].rx_stats_pa, 1345 &s->rxq_descr[i].rxq_stats, 1346 sizeof(s->rxq_descr[i].rxq_stats)); 1347 } 1348 } 1349 1350 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s) 1351 { 1352 struct Vmxnet3_GOSInfo gos; 1353 1354 VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos, 1355 &gos, sizeof(gos)); 1356 s->rx_packets_compound = 1357 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true; 1358 1359 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound); 1360 } 1361 1362 static void 1363 vmxnet3_dump_conf_descr(const char *name, 1364 struct Vmxnet3_VariableLenConfDesc *pm_descr) 1365 { 1366 VMW_CFPRN("%s descriptor dump: Version %u, Length %u", 1367 name, pm_descr->confVer, pm_descr->confLen); 1368 1369 }; 1370 1371 static void vmxnet3_update_pm_state(VMXNET3State *s) 1372 { 1373 struct Vmxnet3_VariableLenConfDesc pm_descr; 1374 1375 pm_descr.confLen = 1376 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen); 1377 pm_descr.confVer = 1378 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer); 1379 pm_descr.confPA = 1380 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA); 1381 1382 vmxnet3_dump_conf_descr("PM State", &pm_descr); 1383 } 1384 1385 static void vmxnet3_update_features(VMXNET3State *s) 1386 { 1387 uint32_t guest_features; 1388 int rxcso_supported; 1389 1390 guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, 1391 devRead.misc.uptFeatures); 1392 1393 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM); 1394 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN); 1395 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO); 1396 1397 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d", 1398 s->lro_supported, rxcso_supported, 1399 s->rx_vlan_stripping); 1400 if (s->peer_has_vhdr) { 1401 qemu_set_offload(qemu_get_queue(s->nic)->peer, 1402 rxcso_supported, 1403 s->lro_supported, 1404 s->lro_supported, 1405 0, 1406 0); 1407 } 1408 } 1409 1410 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx) 1411 { 1412 return s->msix_used || s->msi_used || (intx == 1413 (pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1)); 1414 } 1415 1416 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx) 1417 { 1418 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS; 1419 if (idx >= max_ints) { 1420 hw_error("Bad interrupt index: %d\n", idx); 1421 } 1422 } 1423 1424 static void vmxnet3_validate_interrupts(VMXNET3State *s) 1425 { 1426 int i; 1427 1428 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx); 1429 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx); 1430 1431 for (i = 0; i < s->txq_num; i++) { 1432 int idx = s->txq_descr[i].intr_idx; 1433 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx); 1434 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1435 } 1436 1437 for (i = 0; i < s->rxq_num; i++) { 1438 int idx = s->rxq_descr[i].intr_idx; 1439 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx); 1440 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1441 } 1442 } 1443 1444 static void vmxnet3_validate_queues(VMXNET3State *s) 1445 { 1446 /* 1447 * txq_num and rxq_num are total number of queues 1448 * configured by guest. These numbers must not 1449 * exceed corresponding maximal values. 1450 */ 1451 1452 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) { 1453 hw_error("Bad TX queues number: %d\n", s->txq_num); 1454 } 1455 1456 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) { 1457 hw_error("Bad RX queues number: %d\n", s->rxq_num); 1458 } 1459 } 1460 1461 static void vmxnet3_activate_device(VMXNET3State *s) 1462 { 1463 int i; 1464 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1; 1465 hwaddr qdescr_table_pa; 1466 uint64_t pa; 1467 uint32_t size; 1468 1469 /* Verify configuration consistency */ 1470 if (!vmxnet3_verify_driver_magic(s->drv_shmem)) { 1471 VMW_ERPRN("Device configuration received from driver is invalid"); 1472 return; 1473 } 1474 1475 /* Verify if device is active */ 1476 if (s->device_active) { 1477 VMW_CFPRN("Vmxnet3 device is active"); 1478 return; 1479 } 1480 1481 vmxnet3_adjust_by_guest_type(s); 1482 vmxnet3_update_features(s); 1483 vmxnet3_update_pm_state(s); 1484 vmxnet3_setup_rx_filtering(s); 1485 /* Cache fields from shared memory */ 1486 s->mtu = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.misc.mtu); 1487 VMW_CFPRN("MTU is %u", s->mtu); 1488 1489 s->max_rx_frags = 1490 VMXNET3_READ_DRV_SHARED16(s->drv_shmem, devRead.misc.maxNumRxSG); 1491 1492 if (s->max_rx_frags == 0) { 1493 s->max_rx_frags = 1; 1494 } 1495 1496 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags); 1497 1498 s->event_int_idx = 1499 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx); 1500 assert(vmxnet3_verify_intx(s, s->event_int_idx)); 1501 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx); 1502 1503 s->auto_int_masking = 1504 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.autoMask); 1505 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking); 1506 1507 s->txq_num = 1508 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numTxQueues); 1509 s->rxq_num = 1510 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues); 1511 1512 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num); 1513 vmxnet3_validate_queues(s); 1514 1515 qdescr_table_pa = 1516 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA); 1517 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa); 1518 1519 /* 1520 * Worst-case scenario is a packet that holds all TX rings space so 1521 * we calculate total size of all TX rings for max TX fragments number 1522 */ 1523 s->max_tx_frags = 0; 1524 1525 /* TX queues */ 1526 for (i = 0; i < s->txq_num; i++) { 1527 hwaddr qdescr_pa = 1528 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc); 1529 1530 /* Read interrupt number for this TX queue */ 1531 s->txq_descr[i].intr_idx = 1532 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx); 1533 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx)); 1534 1535 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx); 1536 1537 /* Read rings memory locations for TX queues */ 1538 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.txRingBasePA); 1539 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.txRingSize); 1540 1541 vmxnet3_ring_init(&s->txq_descr[i].tx_ring, pa, size, 1542 sizeof(struct Vmxnet3_TxDesc), false); 1543 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring); 1544 1545 s->max_tx_frags += size; 1546 1547 /* TXC ring */ 1548 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.compRingBasePA); 1549 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.compRingSize); 1550 vmxnet3_ring_init(&s->txq_descr[i].comp_ring, pa, size, 1551 sizeof(struct Vmxnet3_TxCompDesc), true); 1552 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring); 1553 1554 s->txq_descr[i].tx_stats_pa = 1555 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats); 1556 1557 memset(&s->txq_descr[i].txq_stats, 0, 1558 sizeof(s->txq_descr[i].txq_stats)); 1559 1560 /* Fill device-managed parameters for queues */ 1561 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa, 1562 ctrl.txThreshold, 1563 VMXNET3_DEF_TX_THRESHOLD); 1564 } 1565 1566 /* Preallocate TX packet wrapper */ 1567 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags); 1568 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), 1569 s->max_tx_frags, s->peer_has_vhdr); 1570 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); 1571 1572 /* Read rings memory locations for RX queues */ 1573 for (i = 0; i < s->rxq_num; i++) { 1574 int j; 1575 hwaddr qd_pa = 1576 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) + 1577 i * sizeof(struct Vmxnet3_RxQueueDesc); 1578 1579 /* Read interrupt number for this RX queue */ 1580 s->rxq_descr[i].intr_idx = 1581 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx); 1582 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx)); 1583 1584 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx); 1585 1586 /* Read rings memory locations */ 1587 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) { 1588 /* RX rings */ 1589 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.rxRingBasePA[j]); 1590 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.rxRingSize[j]); 1591 vmxnet3_ring_init(&s->rxq_descr[i].rx_ring[j], pa, size, 1592 sizeof(struct Vmxnet3_RxDesc), false); 1593 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d", 1594 i, j, pa, size); 1595 } 1596 1597 /* RXC ring */ 1598 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.compRingBasePA); 1599 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.compRingSize); 1600 vmxnet3_ring_init(&s->rxq_descr[i].comp_ring, pa, size, 1601 sizeof(struct Vmxnet3_RxCompDesc), true); 1602 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size); 1603 1604 s->rxq_descr[i].rx_stats_pa = 1605 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats); 1606 memset(&s->rxq_descr[i].rxq_stats, 0, 1607 sizeof(s->rxq_descr[i].rxq_stats)); 1608 } 1609 1610 vmxnet3_validate_interrupts(s); 1611 1612 /* Make sure everything is in place before device activation */ 1613 smp_wmb(); 1614 1615 vmxnet3_reset_mac(s); 1616 1617 s->device_active = true; 1618 } 1619 1620 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd) 1621 { 1622 s->last_command = cmd; 1623 1624 switch (cmd) { 1625 case VMXNET3_CMD_GET_PERM_MAC_HI: 1626 VMW_CBPRN("Set: Get upper part of permanent MAC"); 1627 break; 1628 1629 case VMXNET3_CMD_GET_PERM_MAC_LO: 1630 VMW_CBPRN("Set: Get lower part of permanent MAC"); 1631 break; 1632 1633 case VMXNET3_CMD_GET_STATS: 1634 VMW_CBPRN("Set: Get device statistics"); 1635 vmxnet3_fill_stats(s); 1636 break; 1637 1638 case VMXNET3_CMD_ACTIVATE_DEV: 1639 VMW_CBPRN("Set: Activating vmxnet3 device"); 1640 vmxnet3_activate_device(s); 1641 break; 1642 1643 case VMXNET3_CMD_UPDATE_RX_MODE: 1644 VMW_CBPRN("Set: Update rx mode"); 1645 vmxnet3_update_rx_mode(s); 1646 break; 1647 1648 case VMXNET3_CMD_UPDATE_VLAN_FILTERS: 1649 VMW_CBPRN("Set: Update VLAN filters"); 1650 vmxnet3_update_vlan_filters(s); 1651 break; 1652 1653 case VMXNET3_CMD_UPDATE_MAC_FILTERS: 1654 VMW_CBPRN("Set: Update MAC filters"); 1655 vmxnet3_update_mcast_filters(s); 1656 break; 1657 1658 case VMXNET3_CMD_UPDATE_FEATURE: 1659 VMW_CBPRN("Set: Update features"); 1660 vmxnet3_update_features(s); 1661 break; 1662 1663 case VMXNET3_CMD_UPDATE_PMCFG: 1664 VMW_CBPRN("Set: Update power management config"); 1665 vmxnet3_update_pm_state(s); 1666 break; 1667 1668 case VMXNET3_CMD_GET_LINK: 1669 VMW_CBPRN("Set: Get link"); 1670 break; 1671 1672 case VMXNET3_CMD_RESET_DEV: 1673 VMW_CBPRN("Set: Reset device"); 1674 vmxnet3_reset(s); 1675 break; 1676 1677 case VMXNET3_CMD_QUIESCE_DEV: 1678 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device"); 1679 vmxnet3_deactivate_device(s); 1680 break; 1681 1682 case VMXNET3_CMD_GET_CONF_INTR: 1683 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration"); 1684 break; 1685 1686 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1687 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - " 1688 "adaptive ring info flags"); 1689 break; 1690 1691 case VMXNET3_CMD_GET_DID_LO: 1692 VMW_CBPRN("Set: Get lower part of device ID"); 1693 break; 1694 1695 case VMXNET3_CMD_GET_DID_HI: 1696 VMW_CBPRN("Set: Get upper part of device ID"); 1697 break; 1698 1699 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1700 VMW_CBPRN("Set: Get device extra info"); 1701 break; 1702 1703 default: 1704 VMW_CBPRN("Received unknown command: %" PRIx64, cmd); 1705 break; 1706 } 1707 } 1708 1709 static uint64_t vmxnet3_get_command_status(VMXNET3State *s) 1710 { 1711 uint64_t ret; 1712 1713 switch (s->last_command) { 1714 case VMXNET3_CMD_ACTIVATE_DEV: 1715 ret = (s->device_active) ? 0 : 1; 1716 VMW_CFPRN("Device active: %" PRIx64, ret); 1717 break; 1718 1719 case VMXNET3_CMD_RESET_DEV: 1720 case VMXNET3_CMD_QUIESCE_DEV: 1721 case VMXNET3_CMD_GET_QUEUE_STATUS: 1722 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1723 ret = 0; 1724 break; 1725 1726 case VMXNET3_CMD_GET_LINK: 1727 ret = s->link_status_and_speed; 1728 VMW_CFPRN("Link and speed: %" PRIx64, ret); 1729 break; 1730 1731 case VMXNET3_CMD_GET_PERM_MAC_LO: 1732 ret = vmxnet3_get_mac_low(&s->perm_mac); 1733 break; 1734 1735 case VMXNET3_CMD_GET_PERM_MAC_HI: 1736 ret = vmxnet3_get_mac_high(&s->perm_mac); 1737 break; 1738 1739 case VMXNET3_CMD_GET_CONF_INTR: 1740 ret = vmxnet3_get_interrupt_config(s); 1741 break; 1742 1743 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1744 ret = VMXNET3_DISABLE_ADAPTIVE_RING; 1745 break; 1746 1747 case VMXNET3_CMD_GET_DID_LO: 1748 ret = PCI_DEVICE_ID_VMWARE_VMXNET3; 1749 break; 1750 1751 case VMXNET3_CMD_GET_DID_HI: 1752 ret = VMXNET3_DEVICE_REVISION; 1753 break; 1754 1755 default: 1756 VMW_WRPRN("Received request for unknown command: %x", s->last_command); 1757 ret = 0; 1758 break; 1759 } 1760 1761 return ret; 1762 } 1763 1764 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val) 1765 { 1766 uint32_t events; 1767 1768 VMW_CBPRN("Setting events: 0x%x", val); 1769 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val; 1770 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events); 1771 } 1772 1773 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val) 1774 { 1775 uint32_t events; 1776 1777 VMW_CBPRN("Clearing events: 0x%x", val); 1778 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val; 1779 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events); 1780 } 1781 1782 static void 1783 vmxnet3_io_bar1_write(void *opaque, 1784 hwaddr addr, 1785 uint64_t val, 1786 unsigned size) 1787 { 1788 VMXNET3State *s = opaque; 1789 1790 switch (addr) { 1791 /* Vmxnet3 Revision Report Selection */ 1792 case VMXNET3_REG_VRRS: 1793 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d", 1794 val, size); 1795 break; 1796 1797 /* UPT Version Report Selection */ 1798 case VMXNET3_REG_UVRS: 1799 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d", 1800 val, size); 1801 break; 1802 1803 /* Driver Shared Address Low */ 1804 case VMXNET3_REG_DSAL: 1805 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d", 1806 val, size); 1807 /* 1808 * Guest driver will first write the low part of the shared 1809 * memory address. We save it to temp variable and set the 1810 * shared address only after we get the high part 1811 */ 1812 if (val == 0) { 1813 vmxnet3_deactivate_device(s); 1814 } 1815 s->temp_shared_guest_driver_memory = val; 1816 s->drv_shmem = 0; 1817 break; 1818 1819 /* Driver Shared Address High */ 1820 case VMXNET3_REG_DSAH: 1821 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d", 1822 val, size); 1823 /* 1824 * Set the shared memory between guest driver and device. 1825 * We already should have low address part. 1826 */ 1827 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32); 1828 break; 1829 1830 /* Command */ 1831 case VMXNET3_REG_CMD: 1832 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d", 1833 val, size); 1834 vmxnet3_handle_command(s, val); 1835 break; 1836 1837 /* MAC Address Low */ 1838 case VMXNET3_REG_MACL: 1839 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d", 1840 val, size); 1841 s->temp_mac = val; 1842 break; 1843 1844 /* MAC Address High */ 1845 case VMXNET3_REG_MACH: 1846 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d", 1847 val, size); 1848 vmxnet3_set_variable_mac(s, val, s->temp_mac); 1849 break; 1850 1851 /* Interrupt Cause Register */ 1852 case VMXNET3_REG_ICR: 1853 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d", 1854 val, size); 1855 g_assert_not_reached(); 1856 break; 1857 1858 /* Event Cause Register */ 1859 case VMXNET3_REG_ECR: 1860 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d", 1861 val, size); 1862 vmxnet3_ack_events(s, val); 1863 break; 1864 1865 default: 1866 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d", 1867 addr, val, size); 1868 break; 1869 } 1870 } 1871 1872 static uint64_t 1873 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size) 1874 { 1875 VMXNET3State *s = opaque; 1876 uint64_t ret = 0; 1877 1878 switch (addr) { 1879 /* Vmxnet3 Revision Report Selection */ 1880 case VMXNET3_REG_VRRS: 1881 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size); 1882 ret = VMXNET3_DEVICE_REVISION; 1883 break; 1884 1885 /* UPT Version Report Selection */ 1886 case VMXNET3_REG_UVRS: 1887 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size); 1888 ret = VMXNET3_UPT_REVISION; 1889 break; 1890 1891 /* Command */ 1892 case VMXNET3_REG_CMD: 1893 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size); 1894 ret = vmxnet3_get_command_status(s); 1895 break; 1896 1897 /* MAC Address Low */ 1898 case VMXNET3_REG_MACL: 1899 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size); 1900 ret = vmxnet3_get_mac_low(&s->conf.macaddr); 1901 break; 1902 1903 /* MAC Address High */ 1904 case VMXNET3_REG_MACH: 1905 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size); 1906 ret = vmxnet3_get_mac_high(&s->conf.macaddr); 1907 break; 1908 1909 /* 1910 * Interrupt Cause Register 1911 * Used for legacy interrupts only so interrupt index always 0 1912 */ 1913 case VMXNET3_REG_ICR: 1914 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size); 1915 if (vmxnet3_interrupt_asserted(s, 0)) { 1916 vmxnet3_clear_interrupt(s, 0); 1917 ret = true; 1918 } else { 1919 ret = false; 1920 } 1921 break; 1922 1923 default: 1924 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size); 1925 break; 1926 } 1927 1928 return ret; 1929 } 1930 1931 static int 1932 vmxnet3_can_receive(NetClientState *nc) 1933 { 1934 VMXNET3State *s = qemu_get_nic_opaque(nc); 1935 return s->device_active && 1936 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP); 1937 } 1938 1939 static inline bool 1940 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data) 1941 { 1942 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK; 1943 if (IS_SPECIAL_VLAN_ID(vlan_tag)) { 1944 return true; 1945 } 1946 1947 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag); 1948 } 1949 1950 static bool 1951 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac) 1952 { 1953 int i; 1954 for (i = 0; i < s->mcast_list_len; i++) { 1955 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) { 1956 return true; 1957 } 1958 } 1959 return false; 1960 } 1961 1962 static bool 1963 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data, 1964 size_t size) 1965 { 1966 struct eth_header *ehdr = PKT_GET_ETH_HDR(data); 1967 1968 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) { 1969 return true; 1970 } 1971 1972 if (!vmxnet3_is_registered_vlan(s, data)) { 1973 return false; 1974 } 1975 1976 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 1977 case ETH_PKT_UCAST: 1978 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) { 1979 return false; 1980 } 1981 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) { 1982 return false; 1983 } 1984 break; 1985 1986 case ETH_PKT_BCAST: 1987 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) { 1988 return false; 1989 } 1990 break; 1991 1992 case ETH_PKT_MCAST: 1993 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) { 1994 return true; 1995 } 1996 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) { 1997 return false; 1998 } 1999 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) { 2000 return false; 2001 } 2002 break; 2003 2004 default: 2005 g_assert_not_reached(); 2006 } 2007 2008 return true; 2009 } 2010 2011 static ssize_t 2012 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size) 2013 { 2014 VMXNET3State *s = qemu_get_nic_opaque(nc); 2015 size_t bytes_indicated; 2016 uint8_t min_buf[MIN_BUF_SIZE]; 2017 2018 if (!vmxnet3_can_receive(nc)) { 2019 VMW_PKPRN("Cannot receive now"); 2020 return -1; 2021 } 2022 2023 if (s->peer_has_vhdr) { 2024 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf); 2025 buf += sizeof(struct virtio_net_hdr); 2026 size -= sizeof(struct virtio_net_hdr); 2027 } 2028 2029 /* Pad to minimum Ethernet frame length */ 2030 if (size < sizeof(min_buf)) { 2031 memcpy(min_buf, buf, size); 2032 memset(&min_buf[size], 0, sizeof(min_buf) - size); 2033 buf = min_buf; 2034 size = sizeof(min_buf); 2035 } 2036 2037 net_rx_pkt_set_packet_type(s->rx_pkt, 2038 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 2039 2040 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) { 2041 net_rx_pkt_set_protocols(s->rx_pkt, buf, size); 2042 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size); 2043 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping); 2044 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1; 2045 if (bytes_indicated < size) { 2046 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size); 2047 } 2048 } else { 2049 VMW_PKPRN("Packet dropped by RX filter"); 2050 bytes_indicated = size; 2051 } 2052 2053 assert(size > 0); 2054 assert(bytes_indicated != 0); 2055 return bytes_indicated; 2056 } 2057 2058 static void vmxnet3_set_link_status(NetClientState *nc) 2059 { 2060 VMXNET3State *s = qemu_get_nic_opaque(nc); 2061 2062 if (nc->link_down) { 2063 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP; 2064 } else { 2065 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP; 2066 } 2067 2068 vmxnet3_set_events(s, VMXNET3_ECR_LINK); 2069 vmxnet3_trigger_interrupt(s, s->event_int_idx); 2070 } 2071 2072 static NetClientInfo net_vmxnet3_info = { 2073 .type = NET_CLIENT_OPTIONS_KIND_NIC, 2074 .size = sizeof(NICState), 2075 .receive = vmxnet3_receive, 2076 .link_status_changed = vmxnet3_set_link_status, 2077 }; 2078 2079 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s) 2080 { 2081 NetClientState *nc = qemu_get_queue(s->nic); 2082 2083 if (qemu_has_vnet_hdr(nc->peer)) { 2084 return true; 2085 } 2086 2087 return false; 2088 } 2089 2090 static void vmxnet3_net_uninit(VMXNET3State *s) 2091 { 2092 g_free(s->mcast_list); 2093 vmxnet3_deactivate_device(s); 2094 qemu_del_nic(s->nic); 2095 } 2096 2097 static void vmxnet3_net_init(VMXNET3State *s) 2098 { 2099 DeviceState *d = DEVICE(s); 2100 2101 VMW_CBPRN("vmxnet3_net_init called..."); 2102 2103 qemu_macaddr_default_if_unset(&s->conf.macaddr); 2104 2105 /* Windows guest will query the address that was set on init */ 2106 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a)); 2107 2108 s->mcast_list = NULL; 2109 s->mcast_list_len = 0; 2110 2111 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP; 2112 2113 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a)); 2114 2115 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf, 2116 object_get_typename(OBJECT(s)), 2117 d->id, s); 2118 2119 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s); 2120 s->tx_sop = true; 2121 s->skip_current_tx_pkt = false; 2122 s->tx_pkt = NULL; 2123 s->rx_pkt = NULL; 2124 s->rx_vlan_stripping = false; 2125 s->lro_supported = false; 2126 2127 if (s->peer_has_vhdr) { 2128 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer, 2129 sizeof(struct virtio_net_hdr)); 2130 2131 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1); 2132 } 2133 2134 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 2135 } 2136 2137 static void 2138 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors) 2139 { 2140 PCIDevice *d = PCI_DEVICE(s); 2141 int i; 2142 for (i = 0; i < num_vectors; i++) { 2143 msix_vector_unuse(d, i); 2144 } 2145 } 2146 2147 static bool 2148 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors) 2149 { 2150 PCIDevice *d = PCI_DEVICE(s); 2151 int i; 2152 for (i = 0; i < num_vectors; i++) { 2153 int res = msix_vector_use(d, i); 2154 if (0 > res) { 2155 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res); 2156 vmxnet3_unuse_msix_vectors(s, i); 2157 return false; 2158 } 2159 } 2160 return true; 2161 } 2162 2163 static bool 2164 vmxnet3_init_msix(VMXNET3State *s) 2165 { 2166 PCIDevice *d = PCI_DEVICE(s); 2167 int res = msix_init(d, VMXNET3_MAX_INTRS, 2168 &s->msix_bar, 2169 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE, 2170 &s->msix_bar, 2171 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s), 2172 VMXNET3_MSIX_OFFSET(s)); 2173 2174 if (0 > res) { 2175 VMW_WRPRN("Failed to initialize MSI-X, error %d", res); 2176 s->msix_used = false; 2177 } else { 2178 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { 2179 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res); 2180 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2181 s->msix_used = false; 2182 } else { 2183 s->msix_used = true; 2184 } 2185 } 2186 return s->msix_used; 2187 } 2188 2189 static void 2190 vmxnet3_cleanup_msix(VMXNET3State *s) 2191 { 2192 PCIDevice *d = PCI_DEVICE(s); 2193 2194 if (s->msix_used) { 2195 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS); 2196 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2197 } 2198 } 2199 2200 #define VMXNET3_USE_64BIT (true) 2201 #define VMXNET3_PER_VECTOR_MASK (false) 2202 2203 static bool 2204 vmxnet3_init_msi(VMXNET3State *s) 2205 { 2206 PCIDevice *d = PCI_DEVICE(s); 2207 int res; 2208 2209 res = msi_init(d, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS, 2210 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK); 2211 if (0 > res) { 2212 VMW_WRPRN("Failed to initialize MSI, error %d", res); 2213 s->msi_used = false; 2214 } else { 2215 s->msi_used = true; 2216 } 2217 2218 return s->msi_used; 2219 } 2220 2221 static void 2222 vmxnet3_cleanup_msi(VMXNET3State *s) 2223 { 2224 PCIDevice *d = PCI_DEVICE(s); 2225 2226 if (s->msi_used) { 2227 msi_uninit(d); 2228 } 2229 } 2230 2231 static void 2232 vmxnet3_msix_save(QEMUFile *f, void *opaque) 2233 { 2234 PCIDevice *d = PCI_DEVICE(opaque); 2235 msix_save(d, f); 2236 } 2237 2238 static int 2239 vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id) 2240 { 2241 PCIDevice *d = PCI_DEVICE(opaque); 2242 msix_load(d, f); 2243 return 0; 2244 } 2245 2246 static const MemoryRegionOps b0_ops = { 2247 .read = vmxnet3_io_bar0_read, 2248 .write = vmxnet3_io_bar0_write, 2249 .endianness = DEVICE_LITTLE_ENDIAN, 2250 .impl = { 2251 .min_access_size = 4, 2252 .max_access_size = 4, 2253 }, 2254 }; 2255 2256 static const MemoryRegionOps b1_ops = { 2257 .read = vmxnet3_io_bar1_read, 2258 .write = vmxnet3_io_bar1_write, 2259 .endianness = DEVICE_LITTLE_ENDIAN, 2260 .impl = { 2261 .min_access_size = 4, 2262 .max_access_size = 4, 2263 }, 2264 }; 2265 2266 static uint64_t vmxnet3_device_serial_num(VMXNET3State *s) 2267 { 2268 uint64_t dsn_payload; 2269 uint8_t *dsnp = (uint8_t *)&dsn_payload; 2270 2271 dsnp[0] = 0xfe; 2272 dsnp[1] = s->conf.macaddr.a[3]; 2273 dsnp[2] = s->conf.macaddr.a[4]; 2274 dsnp[3] = s->conf.macaddr.a[5]; 2275 dsnp[4] = s->conf.macaddr.a[0]; 2276 dsnp[5] = s->conf.macaddr.a[1]; 2277 dsnp[6] = s->conf.macaddr.a[2]; 2278 dsnp[7] = 0xff; 2279 return dsn_payload; 2280 } 2281 2282 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp) 2283 { 2284 DeviceState *dev = DEVICE(pci_dev); 2285 VMXNET3State *s = VMXNET3(pci_dev); 2286 2287 VMW_CBPRN("Starting init..."); 2288 2289 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s, 2290 "vmxnet3-b0", VMXNET3_PT_REG_SIZE); 2291 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX, 2292 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 2293 2294 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s, 2295 "vmxnet3-b1", VMXNET3_VD_REG_SIZE); 2296 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX, 2297 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); 2298 2299 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar", 2300 VMXNET3_MSIX_BAR_SIZE); 2301 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX, 2302 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar); 2303 2304 vmxnet3_reset_interrupt_states(s); 2305 2306 /* Interrupt pin A */ 2307 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01; 2308 2309 if (!vmxnet3_init_msix(s)) { 2310 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent."); 2311 } 2312 2313 if (!vmxnet3_init_msi(s)) { 2314 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent."); 2315 } 2316 2317 vmxnet3_net_init(s); 2318 2319 if (pci_is_express(pci_dev)) { 2320 if (pci_bus_is_express(pci_dev->bus)) { 2321 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET); 2322 } 2323 2324 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET, 2325 vmxnet3_device_serial_num(s)); 2326 } 2327 2328 register_savevm(dev, "vmxnet3-msix", -1, 1, 2329 vmxnet3_msix_save, vmxnet3_msix_load, s); 2330 } 2331 2332 static void vmxnet3_instance_init(Object *obj) 2333 { 2334 VMXNET3State *s = VMXNET3(obj); 2335 device_add_bootindex_property(obj, &s->conf.bootindex, 2336 "bootindex", "/ethernet-phy@0", 2337 DEVICE(obj), NULL); 2338 } 2339 2340 static void vmxnet3_pci_uninit(PCIDevice *pci_dev) 2341 { 2342 DeviceState *dev = DEVICE(pci_dev); 2343 VMXNET3State *s = VMXNET3(pci_dev); 2344 2345 VMW_CBPRN("Starting uninit..."); 2346 2347 unregister_savevm(dev, "vmxnet3-msix", s); 2348 2349 vmxnet3_net_uninit(s); 2350 2351 vmxnet3_cleanup_msix(s); 2352 2353 vmxnet3_cleanup_msi(s); 2354 } 2355 2356 static void vmxnet3_qdev_reset(DeviceState *dev) 2357 { 2358 PCIDevice *d = PCI_DEVICE(dev); 2359 VMXNET3State *s = VMXNET3(d); 2360 2361 VMW_CBPRN("Starting QDEV reset..."); 2362 vmxnet3_reset(s); 2363 } 2364 2365 static bool vmxnet3_mc_list_needed(void *opaque) 2366 { 2367 return true; 2368 } 2369 2370 static int vmxnet3_mcast_list_pre_load(void *opaque) 2371 { 2372 VMXNET3State *s = opaque; 2373 2374 s->mcast_list = g_malloc(s->mcast_list_buff_size); 2375 2376 return 0; 2377 } 2378 2379 2380 static void vmxnet3_pre_save(void *opaque) 2381 { 2382 VMXNET3State *s = opaque; 2383 2384 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr); 2385 } 2386 2387 static const VMStateDescription vmxstate_vmxnet3_mcast_list = { 2388 .name = "vmxnet3/mcast_list", 2389 .version_id = 1, 2390 .minimum_version_id = 1, 2391 .pre_load = vmxnet3_mcast_list_pre_load, 2392 .needed = vmxnet3_mc_list_needed, 2393 .fields = (VMStateField[]) { 2394 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 0, 2395 mcast_list_buff_size), 2396 VMSTATE_END_OF_LIST() 2397 } 2398 }; 2399 2400 static void vmxnet3_get_ring_from_file(QEMUFile *f, Vmxnet3Ring *r) 2401 { 2402 r->pa = qemu_get_be64(f); 2403 r->size = qemu_get_be32(f); 2404 r->cell_size = qemu_get_be32(f); 2405 r->next = qemu_get_be32(f); 2406 r->gen = qemu_get_byte(f); 2407 } 2408 2409 static void vmxnet3_put_ring_to_file(QEMUFile *f, Vmxnet3Ring *r) 2410 { 2411 qemu_put_be64(f, r->pa); 2412 qemu_put_be32(f, r->size); 2413 qemu_put_be32(f, r->cell_size); 2414 qemu_put_be32(f, r->next); 2415 qemu_put_byte(f, r->gen); 2416 } 2417 2418 static void vmxnet3_get_tx_stats_from_file(QEMUFile *f, 2419 struct UPT1_TxStats *tx_stat) 2420 { 2421 tx_stat->TSOPktsTxOK = qemu_get_be64(f); 2422 tx_stat->TSOBytesTxOK = qemu_get_be64(f); 2423 tx_stat->ucastPktsTxOK = qemu_get_be64(f); 2424 tx_stat->ucastBytesTxOK = qemu_get_be64(f); 2425 tx_stat->mcastPktsTxOK = qemu_get_be64(f); 2426 tx_stat->mcastBytesTxOK = qemu_get_be64(f); 2427 tx_stat->bcastPktsTxOK = qemu_get_be64(f); 2428 tx_stat->bcastBytesTxOK = qemu_get_be64(f); 2429 tx_stat->pktsTxError = qemu_get_be64(f); 2430 tx_stat->pktsTxDiscard = qemu_get_be64(f); 2431 } 2432 2433 static void vmxnet3_put_tx_stats_to_file(QEMUFile *f, 2434 struct UPT1_TxStats *tx_stat) 2435 { 2436 qemu_put_be64(f, tx_stat->TSOPktsTxOK); 2437 qemu_put_be64(f, tx_stat->TSOBytesTxOK); 2438 qemu_put_be64(f, tx_stat->ucastPktsTxOK); 2439 qemu_put_be64(f, tx_stat->ucastBytesTxOK); 2440 qemu_put_be64(f, tx_stat->mcastPktsTxOK); 2441 qemu_put_be64(f, tx_stat->mcastBytesTxOK); 2442 qemu_put_be64(f, tx_stat->bcastPktsTxOK); 2443 qemu_put_be64(f, tx_stat->bcastBytesTxOK); 2444 qemu_put_be64(f, tx_stat->pktsTxError); 2445 qemu_put_be64(f, tx_stat->pktsTxDiscard); 2446 } 2447 2448 static int vmxnet3_get_txq_descr(QEMUFile *f, void *pv, size_t size) 2449 { 2450 Vmxnet3TxqDescr *r = pv; 2451 2452 vmxnet3_get_ring_from_file(f, &r->tx_ring); 2453 vmxnet3_get_ring_from_file(f, &r->comp_ring); 2454 r->intr_idx = qemu_get_byte(f); 2455 r->tx_stats_pa = qemu_get_be64(f); 2456 2457 vmxnet3_get_tx_stats_from_file(f, &r->txq_stats); 2458 2459 return 0; 2460 } 2461 2462 static void vmxnet3_put_txq_descr(QEMUFile *f, void *pv, size_t size) 2463 { 2464 Vmxnet3TxqDescr *r = pv; 2465 2466 vmxnet3_put_ring_to_file(f, &r->tx_ring); 2467 vmxnet3_put_ring_to_file(f, &r->comp_ring); 2468 qemu_put_byte(f, r->intr_idx); 2469 qemu_put_be64(f, r->tx_stats_pa); 2470 vmxnet3_put_tx_stats_to_file(f, &r->txq_stats); 2471 } 2472 2473 static const VMStateInfo txq_descr_info = { 2474 .name = "txq_descr", 2475 .get = vmxnet3_get_txq_descr, 2476 .put = vmxnet3_put_txq_descr 2477 }; 2478 2479 static void vmxnet3_get_rx_stats_from_file(QEMUFile *f, 2480 struct UPT1_RxStats *rx_stat) 2481 { 2482 rx_stat->LROPktsRxOK = qemu_get_be64(f); 2483 rx_stat->LROBytesRxOK = qemu_get_be64(f); 2484 rx_stat->ucastPktsRxOK = qemu_get_be64(f); 2485 rx_stat->ucastBytesRxOK = qemu_get_be64(f); 2486 rx_stat->mcastPktsRxOK = qemu_get_be64(f); 2487 rx_stat->mcastBytesRxOK = qemu_get_be64(f); 2488 rx_stat->bcastPktsRxOK = qemu_get_be64(f); 2489 rx_stat->bcastBytesRxOK = qemu_get_be64(f); 2490 rx_stat->pktsRxOutOfBuf = qemu_get_be64(f); 2491 rx_stat->pktsRxError = qemu_get_be64(f); 2492 } 2493 2494 static void vmxnet3_put_rx_stats_to_file(QEMUFile *f, 2495 struct UPT1_RxStats *rx_stat) 2496 { 2497 qemu_put_be64(f, rx_stat->LROPktsRxOK); 2498 qemu_put_be64(f, rx_stat->LROBytesRxOK); 2499 qemu_put_be64(f, rx_stat->ucastPktsRxOK); 2500 qemu_put_be64(f, rx_stat->ucastBytesRxOK); 2501 qemu_put_be64(f, rx_stat->mcastPktsRxOK); 2502 qemu_put_be64(f, rx_stat->mcastBytesRxOK); 2503 qemu_put_be64(f, rx_stat->bcastPktsRxOK); 2504 qemu_put_be64(f, rx_stat->bcastBytesRxOK); 2505 qemu_put_be64(f, rx_stat->pktsRxOutOfBuf); 2506 qemu_put_be64(f, rx_stat->pktsRxError); 2507 } 2508 2509 static int vmxnet3_get_rxq_descr(QEMUFile *f, void *pv, size_t size) 2510 { 2511 Vmxnet3RxqDescr *r = pv; 2512 int i; 2513 2514 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) { 2515 vmxnet3_get_ring_from_file(f, &r->rx_ring[i]); 2516 } 2517 2518 vmxnet3_get_ring_from_file(f, &r->comp_ring); 2519 r->intr_idx = qemu_get_byte(f); 2520 r->rx_stats_pa = qemu_get_be64(f); 2521 2522 vmxnet3_get_rx_stats_from_file(f, &r->rxq_stats); 2523 2524 return 0; 2525 } 2526 2527 static void vmxnet3_put_rxq_descr(QEMUFile *f, void *pv, size_t size) 2528 { 2529 Vmxnet3RxqDescr *r = pv; 2530 int i; 2531 2532 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) { 2533 vmxnet3_put_ring_to_file(f, &r->rx_ring[i]); 2534 } 2535 2536 vmxnet3_put_ring_to_file(f, &r->comp_ring); 2537 qemu_put_byte(f, r->intr_idx); 2538 qemu_put_be64(f, r->rx_stats_pa); 2539 vmxnet3_put_rx_stats_to_file(f, &r->rxq_stats); 2540 } 2541 2542 static int vmxnet3_post_load(void *opaque, int version_id) 2543 { 2544 VMXNET3State *s = opaque; 2545 PCIDevice *d = PCI_DEVICE(s); 2546 2547 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), 2548 s->max_tx_frags, s->peer_has_vhdr); 2549 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); 2550 2551 if (s->msix_used) { 2552 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { 2553 VMW_WRPRN("Failed to re-use MSI-X vectors"); 2554 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2555 s->msix_used = false; 2556 return -1; 2557 } 2558 } 2559 2560 vmxnet3_validate_queues(s); 2561 vmxnet3_validate_interrupts(s); 2562 2563 return 0; 2564 } 2565 2566 static const VMStateInfo rxq_descr_info = { 2567 .name = "rxq_descr", 2568 .get = vmxnet3_get_rxq_descr, 2569 .put = vmxnet3_put_rxq_descr 2570 }; 2571 2572 static int vmxnet3_get_int_state(QEMUFile *f, void *pv, size_t size) 2573 { 2574 Vmxnet3IntState *r = pv; 2575 2576 r->is_masked = qemu_get_byte(f); 2577 r->is_pending = qemu_get_byte(f); 2578 r->is_asserted = qemu_get_byte(f); 2579 2580 return 0; 2581 } 2582 2583 static void vmxnet3_put_int_state(QEMUFile *f, void *pv, size_t size) 2584 { 2585 Vmxnet3IntState *r = pv; 2586 2587 qemu_put_byte(f, r->is_masked); 2588 qemu_put_byte(f, r->is_pending); 2589 qemu_put_byte(f, r->is_asserted); 2590 } 2591 2592 static const VMStateInfo int_state_info = { 2593 .name = "int_state", 2594 .get = vmxnet3_get_int_state, 2595 .put = vmxnet3_put_int_state 2596 }; 2597 2598 static bool vmxnet3_vmstate_need_pcie_device(void *opaque) 2599 { 2600 VMXNET3State *s = VMXNET3(opaque); 2601 2602 return !(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE); 2603 } 2604 2605 static bool vmxnet3_vmstate_test_pci_device(void *opaque, int version_id) 2606 { 2607 return !vmxnet3_vmstate_need_pcie_device(opaque); 2608 } 2609 2610 static const VMStateDescription vmstate_vmxnet3_pcie_device = { 2611 .name = "vmxnet3/pcie", 2612 .version_id = 1, 2613 .minimum_version_id = 1, 2614 .needed = vmxnet3_vmstate_need_pcie_device, 2615 .fields = (VMStateField[]) { 2616 VMSTATE_PCIE_DEVICE(parent_obj, VMXNET3State), 2617 VMSTATE_END_OF_LIST() 2618 } 2619 }; 2620 2621 static const VMStateDescription vmstate_vmxnet3 = { 2622 .name = "vmxnet3", 2623 .version_id = 1, 2624 .minimum_version_id = 1, 2625 .pre_save = vmxnet3_pre_save, 2626 .post_load = vmxnet3_post_load, 2627 .fields = (VMStateField[]) { 2628 VMSTATE_STRUCT_TEST(parent_obj, VMXNET3State, 2629 vmxnet3_vmstate_test_pci_device, 0, 2630 vmstate_pci_device, PCIDevice), 2631 VMSTATE_BOOL(rx_packets_compound, VMXNET3State), 2632 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State), 2633 VMSTATE_BOOL(lro_supported, VMXNET3State), 2634 VMSTATE_UINT32(rx_mode, VMXNET3State), 2635 VMSTATE_UINT32(mcast_list_len, VMXNET3State), 2636 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State), 2637 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE), 2638 VMSTATE_UINT32(mtu, VMXNET3State), 2639 VMSTATE_UINT16(max_rx_frags, VMXNET3State), 2640 VMSTATE_UINT32(max_tx_frags, VMXNET3State), 2641 VMSTATE_UINT8(event_int_idx, VMXNET3State), 2642 VMSTATE_BOOL(auto_int_masking, VMXNET3State), 2643 VMSTATE_UINT8(txq_num, VMXNET3State), 2644 VMSTATE_UINT8(rxq_num, VMXNET3State), 2645 VMSTATE_UINT32(device_active, VMXNET3State), 2646 VMSTATE_UINT32(last_command, VMXNET3State), 2647 VMSTATE_UINT32(link_status_and_speed, VMXNET3State), 2648 VMSTATE_UINT32(temp_mac, VMXNET3State), 2649 VMSTATE_UINT64(drv_shmem, VMXNET3State), 2650 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State), 2651 2652 VMSTATE_ARRAY(txq_descr, VMXNET3State, 2653 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, txq_descr_info, 2654 Vmxnet3TxqDescr), 2655 VMSTATE_ARRAY(rxq_descr, VMXNET3State, 2656 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, rxq_descr_info, 2657 Vmxnet3RxqDescr), 2658 VMSTATE_ARRAY(interrupt_states, VMXNET3State, VMXNET3_MAX_INTRS, 2659 0, int_state_info, Vmxnet3IntState), 2660 2661 VMSTATE_END_OF_LIST() 2662 }, 2663 .subsections = (const VMStateDescription*[]) { 2664 &vmxstate_vmxnet3_mcast_list, 2665 &vmstate_vmxnet3_pcie_device, 2666 NULL 2667 } 2668 }; 2669 2670 static Property vmxnet3_properties[] = { 2671 DEFINE_NIC_PROPERTIES(VMXNET3State, conf), 2672 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags, 2673 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false), 2674 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags, 2675 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false), 2676 DEFINE_PROP_END_OF_LIST(), 2677 }; 2678 2679 static void vmxnet3_realize(DeviceState *qdev, Error **errp) 2680 { 2681 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev); 2682 PCIDevice *pci_dev = PCI_DEVICE(qdev); 2683 VMXNET3State *s = VMXNET3(qdev); 2684 2685 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) { 2686 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2687 } 2688 2689 vc->parent_dc_realize(qdev, errp); 2690 } 2691 2692 static void vmxnet3_class_init(ObjectClass *class, void *data) 2693 { 2694 DeviceClass *dc = DEVICE_CLASS(class); 2695 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 2696 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class); 2697 2698 c->realize = vmxnet3_pci_realize; 2699 c->exit = vmxnet3_pci_uninit; 2700 c->vendor_id = PCI_VENDOR_ID_VMWARE; 2701 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2702 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION; 2703 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 2704 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 2705 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2706 vc->parent_dc_realize = dc->realize; 2707 dc->realize = vmxnet3_realize; 2708 dc->desc = "VMWare Paravirtualized Ethernet v3"; 2709 dc->reset = vmxnet3_qdev_reset; 2710 dc->vmsd = &vmstate_vmxnet3; 2711 dc->props = vmxnet3_properties; 2712 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2713 } 2714 2715 static const TypeInfo vmxnet3_info = { 2716 .name = TYPE_VMXNET3, 2717 .parent = TYPE_PCI_DEVICE, 2718 .class_size = sizeof(VMXNET3Class), 2719 .instance_size = sizeof(VMXNET3State), 2720 .class_init = vmxnet3_class_init, 2721 .instance_init = vmxnet3_instance_init, 2722 }; 2723 2724 static void vmxnet3_register_types(void) 2725 { 2726 VMW_CBPRN("vmxnet3_register_types called..."); 2727 type_register_static(&vmxnet3_info); 2728 } 2729 2730 type_init(vmxnet3_register_types) 2731