1*49ab747fSPaolo Bonzini /* 2*49ab747fSPaolo Bonzini * QEMU model of XGMAC Ethernet. 3*49ab747fSPaolo Bonzini * 4*49ab747fSPaolo Bonzini * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias. 5*49ab747fSPaolo Bonzini * 6*49ab747fSPaolo Bonzini * Copyright (c) 2011 Calxeda, Inc. 7*49ab747fSPaolo Bonzini * 8*49ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 9*49ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 10*49ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 11*49ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12*49ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 13*49ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 14*49ab747fSPaolo Bonzini * 15*49ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 16*49ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 17*49ab747fSPaolo Bonzini * 18*49ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19*49ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20*49ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21*49ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22*49ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23*49ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24*49ab747fSPaolo Bonzini * THE SOFTWARE. 25*49ab747fSPaolo Bonzini */ 26*49ab747fSPaolo Bonzini 27*49ab747fSPaolo Bonzini #include "hw/sysbus.h" 28*49ab747fSPaolo Bonzini #include "char/char.h" 29*49ab747fSPaolo Bonzini #include "qemu/log.h" 30*49ab747fSPaolo Bonzini #include "net/net.h" 31*49ab747fSPaolo Bonzini #include "net/checksum.h" 32*49ab747fSPaolo Bonzini 33*49ab747fSPaolo Bonzini #ifdef DEBUG_XGMAC 34*49ab747fSPaolo Bonzini #define DEBUGF_BRK(message, args...) do { \ 35*49ab747fSPaolo Bonzini fprintf(stderr, (message), ## args); \ 36*49ab747fSPaolo Bonzini } while (0) 37*49ab747fSPaolo Bonzini #else 38*49ab747fSPaolo Bonzini #define DEBUGF_BRK(message, args...) do { } while (0) 39*49ab747fSPaolo Bonzini #endif 40*49ab747fSPaolo Bonzini 41*49ab747fSPaolo Bonzini #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */ 42*49ab747fSPaolo Bonzini #define XGMAC_FRAME_FILTER 0x00000001 /* MAC Frame Filter */ 43*49ab747fSPaolo Bonzini #define XGMAC_FLOW_CTRL 0x00000006 /* MAC Flow Control */ 44*49ab747fSPaolo Bonzini #define XGMAC_VLAN_TAG 0x00000007 /* VLAN Tags */ 45*49ab747fSPaolo Bonzini #define XGMAC_VERSION 0x00000008 /* Version */ 46*49ab747fSPaolo Bonzini /* VLAN tag for insertion or replacement into tx frames */ 47*49ab747fSPaolo Bonzini #define XGMAC_VLAN_INCL 0x00000009 48*49ab747fSPaolo Bonzini #define XGMAC_LPI_CTRL 0x0000000a /* LPI Control and Status */ 49*49ab747fSPaolo Bonzini #define XGMAC_LPI_TIMER 0x0000000b /* LPI Timers Control */ 50*49ab747fSPaolo Bonzini #define XGMAC_TX_PACE 0x0000000c /* Transmit Pace and Stretch */ 51*49ab747fSPaolo Bonzini #define XGMAC_VLAN_HASH 0x0000000d /* VLAN Hash Table */ 52*49ab747fSPaolo Bonzini #define XGMAC_DEBUG 0x0000000e /* Debug */ 53*49ab747fSPaolo Bonzini #define XGMAC_INT_STATUS 0x0000000f /* Interrupt and Control */ 54*49ab747fSPaolo Bonzini /* HASH table registers */ 55*49ab747fSPaolo Bonzini #define XGMAC_HASH(n) ((0x00000300/4) + (n)) 56*49ab747fSPaolo Bonzini #define XGMAC_NUM_HASH 16 57*49ab747fSPaolo Bonzini /* Operation Mode */ 58*49ab747fSPaolo Bonzini #define XGMAC_OPMODE (0x00000400/4) 59*49ab747fSPaolo Bonzini /* Remote Wake-Up Frame Filter */ 60*49ab747fSPaolo Bonzini #define XGMAC_REMOTE_WAKE (0x00000700/4) 61*49ab747fSPaolo Bonzini /* PMT Control and Status */ 62*49ab747fSPaolo Bonzini #define XGMAC_PMT (0x00000704/4) 63*49ab747fSPaolo Bonzini 64*49ab747fSPaolo Bonzini #define XGMAC_ADDR_HIGH(reg) (0x00000010+((reg) * 2)) 65*49ab747fSPaolo Bonzini #define XGMAC_ADDR_LOW(reg) (0x00000011+((reg) * 2)) 66*49ab747fSPaolo Bonzini 67*49ab747fSPaolo Bonzini #define DMA_BUS_MODE 0x000003c0 /* Bus Mode */ 68*49ab747fSPaolo Bonzini #define DMA_XMT_POLL_DEMAND 0x000003c1 /* Transmit Poll Demand */ 69*49ab747fSPaolo Bonzini #define DMA_RCV_POLL_DEMAND 0x000003c2 /* Received Poll Demand */ 70*49ab747fSPaolo Bonzini #define DMA_RCV_BASE_ADDR 0x000003c3 /* Receive List Base */ 71*49ab747fSPaolo Bonzini #define DMA_TX_BASE_ADDR 0x000003c4 /* Transmit List Base */ 72*49ab747fSPaolo Bonzini #define DMA_STATUS 0x000003c5 /* Status Register */ 73*49ab747fSPaolo Bonzini #define DMA_CONTROL 0x000003c6 /* Ctrl (Operational Mode) */ 74*49ab747fSPaolo Bonzini #define DMA_INTR_ENA 0x000003c7 /* Interrupt Enable */ 75*49ab747fSPaolo Bonzini #define DMA_MISSED_FRAME_CTR 0x000003c8 /* Missed Frame Counter */ 76*49ab747fSPaolo Bonzini /* Receive Interrupt Watchdog Timer */ 77*49ab747fSPaolo Bonzini #define DMA_RI_WATCHDOG_TIMER 0x000003c9 78*49ab747fSPaolo Bonzini #define DMA_AXI_BUS 0x000003ca /* AXI Bus Mode */ 79*49ab747fSPaolo Bonzini #define DMA_AXI_STATUS 0x000003cb /* AXI Status */ 80*49ab747fSPaolo Bonzini #define DMA_CUR_TX_DESC_ADDR 0x000003d2 /* Current Host Tx Descriptor */ 81*49ab747fSPaolo Bonzini #define DMA_CUR_RX_DESC_ADDR 0x000003d3 /* Current Host Rx Descriptor */ 82*49ab747fSPaolo Bonzini #define DMA_CUR_TX_BUF_ADDR 0x000003d4 /* Current Host Tx Buffer */ 83*49ab747fSPaolo Bonzini #define DMA_CUR_RX_BUF_ADDR 0x000003d5 /* Current Host Rx Buffer */ 84*49ab747fSPaolo Bonzini #define DMA_HW_FEATURE 0x000003d6 /* Enabled Hardware Features */ 85*49ab747fSPaolo Bonzini 86*49ab747fSPaolo Bonzini /* DMA Status register defines */ 87*49ab747fSPaolo Bonzini #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ 88*49ab747fSPaolo Bonzini #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */ 89*49ab747fSPaolo Bonzini #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ 90*49ab747fSPaolo Bonzini #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ 91*49ab747fSPaolo Bonzini #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ 92*49ab747fSPaolo Bonzini #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ 93*49ab747fSPaolo Bonzini #define DMA_STATUS_TS_SHIFT 20 94*49ab747fSPaolo Bonzini #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ 95*49ab747fSPaolo Bonzini #define DMA_STATUS_RS_SHIFT 17 96*49ab747fSPaolo Bonzini #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ 97*49ab747fSPaolo Bonzini #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ 98*49ab747fSPaolo Bonzini #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ 99*49ab747fSPaolo Bonzini #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ 100*49ab747fSPaolo Bonzini #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ 101*49ab747fSPaolo Bonzini #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ 102*49ab747fSPaolo Bonzini #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ 103*49ab747fSPaolo Bonzini #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ 104*49ab747fSPaolo Bonzini #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ 105*49ab747fSPaolo Bonzini #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ 106*49ab747fSPaolo Bonzini #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ 107*49ab747fSPaolo Bonzini #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ 108*49ab747fSPaolo Bonzini #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */ 109*49ab747fSPaolo Bonzini #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ 110*49ab747fSPaolo Bonzini #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ 111*49ab747fSPaolo Bonzini 112*49ab747fSPaolo Bonzini /* DMA Control register defines */ 113*49ab747fSPaolo Bonzini #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ 114*49ab747fSPaolo Bonzini #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ 115*49ab747fSPaolo Bonzini #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */ 116*49ab747fSPaolo Bonzini 117*49ab747fSPaolo Bonzini struct desc { 118*49ab747fSPaolo Bonzini uint32_t ctl_stat; 119*49ab747fSPaolo Bonzini uint16_t buffer1_size; 120*49ab747fSPaolo Bonzini uint16_t buffer2_size; 121*49ab747fSPaolo Bonzini uint32_t buffer1_addr; 122*49ab747fSPaolo Bonzini uint32_t buffer2_addr; 123*49ab747fSPaolo Bonzini uint32_t ext_stat; 124*49ab747fSPaolo Bonzini uint32_t res[3]; 125*49ab747fSPaolo Bonzini }; 126*49ab747fSPaolo Bonzini 127*49ab747fSPaolo Bonzini #define R_MAX 0x400 128*49ab747fSPaolo Bonzini 129*49ab747fSPaolo Bonzini typedef struct RxTxStats { 130*49ab747fSPaolo Bonzini uint64_t rx_bytes; 131*49ab747fSPaolo Bonzini uint64_t tx_bytes; 132*49ab747fSPaolo Bonzini 133*49ab747fSPaolo Bonzini uint64_t rx; 134*49ab747fSPaolo Bonzini uint64_t rx_bcast; 135*49ab747fSPaolo Bonzini uint64_t rx_mcast; 136*49ab747fSPaolo Bonzini } RxTxStats; 137*49ab747fSPaolo Bonzini 138*49ab747fSPaolo Bonzini typedef struct XgmacState { 139*49ab747fSPaolo Bonzini SysBusDevice busdev; 140*49ab747fSPaolo Bonzini MemoryRegion iomem; 141*49ab747fSPaolo Bonzini qemu_irq sbd_irq; 142*49ab747fSPaolo Bonzini qemu_irq pmt_irq; 143*49ab747fSPaolo Bonzini qemu_irq mci_irq; 144*49ab747fSPaolo Bonzini NICState *nic; 145*49ab747fSPaolo Bonzini NICConf conf; 146*49ab747fSPaolo Bonzini 147*49ab747fSPaolo Bonzini struct RxTxStats stats; 148*49ab747fSPaolo Bonzini uint32_t regs[R_MAX]; 149*49ab747fSPaolo Bonzini } XgmacState; 150*49ab747fSPaolo Bonzini 151*49ab747fSPaolo Bonzini const VMStateDescription vmstate_rxtx_stats = { 152*49ab747fSPaolo Bonzini .name = "xgmac_stats", 153*49ab747fSPaolo Bonzini .version_id = 1, 154*49ab747fSPaolo Bonzini .minimum_version_id = 1, 155*49ab747fSPaolo Bonzini .fields = (VMStateField[]) { 156*49ab747fSPaolo Bonzini VMSTATE_UINT64(rx_bytes, RxTxStats), 157*49ab747fSPaolo Bonzini VMSTATE_UINT64(tx_bytes, RxTxStats), 158*49ab747fSPaolo Bonzini VMSTATE_UINT64(rx, RxTxStats), 159*49ab747fSPaolo Bonzini VMSTATE_UINT64(rx_bcast, RxTxStats), 160*49ab747fSPaolo Bonzini VMSTATE_UINT64(rx_mcast, RxTxStats), 161*49ab747fSPaolo Bonzini VMSTATE_END_OF_LIST() 162*49ab747fSPaolo Bonzini } 163*49ab747fSPaolo Bonzini }; 164*49ab747fSPaolo Bonzini 165*49ab747fSPaolo Bonzini static const VMStateDescription vmstate_xgmac = { 166*49ab747fSPaolo Bonzini .name = "xgmac", 167*49ab747fSPaolo Bonzini .version_id = 1, 168*49ab747fSPaolo Bonzini .minimum_version_id = 1, 169*49ab747fSPaolo Bonzini .fields = (VMStateField[]) { 170*49ab747fSPaolo Bonzini VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats), 171*49ab747fSPaolo Bonzini VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX), 172*49ab747fSPaolo Bonzini VMSTATE_END_OF_LIST() 173*49ab747fSPaolo Bonzini } 174*49ab747fSPaolo Bonzini }; 175*49ab747fSPaolo Bonzini 176*49ab747fSPaolo Bonzini static void xgmac_read_desc(struct XgmacState *s, struct desc *d, int rx) 177*49ab747fSPaolo Bonzini { 178*49ab747fSPaolo Bonzini uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] : 179*49ab747fSPaolo Bonzini s->regs[DMA_CUR_TX_DESC_ADDR]; 180*49ab747fSPaolo Bonzini cpu_physical_memory_read(addr, d, sizeof(*d)); 181*49ab747fSPaolo Bonzini } 182*49ab747fSPaolo Bonzini 183*49ab747fSPaolo Bonzini static void xgmac_write_desc(struct XgmacState *s, struct desc *d, int rx) 184*49ab747fSPaolo Bonzini { 185*49ab747fSPaolo Bonzini int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR; 186*49ab747fSPaolo Bonzini uint32_t addr = s->regs[reg]; 187*49ab747fSPaolo Bonzini 188*49ab747fSPaolo Bonzini if (!rx && (d->ctl_stat & 0x00200000)) { 189*49ab747fSPaolo Bonzini s->regs[reg] = s->regs[DMA_TX_BASE_ADDR]; 190*49ab747fSPaolo Bonzini } else if (rx && (d->buffer1_size & 0x8000)) { 191*49ab747fSPaolo Bonzini s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR]; 192*49ab747fSPaolo Bonzini } else { 193*49ab747fSPaolo Bonzini s->regs[reg] += sizeof(*d); 194*49ab747fSPaolo Bonzini } 195*49ab747fSPaolo Bonzini cpu_physical_memory_write(addr, d, sizeof(*d)); 196*49ab747fSPaolo Bonzini } 197*49ab747fSPaolo Bonzini 198*49ab747fSPaolo Bonzini static void xgmac_enet_send(struct XgmacState *s) 199*49ab747fSPaolo Bonzini { 200*49ab747fSPaolo Bonzini struct desc bd; 201*49ab747fSPaolo Bonzini int frame_size; 202*49ab747fSPaolo Bonzini int len; 203*49ab747fSPaolo Bonzini uint8_t frame[8192]; 204*49ab747fSPaolo Bonzini uint8_t *ptr; 205*49ab747fSPaolo Bonzini 206*49ab747fSPaolo Bonzini ptr = frame; 207*49ab747fSPaolo Bonzini frame_size = 0; 208*49ab747fSPaolo Bonzini while (1) { 209*49ab747fSPaolo Bonzini xgmac_read_desc(s, &bd, 0); 210*49ab747fSPaolo Bonzini if ((bd.ctl_stat & 0x80000000) == 0) { 211*49ab747fSPaolo Bonzini /* Run out of descriptors to transmit. */ 212*49ab747fSPaolo Bonzini break; 213*49ab747fSPaolo Bonzini } 214*49ab747fSPaolo Bonzini len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff); 215*49ab747fSPaolo Bonzini 216*49ab747fSPaolo Bonzini if ((bd.buffer1_size & 0xfff) > 2048) { 217*49ab747fSPaolo Bonzini DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- " 218*49ab747fSPaolo Bonzini "xgmac buffer 1 len on send > 2048 (0x%x)\n", 219*49ab747fSPaolo Bonzini __func__, bd.buffer1_size & 0xfff); 220*49ab747fSPaolo Bonzini } 221*49ab747fSPaolo Bonzini if ((bd.buffer2_size & 0xfff) != 0) { 222*49ab747fSPaolo Bonzini DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- " 223*49ab747fSPaolo Bonzini "xgmac buffer 2 len on send != 0 (0x%x)\n", 224*49ab747fSPaolo Bonzini __func__, bd.buffer2_size & 0xfff); 225*49ab747fSPaolo Bonzini } 226*49ab747fSPaolo Bonzini if (len >= sizeof(frame)) { 227*49ab747fSPaolo Bonzini DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu " 228*49ab747fSPaolo Bonzini "buffer\n" , __func__, len, sizeof(frame)); 229*49ab747fSPaolo Bonzini DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n", 230*49ab747fSPaolo Bonzini __func__, bd.buffer1_size, bd.buffer2_size); 231*49ab747fSPaolo Bonzini } 232*49ab747fSPaolo Bonzini 233*49ab747fSPaolo Bonzini cpu_physical_memory_read(bd.buffer1_addr, ptr, len); 234*49ab747fSPaolo Bonzini ptr += len; 235*49ab747fSPaolo Bonzini frame_size += len; 236*49ab747fSPaolo Bonzini if (bd.ctl_stat & 0x20000000) { 237*49ab747fSPaolo Bonzini /* Last buffer in frame. */ 238*49ab747fSPaolo Bonzini qemu_send_packet(qemu_get_queue(s->nic), frame, len); 239*49ab747fSPaolo Bonzini ptr = frame; 240*49ab747fSPaolo Bonzini frame_size = 0; 241*49ab747fSPaolo Bonzini s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS; 242*49ab747fSPaolo Bonzini } 243*49ab747fSPaolo Bonzini bd.ctl_stat &= ~0x80000000; 244*49ab747fSPaolo Bonzini /* Write back the modified descriptor. */ 245*49ab747fSPaolo Bonzini xgmac_write_desc(s, &bd, 0); 246*49ab747fSPaolo Bonzini } 247*49ab747fSPaolo Bonzini } 248*49ab747fSPaolo Bonzini 249*49ab747fSPaolo Bonzini static void enet_update_irq(struct XgmacState *s) 250*49ab747fSPaolo Bonzini { 251*49ab747fSPaolo Bonzini int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA]; 252*49ab747fSPaolo Bonzini qemu_set_irq(s->sbd_irq, !!stat); 253*49ab747fSPaolo Bonzini } 254*49ab747fSPaolo Bonzini 255*49ab747fSPaolo Bonzini static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 256*49ab747fSPaolo Bonzini { 257*49ab747fSPaolo Bonzini struct XgmacState *s = opaque; 258*49ab747fSPaolo Bonzini uint64_t r = 0; 259*49ab747fSPaolo Bonzini addr >>= 2; 260*49ab747fSPaolo Bonzini 261*49ab747fSPaolo Bonzini switch (addr) { 262*49ab747fSPaolo Bonzini case XGMAC_VERSION: 263*49ab747fSPaolo Bonzini r = 0x1012; 264*49ab747fSPaolo Bonzini break; 265*49ab747fSPaolo Bonzini default: 266*49ab747fSPaolo Bonzini if (addr < ARRAY_SIZE(s->regs)) { 267*49ab747fSPaolo Bonzini r = s->regs[addr]; 268*49ab747fSPaolo Bonzini } 269*49ab747fSPaolo Bonzini break; 270*49ab747fSPaolo Bonzini } 271*49ab747fSPaolo Bonzini return r; 272*49ab747fSPaolo Bonzini } 273*49ab747fSPaolo Bonzini 274*49ab747fSPaolo Bonzini static void enet_write(void *opaque, hwaddr addr, 275*49ab747fSPaolo Bonzini uint64_t value, unsigned size) 276*49ab747fSPaolo Bonzini { 277*49ab747fSPaolo Bonzini struct XgmacState *s = opaque; 278*49ab747fSPaolo Bonzini 279*49ab747fSPaolo Bonzini addr >>= 2; 280*49ab747fSPaolo Bonzini switch (addr) { 281*49ab747fSPaolo Bonzini case DMA_BUS_MODE: 282*49ab747fSPaolo Bonzini s->regs[DMA_BUS_MODE] = value & ~0x1; 283*49ab747fSPaolo Bonzini break; 284*49ab747fSPaolo Bonzini case DMA_XMT_POLL_DEMAND: 285*49ab747fSPaolo Bonzini xgmac_enet_send(s); 286*49ab747fSPaolo Bonzini break; 287*49ab747fSPaolo Bonzini case DMA_STATUS: 288*49ab747fSPaolo Bonzini s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value; 289*49ab747fSPaolo Bonzini break; 290*49ab747fSPaolo Bonzini case DMA_RCV_BASE_ADDR: 291*49ab747fSPaolo Bonzini s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value; 292*49ab747fSPaolo Bonzini break; 293*49ab747fSPaolo Bonzini case DMA_TX_BASE_ADDR: 294*49ab747fSPaolo Bonzini s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value; 295*49ab747fSPaolo Bonzini break; 296*49ab747fSPaolo Bonzini default: 297*49ab747fSPaolo Bonzini if (addr < ARRAY_SIZE(s->regs)) { 298*49ab747fSPaolo Bonzini s->regs[addr] = value; 299*49ab747fSPaolo Bonzini } 300*49ab747fSPaolo Bonzini break; 301*49ab747fSPaolo Bonzini } 302*49ab747fSPaolo Bonzini enet_update_irq(s); 303*49ab747fSPaolo Bonzini } 304*49ab747fSPaolo Bonzini 305*49ab747fSPaolo Bonzini static const MemoryRegionOps enet_mem_ops = { 306*49ab747fSPaolo Bonzini .read = enet_read, 307*49ab747fSPaolo Bonzini .write = enet_write, 308*49ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 309*49ab747fSPaolo Bonzini }; 310*49ab747fSPaolo Bonzini 311*49ab747fSPaolo Bonzini static int eth_can_rx(NetClientState *nc) 312*49ab747fSPaolo Bonzini { 313*49ab747fSPaolo Bonzini struct XgmacState *s = qemu_get_nic_opaque(nc); 314*49ab747fSPaolo Bonzini 315*49ab747fSPaolo Bonzini /* RX enabled? */ 316*49ab747fSPaolo Bonzini return s->regs[DMA_CONTROL] & DMA_CONTROL_SR; 317*49ab747fSPaolo Bonzini } 318*49ab747fSPaolo Bonzini 319*49ab747fSPaolo Bonzini static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 320*49ab747fSPaolo Bonzini { 321*49ab747fSPaolo Bonzini struct XgmacState *s = qemu_get_nic_opaque(nc); 322*49ab747fSPaolo Bonzini static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 323*49ab747fSPaolo Bonzini 0xff, 0xff, 0xff}; 324*49ab747fSPaolo Bonzini int unicast, broadcast, multicast; 325*49ab747fSPaolo Bonzini struct desc bd; 326*49ab747fSPaolo Bonzini ssize_t ret; 327*49ab747fSPaolo Bonzini 328*49ab747fSPaolo Bonzini unicast = ~buf[0] & 0x1; 329*49ab747fSPaolo Bonzini broadcast = memcmp(buf, sa_bcast, 6) == 0; 330*49ab747fSPaolo Bonzini multicast = !unicast && !broadcast; 331*49ab747fSPaolo Bonzini if (size < 12) { 332*49ab747fSPaolo Bonzini s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS; 333*49ab747fSPaolo Bonzini ret = -1; 334*49ab747fSPaolo Bonzini goto out; 335*49ab747fSPaolo Bonzini } 336*49ab747fSPaolo Bonzini 337*49ab747fSPaolo Bonzini xgmac_read_desc(s, &bd, 1); 338*49ab747fSPaolo Bonzini if ((bd.ctl_stat & 0x80000000) == 0) { 339*49ab747fSPaolo Bonzini s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS; 340*49ab747fSPaolo Bonzini ret = size; 341*49ab747fSPaolo Bonzini goto out; 342*49ab747fSPaolo Bonzini } 343*49ab747fSPaolo Bonzini 344*49ab747fSPaolo Bonzini cpu_physical_memory_write(bd.buffer1_addr, buf, size); 345*49ab747fSPaolo Bonzini 346*49ab747fSPaolo Bonzini /* Add in the 4 bytes for crc (the real hw returns length incl crc) */ 347*49ab747fSPaolo Bonzini size += 4; 348*49ab747fSPaolo Bonzini bd.ctl_stat = (size << 16) | 0x300; 349*49ab747fSPaolo Bonzini xgmac_write_desc(s, &bd, 1); 350*49ab747fSPaolo Bonzini 351*49ab747fSPaolo Bonzini s->stats.rx_bytes += size; 352*49ab747fSPaolo Bonzini s->stats.rx++; 353*49ab747fSPaolo Bonzini if (multicast) { 354*49ab747fSPaolo Bonzini s->stats.rx_mcast++; 355*49ab747fSPaolo Bonzini } else if (broadcast) { 356*49ab747fSPaolo Bonzini s->stats.rx_bcast++; 357*49ab747fSPaolo Bonzini } 358*49ab747fSPaolo Bonzini 359*49ab747fSPaolo Bonzini s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS; 360*49ab747fSPaolo Bonzini ret = size; 361*49ab747fSPaolo Bonzini 362*49ab747fSPaolo Bonzini out: 363*49ab747fSPaolo Bonzini enet_update_irq(s); 364*49ab747fSPaolo Bonzini return ret; 365*49ab747fSPaolo Bonzini } 366*49ab747fSPaolo Bonzini 367*49ab747fSPaolo Bonzini static void eth_cleanup(NetClientState *nc) 368*49ab747fSPaolo Bonzini { 369*49ab747fSPaolo Bonzini struct XgmacState *s = qemu_get_nic_opaque(nc); 370*49ab747fSPaolo Bonzini s->nic = NULL; 371*49ab747fSPaolo Bonzini } 372*49ab747fSPaolo Bonzini 373*49ab747fSPaolo Bonzini static NetClientInfo net_xgmac_enet_info = { 374*49ab747fSPaolo Bonzini .type = NET_CLIENT_OPTIONS_KIND_NIC, 375*49ab747fSPaolo Bonzini .size = sizeof(NICState), 376*49ab747fSPaolo Bonzini .can_receive = eth_can_rx, 377*49ab747fSPaolo Bonzini .receive = eth_rx, 378*49ab747fSPaolo Bonzini .cleanup = eth_cleanup, 379*49ab747fSPaolo Bonzini }; 380*49ab747fSPaolo Bonzini 381*49ab747fSPaolo Bonzini static int xgmac_enet_init(SysBusDevice *dev) 382*49ab747fSPaolo Bonzini { 383*49ab747fSPaolo Bonzini struct XgmacState *s = FROM_SYSBUS(typeof(*s), dev); 384*49ab747fSPaolo Bonzini 385*49ab747fSPaolo Bonzini memory_region_init_io(&s->iomem, &enet_mem_ops, s, "xgmac", 0x1000); 386*49ab747fSPaolo Bonzini sysbus_init_mmio(dev, &s->iomem); 387*49ab747fSPaolo Bonzini sysbus_init_irq(dev, &s->sbd_irq); 388*49ab747fSPaolo Bonzini sysbus_init_irq(dev, &s->pmt_irq); 389*49ab747fSPaolo Bonzini sysbus_init_irq(dev, &s->mci_irq); 390*49ab747fSPaolo Bonzini 391*49ab747fSPaolo Bonzini qemu_macaddr_default_if_unset(&s->conf.macaddr); 392*49ab747fSPaolo Bonzini s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf, 393*49ab747fSPaolo Bonzini object_get_typename(OBJECT(dev)), dev->qdev.id, s); 394*49ab747fSPaolo Bonzini qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 395*49ab747fSPaolo Bonzini 396*49ab747fSPaolo Bonzini s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) | 397*49ab747fSPaolo Bonzini s->conf.macaddr.a[4]; 398*49ab747fSPaolo Bonzini s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) | 399*49ab747fSPaolo Bonzini (s->conf.macaddr.a[2] << 16) | 400*49ab747fSPaolo Bonzini (s->conf.macaddr.a[1] << 8) | 401*49ab747fSPaolo Bonzini s->conf.macaddr.a[0]; 402*49ab747fSPaolo Bonzini 403*49ab747fSPaolo Bonzini return 0; 404*49ab747fSPaolo Bonzini } 405*49ab747fSPaolo Bonzini 406*49ab747fSPaolo Bonzini static Property xgmac_properties[] = { 407*49ab747fSPaolo Bonzini DEFINE_NIC_PROPERTIES(struct XgmacState, conf), 408*49ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 409*49ab747fSPaolo Bonzini }; 410*49ab747fSPaolo Bonzini 411*49ab747fSPaolo Bonzini static void xgmac_enet_class_init(ObjectClass *klass, void *data) 412*49ab747fSPaolo Bonzini { 413*49ab747fSPaolo Bonzini SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 414*49ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 415*49ab747fSPaolo Bonzini 416*49ab747fSPaolo Bonzini sbc->init = xgmac_enet_init; 417*49ab747fSPaolo Bonzini dc->vmsd = &vmstate_xgmac; 418*49ab747fSPaolo Bonzini dc->props = xgmac_properties; 419*49ab747fSPaolo Bonzini } 420*49ab747fSPaolo Bonzini 421*49ab747fSPaolo Bonzini static const TypeInfo xgmac_enet_info = { 422*49ab747fSPaolo Bonzini .name = "xgmac", 423*49ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 424*49ab747fSPaolo Bonzini .instance_size = sizeof(struct XgmacState), 425*49ab747fSPaolo Bonzini .class_init = xgmac_enet_class_init, 426*49ab747fSPaolo Bonzini }; 427*49ab747fSPaolo Bonzini 428*49ab747fSPaolo Bonzini static void xgmac_enet_register_types(void) 429*49ab747fSPaolo Bonzini { 430*49ab747fSPaolo Bonzini type_register_static(&xgmac_enet_info); 431*49ab747fSPaolo Bonzini } 432*49ab747fSPaolo Bonzini 433*49ab747fSPaolo Bonzini type_init(xgmac_enet_register_types) 434