xref: /qemu/hw/net/xgmac.c (revision d6454270)
149ab747fSPaolo Bonzini /*
249ab747fSPaolo Bonzini  * QEMU model of XGMAC Ethernet.
349ab747fSPaolo Bonzini  *
449ab747fSPaolo Bonzini  * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
549ab747fSPaolo Bonzini  *
649ab747fSPaolo Bonzini  * Copyright (c) 2011 Calxeda, Inc.
749ab747fSPaolo Bonzini  *
849ab747fSPaolo Bonzini  * Permission is hereby granted, free of charge, to any person obtaining a copy
949ab747fSPaolo Bonzini  * of this software and associated documentation files (the "Software"), to deal
1049ab747fSPaolo Bonzini  * in the Software without restriction, including without limitation the rights
1149ab747fSPaolo Bonzini  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
1249ab747fSPaolo Bonzini  * copies of the Software, and to permit persons to whom the Software is
1349ab747fSPaolo Bonzini  * furnished to do so, subject to the following conditions:
1449ab747fSPaolo Bonzini  *
1549ab747fSPaolo Bonzini  * The above copyright notice and this permission notice shall be included in
1649ab747fSPaolo Bonzini  * all copies or substantial portions of the Software.
1749ab747fSPaolo Bonzini  *
1849ab747fSPaolo Bonzini  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1949ab747fSPaolo Bonzini  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2049ab747fSPaolo Bonzini  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
2149ab747fSPaolo Bonzini  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2249ab747fSPaolo Bonzini  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2349ab747fSPaolo Bonzini  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
2449ab747fSPaolo Bonzini  * THE SOFTWARE.
2549ab747fSPaolo Bonzini  */
2649ab747fSPaolo Bonzini 
278ef94f0bSPeter Maydell #include "qemu/osdep.h"
2864552b6bSMarkus Armbruster #include "hw/irq.h"
2949ab747fSPaolo Bonzini #include "hw/sysbus.h"
30*d6454270SMarkus Armbruster #include "migration/vmstate.h"
3149ab747fSPaolo Bonzini #include "qemu/log.h"
320b8fa32fSMarkus Armbruster #include "qemu/module.h"
3349ab747fSPaolo Bonzini #include "net/net.h"
3449ab747fSPaolo Bonzini 
3549ab747fSPaolo Bonzini #ifdef DEBUG_XGMAC
3649ab747fSPaolo Bonzini #define DEBUGF_BRK(message, args...) do { \
3749ab747fSPaolo Bonzini                                          fprintf(stderr, (message), ## args); \
3849ab747fSPaolo Bonzini                                      } while (0)
3949ab747fSPaolo Bonzini #else
4049ab747fSPaolo Bonzini #define DEBUGF_BRK(message, args...) do { } while (0)
4149ab747fSPaolo Bonzini #endif
4249ab747fSPaolo Bonzini 
4349ab747fSPaolo Bonzini #define XGMAC_CONTROL           0x00000000   /* MAC Configuration */
4449ab747fSPaolo Bonzini #define XGMAC_FRAME_FILTER      0x00000001   /* MAC Frame Filter */
4549ab747fSPaolo Bonzini #define XGMAC_FLOW_CTRL         0x00000006   /* MAC Flow Control */
4649ab747fSPaolo Bonzini #define XGMAC_VLAN_TAG          0x00000007   /* VLAN Tags */
4749ab747fSPaolo Bonzini #define XGMAC_VERSION           0x00000008   /* Version */
4849ab747fSPaolo Bonzini /* VLAN tag for insertion or replacement into tx frames */
4949ab747fSPaolo Bonzini #define XGMAC_VLAN_INCL         0x00000009
5049ab747fSPaolo Bonzini #define XGMAC_LPI_CTRL          0x0000000a   /* LPI Control and Status */
5149ab747fSPaolo Bonzini #define XGMAC_LPI_TIMER         0x0000000b   /* LPI Timers Control */
5249ab747fSPaolo Bonzini #define XGMAC_TX_PACE           0x0000000c   /* Transmit Pace and Stretch */
5349ab747fSPaolo Bonzini #define XGMAC_VLAN_HASH         0x0000000d   /* VLAN Hash Table */
5449ab747fSPaolo Bonzini #define XGMAC_DEBUG             0x0000000e   /* Debug */
5549ab747fSPaolo Bonzini #define XGMAC_INT_STATUS        0x0000000f   /* Interrupt and Control */
5649ab747fSPaolo Bonzini /* HASH table registers */
5749ab747fSPaolo Bonzini #define XGMAC_HASH(n)           ((0x00000300/4) + (n))
5849ab747fSPaolo Bonzini #define XGMAC_NUM_HASH          16
5949ab747fSPaolo Bonzini /* Operation Mode */
6049ab747fSPaolo Bonzini #define XGMAC_OPMODE            (0x00000400/4)
6149ab747fSPaolo Bonzini /* Remote Wake-Up Frame Filter */
6249ab747fSPaolo Bonzini #define XGMAC_REMOTE_WAKE       (0x00000700/4)
6349ab747fSPaolo Bonzini /* PMT Control and Status */
6449ab747fSPaolo Bonzini #define XGMAC_PMT               (0x00000704/4)
6549ab747fSPaolo Bonzini 
6649ab747fSPaolo Bonzini #define XGMAC_ADDR_HIGH(reg)    (0x00000010+((reg) * 2))
6749ab747fSPaolo Bonzini #define XGMAC_ADDR_LOW(reg)     (0x00000011+((reg) * 2))
6849ab747fSPaolo Bonzini 
6949ab747fSPaolo Bonzini #define DMA_BUS_MODE            0x000003c0   /* Bus Mode */
7049ab747fSPaolo Bonzini #define DMA_XMT_POLL_DEMAND     0x000003c1   /* Transmit Poll Demand */
7149ab747fSPaolo Bonzini #define DMA_RCV_POLL_DEMAND     0x000003c2   /* Received Poll Demand */
7249ab747fSPaolo Bonzini #define DMA_RCV_BASE_ADDR       0x000003c3   /* Receive List Base */
7349ab747fSPaolo Bonzini #define DMA_TX_BASE_ADDR        0x000003c4   /* Transmit List Base */
7449ab747fSPaolo Bonzini #define DMA_STATUS              0x000003c5   /* Status Register */
7549ab747fSPaolo Bonzini #define DMA_CONTROL             0x000003c6   /* Ctrl (Operational Mode) */
7649ab747fSPaolo Bonzini #define DMA_INTR_ENA            0x000003c7   /* Interrupt Enable */
7749ab747fSPaolo Bonzini #define DMA_MISSED_FRAME_CTR    0x000003c8   /* Missed Frame Counter */
7849ab747fSPaolo Bonzini /* Receive Interrupt Watchdog Timer */
7949ab747fSPaolo Bonzini #define DMA_RI_WATCHDOG_TIMER   0x000003c9
8049ab747fSPaolo Bonzini #define DMA_AXI_BUS             0x000003ca   /* AXI Bus Mode */
8149ab747fSPaolo Bonzini #define DMA_AXI_STATUS          0x000003cb   /* AXI Status */
8249ab747fSPaolo Bonzini #define DMA_CUR_TX_DESC_ADDR    0x000003d2   /* Current Host Tx Descriptor */
8349ab747fSPaolo Bonzini #define DMA_CUR_RX_DESC_ADDR    0x000003d3   /* Current Host Rx Descriptor */
8449ab747fSPaolo Bonzini #define DMA_CUR_TX_BUF_ADDR     0x000003d4   /* Current Host Tx Buffer */
8549ab747fSPaolo Bonzini #define DMA_CUR_RX_BUF_ADDR     0x000003d5   /* Current Host Rx Buffer */
8649ab747fSPaolo Bonzini #define DMA_HW_FEATURE          0x000003d6   /* Enabled Hardware Features */
8749ab747fSPaolo Bonzini 
8849ab747fSPaolo Bonzini /* DMA Status register defines */
8949ab747fSPaolo Bonzini #define DMA_STATUS_GMI          0x08000000   /* MMC interrupt */
9049ab747fSPaolo Bonzini #define DMA_STATUS_GLI          0x04000000   /* GMAC Line interface int */
9149ab747fSPaolo Bonzini #define DMA_STATUS_EB_MASK      0x00380000   /* Error Bits Mask */
9249ab747fSPaolo Bonzini #define DMA_STATUS_EB_TX_ABORT  0x00080000   /* Error Bits - TX Abort */
9349ab747fSPaolo Bonzini #define DMA_STATUS_EB_RX_ABORT  0x00100000   /* Error Bits - RX Abort */
9449ab747fSPaolo Bonzini #define DMA_STATUS_TS_MASK      0x00700000   /* Transmit Process State */
9549ab747fSPaolo Bonzini #define DMA_STATUS_TS_SHIFT     20
9649ab747fSPaolo Bonzini #define DMA_STATUS_RS_MASK      0x000e0000   /* Receive Process State */
9749ab747fSPaolo Bonzini #define DMA_STATUS_RS_SHIFT     17
9849ab747fSPaolo Bonzini #define DMA_STATUS_NIS          0x00010000   /* Normal Interrupt Summary */
9949ab747fSPaolo Bonzini #define DMA_STATUS_AIS          0x00008000   /* Abnormal Interrupt Summary */
10049ab747fSPaolo Bonzini #define DMA_STATUS_ERI          0x00004000   /* Early Receive Interrupt */
10149ab747fSPaolo Bonzini #define DMA_STATUS_FBI          0x00002000   /* Fatal Bus Error Interrupt */
10249ab747fSPaolo Bonzini #define DMA_STATUS_ETI          0x00000400   /* Early Transmit Interrupt */
10349ab747fSPaolo Bonzini #define DMA_STATUS_RWT          0x00000200   /* Receive Watchdog Timeout */
10449ab747fSPaolo Bonzini #define DMA_STATUS_RPS          0x00000100   /* Receive Process Stopped */
10549ab747fSPaolo Bonzini #define DMA_STATUS_RU           0x00000080   /* Receive Buffer Unavailable */
10649ab747fSPaolo Bonzini #define DMA_STATUS_RI           0x00000040   /* Receive Interrupt */
10749ab747fSPaolo Bonzini #define DMA_STATUS_UNF          0x00000020   /* Transmit Underflow */
10849ab747fSPaolo Bonzini #define DMA_STATUS_OVF          0x00000010   /* Receive Overflow */
10949ab747fSPaolo Bonzini #define DMA_STATUS_TJT          0x00000008   /* Transmit Jabber Timeout */
11049ab747fSPaolo Bonzini #define DMA_STATUS_TU           0x00000004   /* Transmit Buffer Unavailable */
11149ab747fSPaolo Bonzini #define DMA_STATUS_TPS          0x00000002   /* Transmit Process Stopped */
11249ab747fSPaolo Bonzini #define DMA_STATUS_TI           0x00000001   /* Transmit Interrupt */
11349ab747fSPaolo Bonzini 
11449ab747fSPaolo Bonzini /* DMA Control register defines */
11549ab747fSPaolo Bonzini #define DMA_CONTROL_ST          0x00002000   /* Start/Stop Transmission */
11649ab747fSPaolo Bonzini #define DMA_CONTROL_SR          0x00000002   /* Start/Stop Receive */
11749ab747fSPaolo Bonzini #define DMA_CONTROL_DFF         0x01000000   /* Disable flush of rx frames */
11849ab747fSPaolo Bonzini 
11949ab747fSPaolo Bonzini struct desc {
12049ab747fSPaolo Bonzini     uint32_t ctl_stat;
12149ab747fSPaolo Bonzini     uint16_t buffer1_size;
12249ab747fSPaolo Bonzini     uint16_t buffer2_size;
12349ab747fSPaolo Bonzini     uint32_t buffer1_addr;
12449ab747fSPaolo Bonzini     uint32_t buffer2_addr;
12549ab747fSPaolo Bonzini     uint32_t ext_stat;
12649ab747fSPaolo Bonzini     uint32_t res[3];
12749ab747fSPaolo Bonzini };
12849ab747fSPaolo Bonzini 
12949ab747fSPaolo Bonzini #define R_MAX 0x400
13049ab747fSPaolo Bonzini 
13149ab747fSPaolo Bonzini typedef struct RxTxStats {
13249ab747fSPaolo Bonzini     uint64_t rx_bytes;
13349ab747fSPaolo Bonzini     uint64_t tx_bytes;
13449ab747fSPaolo Bonzini 
13549ab747fSPaolo Bonzini     uint64_t rx;
13649ab747fSPaolo Bonzini     uint64_t rx_bcast;
13749ab747fSPaolo Bonzini     uint64_t rx_mcast;
13849ab747fSPaolo Bonzini } RxTxStats;
13949ab747fSPaolo Bonzini 
140546921eaSAndreas Färber #define TYPE_XGMAC "xgmac"
141546921eaSAndreas Färber #define XGMAC(obj) OBJECT_CHECK(XgmacState, (obj), TYPE_XGMAC)
142546921eaSAndreas Färber 
14349ab747fSPaolo Bonzini typedef struct XgmacState {
144546921eaSAndreas Färber     SysBusDevice parent_obj;
145546921eaSAndreas Färber 
14649ab747fSPaolo Bonzini     MemoryRegion iomem;
14749ab747fSPaolo Bonzini     qemu_irq sbd_irq;
14849ab747fSPaolo Bonzini     qemu_irq pmt_irq;
14949ab747fSPaolo Bonzini     qemu_irq mci_irq;
15049ab747fSPaolo Bonzini     NICState *nic;
15149ab747fSPaolo Bonzini     NICConf conf;
15249ab747fSPaolo Bonzini 
15349ab747fSPaolo Bonzini     struct RxTxStats stats;
15449ab747fSPaolo Bonzini     uint32_t regs[R_MAX];
15549ab747fSPaolo Bonzini } XgmacState;
15649ab747fSPaolo Bonzini 
1576a0a70b0SStefan Weil static const VMStateDescription vmstate_rxtx_stats = {
15849ab747fSPaolo Bonzini     .name = "xgmac_stats",
15949ab747fSPaolo Bonzini     .version_id = 1,
16049ab747fSPaolo Bonzini     .minimum_version_id = 1,
16149ab747fSPaolo Bonzini     .fields = (VMStateField[]) {
16249ab747fSPaolo Bonzini         VMSTATE_UINT64(rx_bytes, RxTxStats),
16349ab747fSPaolo Bonzini         VMSTATE_UINT64(tx_bytes, RxTxStats),
16449ab747fSPaolo Bonzini         VMSTATE_UINT64(rx, RxTxStats),
16549ab747fSPaolo Bonzini         VMSTATE_UINT64(rx_bcast, RxTxStats),
16649ab747fSPaolo Bonzini         VMSTATE_UINT64(rx_mcast, RxTxStats),
16749ab747fSPaolo Bonzini         VMSTATE_END_OF_LIST()
16849ab747fSPaolo Bonzini     }
16949ab747fSPaolo Bonzini };
17049ab747fSPaolo Bonzini 
17149ab747fSPaolo Bonzini static const VMStateDescription vmstate_xgmac = {
17249ab747fSPaolo Bonzini     .name = "xgmac",
17349ab747fSPaolo Bonzini     .version_id = 1,
17449ab747fSPaolo Bonzini     .minimum_version_id = 1,
17549ab747fSPaolo Bonzini     .fields = (VMStateField[]) {
17649ab747fSPaolo Bonzini         VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats),
17749ab747fSPaolo Bonzini         VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX),
17849ab747fSPaolo Bonzini         VMSTATE_END_OF_LIST()
17949ab747fSPaolo Bonzini     }
18049ab747fSPaolo Bonzini };
18149ab747fSPaolo Bonzini 
182546921eaSAndreas Färber static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx)
18349ab747fSPaolo Bonzini {
18449ab747fSPaolo Bonzini     uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] :
18549ab747fSPaolo Bonzini         s->regs[DMA_CUR_TX_DESC_ADDR];
18649ab747fSPaolo Bonzini     cpu_physical_memory_read(addr, d, sizeof(*d));
18749ab747fSPaolo Bonzini }
18849ab747fSPaolo Bonzini 
189546921eaSAndreas Färber static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx)
19049ab747fSPaolo Bonzini {
19149ab747fSPaolo Bonzini     int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR;
19249ab747fSPaolo Bonzini     uint32_t addr = s->regs[reg];
19349ab747fSPaolo Bonzini 
19449ab747fSPaolo Bonzini     if (!rx && (d->ctl_stat & 0x00200000)) {
19549ab747fSPaolo Bonzini         s->regs[reg] = s->regs[DMA_TX_BASE_ADDR];
19649ab747fSPaolo Bonzini     } else if (rx && (d->buffer1_size & 0x8000)) {
19749ab747fSPaolo Bonzini         s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR];
19849ab747fSPaolo Bonzini     } else {
19949ab747fSPaolo Bonzini         s->regs[reg] += sizeof(*d);
20049ab747fSPaolo Bonzini     }
20149ab747fSPaolo Bonzini     cpu_physical_memory_write(addr, d, sizeof(*d));
20249ab747fSPaolo Bonzini }
20349ab747fSPaolo Bonzini 
204546921eaSAndreas Färber static void xgmac_enet_send(XgmacState *s)
20549ab747fSPaolo Bonzini {
20649ab747fSPaolo Bonzini     struct desc bd;
20749ab747fSPaolo Bonzini     int frame_size;
20849ab747fSPaolo Bonzini     int len;
20949ab747fSPaolo Bonzini     uint8_t frame[8192];
21049ab747fSPaolo Bonzini     uint8_t *ptr;
21149ab747fSPaolo Bonzini 
21249ab747fSPaolo Bonzini     ptr = frame;
21349ab747fSPaolo Bonzini     frame_size = 0;
21449ab747fSPaolo Bonzini     while (1) {
21549ab747fSPaolo Bonzini         xgmac_read_desc(s, &bd, 0);
21649ab747fSPaolo Bonzini         if ((bd.ctl_stat & 0x80000000) == 0) {
21749ab747fSPaolo Bonzini             /* Run out of descriptors to transmit.  */
21849ab747fSPaolo Bonzini             break;
21949ab747fSPaolo Bonzini         }
22049ab747fSPaolo Bonzini         len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff);
22149ab747fSPaolo Bonzini 
22249ab747fSPaolo Bonzini         if ((bd.buffer1_size & 0xfff) > 2048) {
22349ab747fSPaolo Bonzini             DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
22449ab747fSPaolo Bonzini                         "xgmac buffer 1 len on send > 2048 (0x%x)\n",
22549ab747fSPaolo Bonzini                          __func__, bd.buffer1_size & 0xfff);
22649ab747fSPaolo Bonzini         }
22749ab747fSPaolo Bonzini         if ((bd.buffer2_size & 0xfff) != 0) {
22849ab747fSPaolo Bonzini             DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
22949ab747fSPaolo Bonzini                         "xgmac buffer 2 len on send != 0 (0x%x)\n",
23049ab747fSPaolo Bonzini                         __func__, bd.buffer2_size & 0xfff);
23149ab747fSPaolo Bonzini         }
23249ab747fSPaolo Bonzini         if (len >= sizeof(frame)) {
23349ab747fSPaolo Bonzini             DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu "
23449ab747fSPaolo Bonzini                         "buffer\n" , __func__, len, sizeof(frame));
23549ab747fSPaolo Bonzini             DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n",
23649ab747fSPaolo Bonzini                         __func__, bd.buffer1_size, bd.buffer2_size);
23749ab747fSPaolo Bonzini         }
23849ab747fSPaolo Bonzini 
23949ab747fSPaolo Bonzini         cpu_physical_memory_read(bd.buffer1_addr, ptr, len);
24049ab747fSPaolo Bonzini         ptr += len;
24149ab747fSPaolo Bonzini         frame_size += len;
24249ab747fSPaolo Bonzini         if (bd.ctl_stat & 0x20000000) {
24349ab747fSPaolo Bonzini             /* Last buffer in frame.  */
24449ab747fSPaolo Bonzini             qemu_send_packet(qemu_get_queue(s->nic), frame, len);
24549ab747fSPaolo Bonzini             ptr = frame;
24649ab747fSPaolo Bonzini             frame_size = 0;
24749ab747fSPaolo Bonzini             s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;
24849ab747fSPaolo Bonzini         }
24949ab747fSPaolo Bonzini         bd.ctl_stat &= ~0x80000000;
25049ab747fSPaolo Bonzini         /* Write back the modified descriptor.  */
25149ab747fSPaolo Bonzini         xgmac_write_desc(s, &bd, 0);
25249ab747fSPaolo Bonzini     }
25349ab747fSPaolo Bonzini }
25449ab747fSPaolo Bonzini 
255546921eaSAndreas Färber static void enet_update_irq(XgmacState *s)
25649ab747fSPaolo Bonzini {
25749ab747fSPaolo Bonzini     int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA];
25849ab747fSPaolo Bonzini     qemu_set_irq(s->sbd_irq, !!stat);
25949ab747fSPaolo Bonzini }
26049ab747fSPaolo Bonzini 
26149ab747fSPaolo Bonzini static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
26249ab747fSPaolo Bonzini {
263546921eaSAndreas Färber     XgmacState *s = opaque;
26449ab747fSPaolo Bonzini     uint64_t r = 0;
26549ab747fSPaolo Bonzini     addr >>= 2;
26649ab747fSPaolo Bonzini 
26749ab747fSPaolo Bonzini     switch (addr) {
26849ab747fSPaolo Bonzini     case XGMAC_VERSION:
26949ab747fSPaolo Bonzini         r = 0x1012;
27049ab747fSPaolo Bonzini         break;
27149ab747fSPaolo Bonzini     default:
27249ab747fSPaolo Bonzini         if (addr < ARRAY_SIZE(s->regs)) {
27349ab747fSPaolo Bonzini             r = s->regs[addr];
27449ab747fSPaolo Bonzini         }
27549ab747fSPaolo Bonzini         break;
27649ab747fSPaolo Bonzini     }
27749ab747fSPaolo Bonzini     return r;
27849ab747fSPaolo Bonzini }
27949ab747fSPaolo Bonzini 
28049ab747fSPaolo Bonzini static void enet_write(void *opaque, hwaddr addr,
28149ab747fSPaolo Bonzini                        uint64_t value, unsigned size)
28249ab747fSPaolo Bonzini {
283546921eaSAndreas Färber     XgmacState *s = opaque;
28449ab747fSPaolo Bonzini 
28549ab747fSPaolo Bonzini     addr >>= 2;
28649ab747fSPaolo Bonzini     switch (addr) {
28749ab747fSPaolo Bonzini     case DMA_BUS_MODE:
28849ab747fSPaolo Bonzini         s->regs[DMA_BUS_MODE] = value & ~0x1;
28949ab747fSPaolo Bonzini         break;
29049ab747fSPaolo Bonzini     case DMA_XMT_POLL_DEMAND:
29149ab747fSPaolo Bonzini         xgmac_enet_send(s);
29249ab747fSPaolo Bonzini         break;
29349ab747fSPaolo Bonzini     case DMA_STATUS:
29449ab747fSPaolo Bonzini         s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value;
29549ab747fSPaolo Bonzini         break;
29649ab747fSPaolo Bonzini     case DMA_RCV_BASE_ADDR:
29749ab747fSPaolo Bonzini         s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value;
29849ab747fSPaolo Bonzini         break;
29949ab747fSPaolo Bonzini     case DMA_TX_BASE_ADDR:
30049ab747fSPaolo Bonzini         s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value;
30149ab747fSPaolo Bonzini         break;
30249ab747fSPaolo Bonzini     default:
30349ab747fSPaolo Bonzini         if (addr < ARRAY_SIZE(s->regs)) {
30449ab747fSPaolo Bonzini             s->regs[addr] = value;
30549ab747fSPaolo Bonzini         }
30649ab747fSPaolo Bonzini         break;
30749ab747fSPaolo Bonzini     }
30849ab747fSPaolo Bonzini     enet_update_irq(s);
30949ab747fSPaolo Bonzini }
31049ab747fSPaolo Bonzini 
31149ab747fSPaolo Bonzini static const MemoryRegionOps enet_mem_ops = {
31249ab747fSPaolo Bonzini     .read = enet_read,
31349ab747fSPaolo Bonzini     .write = enet_write,
31449ab747fSPaolo Bonzini     .endianness = DEVICE_LITTLE_ENDIAN,
31549ab747fSPaolo Bonzini };
31649ab747fSPaolo Bonzini 
3178c8c460cSFam Zheng static int eth_can_rx(XgmacState *s)
31849ab747fSPaolo Bonzini {
31949ab747fSPaolo Bonzini     /* RX enabled?  */
32049ab747fSPaolo Bonzini     return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;
32149ab747fSPaolo Bonzini }
32249ab747fSPaolo Bonzini 
32349ab747fSPaolo Bonzini static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
32449ab747fSPaolo Bonzini {
325546921eaSAndreas Färber     XgmacState *s = qemu_get_nic_opaque(nc);
32649ab747fSPaolo Bonzini     static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
32749ab747fSPaolo Bonzini                                               0xff, 0xff, 0xff};
32849ab747fSPaolo Bonzini     int unicast, broadcast, multicast;
32949ab747fSPaolo Bonzini     struct desc bd;
33049ab747fSPaolo Bonzini     ssize_t ret;
33149ab747fSPaolo Bonzini 
3328c8c460cSFam Zheng     if (!eth_can_rx(s)) {
3338c8c460cSFam Zheng         return -1;
3348c8c460cSFam Zheng     }
33549ab747fSPaolo Bonzini     unicast = ~buf[0] & 0x1;
33649ab747fSPaolo Bonzini     broadcast = memcmp(buf, sa_bcast, 6) == 0;
33749ab747fSPaolo Bonzini     multicast = !unicast && !broadcast;
33849ab747fSPaolo Bonzini     if (size < 12) {
33949ab747fSPaolo Bonzini         s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
34049ab747fSPaolo Bonzini         ret = -1;
34149ab747fSPaolo Bonzini         goto out;
34249ab747fSPaolo Bonzini     }
34349ab747fSPaolo Bonzini 
34449ab747fSPaolo Bonzini     xgmac_read_desc(s, &bd, 1);
34549ab747fSPaolo Bonzini     if ((bd.ctl_stat & 0x80000000) == 0) {
34649ab747fSPaolo Bonzini         s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS;
34749ab747fSPaolo Bonzini         ret = size;
34849ab747fSPaolo Bonzini         goto out;
34949ab747fSPaolo Bonzini     }
35049ab747fSPaolo Bonzini 
35149ab747fSPaolo Bonzini     cpu_physical_memory_write(bd.buffer1_addr, buf, size);
35249ab747fSPaolo Bonzini 
35349ab747fSPaolo Bonzini     /* Add in the 4 bytes for crc (the real hw returns length incl crc) */
35449ab747fSPaolo Bonzini     size += 4;
35549ab747fSPaolo Bonzini     bd.ctl_stat = (size << 16) | 0x300;
35649ab747fSPaolo Bonzini     xgmac_write_desc(s, &bd, 1);
35749ab747fSPaolo Bonzini 
35849ab747fSPaolo Bonzini     s->stats.rx_bytes += size;
35949ab747fSPaolo Bonzini     s->stats.rx++;
36049ab747fSPaolo Bonzini     if (multicast) {
36149ab747fSPaolo Bonzini         s->stats.rx_mcast++;
36249ab747fSPaolo Bonzini     } else if (broadcast) {
36349ab747fSPaolo Bonzini         s->stats.rx_bcast++;
36449ab747fSPaolo Bonzini     }
36549ab747fSPaolo Bonzini 
36649ab747fSPaolo Bonzini     s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
36749ab747fSPaolo Bonzini     ret = size;
36849ab747fSPaolo Bonzini 
36949ab747fSPaolo Bonzini out:
37049ab747fSPaolo Bonzini     enet_update_irq(s);
37149ab747fSPaolo Bonzini     return ret;
37249ab747fSPaolo Bonzini }
37349ab747fSPaolo Bonzini 
37449ab747fSPaolo Bonzini static NetClientInfo net_xgmac_enet_info = {
375f394b2e2SEric Blake     .type = NET_CLIENT_DRIVER_NIC,
37649ab747fSPaolo Bonzini     .size = sizeof(NICState),
37749ab747fSPaolo Bonzini     .receive = eth_rx,
37849ab747fSPaolo Bonzini };
37949ab747fSPaolo Bonzini 
3808fa922c2SCédric Le Goater static void xgmac_enet_realize(DeviceState *dev, Error **errp)
38149ab747fSPaolo Bonzini {
3828fa922c2SCédric Le Goater     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
383546921eaSAndreas Färber     XgmacState *s = XGMAC(dev);
38449ab747fSPaolo Bonzini 
385eedfac6fSPaolo Bonzini     memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s,
386eedfac6fSPaolo Bonzini                           "xgmac", 0x1000);
387546921eaSAndreas Färber     sysbus_init_mmio(sbd, &s->iomem);
388546921eaSAndreas Färber     sysbus_init_irq(sbd, &s->sbd_irq);
389546921eaSAndreas Färber     sysbus_init_irq(sbd, &s->pmt_irq);
390546921eaSAndreas Färber     sysbus_init_irq(sbd, &s->mci_irq);
39149ab747fSPaolo Bonzini 
39249ab747fSPaolo Bonzini     qemu_macaddr_default_if_unset(&s->conf.macaddr);
39349ab747fSPaolo Bonzini     s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,
394546921eaSAndreas Färber                           object_get_typename(OBJECT(dev)), dev->id, s);
39549ab747fSPaolo Bonzini     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
39649ab747fSPaolo Bonzini 
39749ab747fSPaolo Bonzini     s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |
39849ab747fSPaolo Bonzini                                    s->conf.macaddr.a[4];
39949ab747fSPaolo Bonzini     s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) |
40049ab747fSPaolo Bonzini                                  (s->conf.macaddr.a[2] << 16) |
40149ab747fSPaolo Bonzini                                  (s->conf.macaddr.a[1] << 8) |
40249ab747fSPaolo Bonzini                                   s->conf.macaddr.a[0];
40349ab747fSPaolo Bonzini }
40449ab747fSPaolo Bonzini 
40549ab747fSPaolo Bonzini static Property xgmac_properties[] = {
406546921eaSAndreas Färber     DEFINE_NIC_PROPERTIES(XgmacState, conf),
40749ab747fSPaolo Bonzini     DEFINE_PROP_END_OF_LIST(),
40849ab747fSPaolo Bonzini };
40949ab747fSPaolo Bonzini 
41049ab747fSPaolo Bonzini static void xgmac_enet_class_init(ObjectClass *klass, void *data)
41149ab747fSPaolo Bonzini {
41249ab747fSPaolo Bonzini     DeviceClass *dc = DEVICE_CLASS(klass);
41349ab747fSPaolo Bonzini 
4148fa922c2SCédric Le Goater     dc->realize = xgmac_enet_realize;
41549ab747fSPaolo Bonzini     dc->vmsd = &vmstate_xgmac;
41649ab747fSPaolo Bonzini     dc->props = xgmac_properties;
41749ab747fSPaolo Bonzini }
41849ab747fSPaolo Bonzini 
41949ab747fSPaolo Bonzini static const TypeInfo xgmac_enet_info = {
420546921eaSAndreas Färber     .name          = TYPE_XGMAC,
42149ab747fSPaolo Bonzini     .parent        = TYPE_SYS_BUS_DEVICE,
422546921eaSAndreas Färber     .instance_size = sizeof(XgmacState),
42349ab747fSPaolo Bonzini     .class_init    = xgmac_enet_class_init,
42449ab747fSPaolo Bonzini };
42549ab747fSPaolo Bonzini 
42649ab747fSPaolo Bonzini static void xgmac_enet_register_types(void)
42749ab747fSPaolo Bonzini {
42849ab747fSPaolo Bonzini     type_register_static(&xgmac_enet_info);
42949ab747fSPaolo Bonzini }
43049ab747fSPaolo Bonzini 
43149ab747fSPaolo Bonzini type_init(xgmac_enet_register_types)
432