1 /* 2 * OpenRISC simulator for use as an IIS. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Feng Gao <gf91597@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "hw/irq.h" 26 #include "hw/boards.h" 27 #include "elf.h" 28 #include "hw/char/serial.h" 29 #include "net/net.h" 30 #include "hw/loader.h" 31 #include "hw/qdev-properties.h" 32 #include "exec/address-spaces.h" 33 #include "sysemu/device_tree.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/sysbus.h" 36 #include "sysemu/qtest.h" 37 #include "sysemu/reset.h" 38 #include "hw/core/split-irq.h" 39 40 #include <libfdt.h> 41 42 #define KERNEL_LOAD_ADDR 0x100 43 44 #define OR1KSIM_CPUS_MAX 4 45 #define OR1KSIM_CLK_MHZ 20000000 46 47 #define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim") 48 #define OR1KSIM_MACHINE(obj) \ 49 OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE) 50 51 typedef struct Or1ksimState { 52 /*< private >*/ 53 MachineState parent_obj; 54 55 /*< public >*/ 56 void *fdt; 57 int fdt_size; 58 59 } Or1ksimState; 60 61 enum { 62 OR1KSIM_DRAM, 63 OR1KSIM_UART, 64 OR1KSIM_ETHOC, 65 OR1KSIM_OMPIC, 66 }; 67 68 enum { 69 OR1KSIM_OMPIC_IRQ = 1, 70 OR1KSIM_UART_IRQ = 2, 71 OR1KSIM_ETHOC_IRQ = 4, 72 }; 73 74 static const struct MemmapEntry { 75 hwaddr base; 76 hwaddr size; 77 } or1ksim_memmap[] = { 78 [OR1KSIM_DRAM] = { 0x00000000, 0 }, 79 [OR1KSIM_UART] = { 0x90000000, 0x100 }, 80 [OR1KSIM_ETHOC] = { 0x92000000, 0x800 }, 81 [OR1KSIM_OMPIC] = { 0x98000000, 16 }, 82 }; 83 84 static struct openrisc_boot_info { 85 uint32_t bootstrap_pc; 86 uint32_t fdt_addr; 87 } boot_info; 88 89 static void main_cpu_reset(void *opaque) 90 { 91 OpenRISCCPU *cpu = opaque; 92 CPUState *cs = CPU(cpu); 93 94 cpu_reset(CPU(cpu)); 95 96 cpu_set_pc(cs, boot_info.bootstrap_pc); 97 cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr); 98 } 99 100 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) 101 { 102 return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); 103 } 104 105 static void openrisc_create_fdt(Or1ksimState *state, 106 const struct MemmapEntry *memmap, 107 int num_cpus, uint64_t mem_size, 108 const char *cmdline) 109 { 110 void *fdt; 111 int cpu; 112 char *nodename; 113 int pic_ph; 114 115 fdt = state->fdt = create_device_tree(&state->fdt_size); 116 if (!fdt) { 117 error_report("create_device_tree() failed"); 118 exit(1); 119 } 120 121 qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim"); 122 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); 123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); 124 125 nodename = g_strdup_printf("/memory@%" HWADDR_PRIx, 126 memmap[OR1KSIM_DRAM].base); 127 qemu_fdt_add_subnode(fdt, nodename); 128 qemu_fdt_setprop_cells(fdt, nodename, "reg", 129 memmap[OR1KSIM_DRAM].base, mem_size); 130 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 131 g_free(nodename); 132 133 qemu_fdt_add_subnode(fdt, "/cpus"); 134 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 135 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 136 137 for (cpu = 0; cpu < num_cpus; cpu++) { 138 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 139 qemu_fdt_add_subnode(fdt, nodename); 140 qemu_fdt_setprop_string(fdt, nodename, "compatible", 141 "opencores,or1200-rtlsvn481"); 142 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 143 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 144 OR1KSIM_CLK_MHZ); 145 g_free(nodename); 146 } 147 148 nodename = (char *)"/pic"; 149 qemu_fdt_add_subnode(fdt, nodename); 150 pic_ph = qemu_fdt_alloc_phandle(fdt); 151 qemu_fdt_setprop_string(fdt, nodename, "compatible", 152 "opencores,or1k-pic-level"); 153 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 154 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 155 qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph); 156 157 qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph); 158 159 qemu_fdt_add_subnode(fdt, "/chosen"); 160 if (cmdline) { 161 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 162 } 163 164 /* Create aliases node for use by devices. */ 165 qemu_fdt_add_subnode(fdt, "/aliases"); 166 } 167 168 static void openrisc_sim_net_init(Or1ksimState *state, hwaddr base, hwaddr size, 169 int num_cpus, OpenRISCCPU *cpus[], 170 int irq_pin, NICInfo *nd) 171 { 172 void *fdt = state->fdt; 173 DeviceState *dev; 174 SysBusDevice *s; 175 char *nodename; 176 int i; 177 178 dev = qdev_new("open_eth"); 179 qdev_set_nic_properties(dev, nd); 180 181 s = SYS_BUS_DEVICE(dev); 182 sysbus_realize_and_unref(s, &error_fatal); 183 if (num_cpus > 1) { 184 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 185 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 186 qdev_realize_and_unref(splitter, NULL, &error_fatal); 187 for (i = 0; i < num_cpus; i++) { 188 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 189 } 190 sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); 191 } else { 192 sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin)); 193 } 194 sysbus_mmio_map(s, 0, base); 195 sysbus_mmio_map(s, 1, base + 0x400); 196 197 /* Init device tree node for ethoc. */ 198 nodename = g_strdup_printf("/ethoc@%" HWADDR_PRIx, base); 199 qemu_fdt_add_subnode(fdt, nodename); 200 qemu_fdt_setprop_string(fdt, nodename, "compatible", "opencores,ethoc"); 201 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 202 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 203 qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0); 204 205 qemu_fdt_setprop_string(fdt, "/aliases", "enet0", nodename); 206 g_free(nodename); 207 } 208 209 static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base, 210 hwaddr size, int num_cpus, 211 OpenRISCCPU *cpus[], int irq_pin) 212 { 213 void *fdt = state->fdt; 214 DeviceState *dev; 215 SysBusDevice *s; 216 char *nodename; 217 int i; 218 219 dev = qdev_new("or1k-ompic"); 220 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 221 222 s = SYS_BUS_DEVICE(dev); 223 sysbus_realize_and_unref(s, &error_fatal); 224 for (i = 0; i < num_cpus; i++) { 225 sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin)); 226 } 227 sysbus_mmio_map(s, 0, base); 228 229 /* Add device tree node for ompic. */ 230 nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base); 231 qemu_fdt_add_subnode(fdt, nodename); 232 qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic"); 233 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 234 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 235 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0); 236 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 237 g_free(nodename); 238 } 239 240 static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base, 241 hwaddr size, int num_cpus, 242 OpenRISCCPU *cpus[], int irq_pin) 243 { 244 void *fdt = state->fdt; 245 char *nodename; 246 qemu_irq serial_irq; 247 int i; 248 249 if (num_cpus > 1) { 250 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 251 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 252 qdev_realize_and_unref(splitter, NULL, &error_fatal); 253 for (i = 0; i < num_cpus; i++) { 254 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 255 } 256 serial_irq = qdev_get_gpio_in(splitter, 0); 257 } else { 258 serial_irq = get_cpu_irq(cpus, 0, irq_pin); 259 } 260 serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, 261 serial_hd(0), DEVICE_NATIVE_ENDIAN); 262 263 /* Add device tree node for serial. */ 264 nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base); 265 qemu_fdt_add_subnode(fdt, nodename); 266 qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); 267 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 268 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 269 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ); 270 qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0); 271 272 /* The /chosen node is created during fdt creation. */ 273 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 274 qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename); 275 g_free(nodename); 276 } 277 278 static hwaddr openrisc_load_kernel(ram_addr_t ram_size, 279 const char *kernel_filename) 280 { 281 long kernel_size; 282 uint64_t elf_entry; 283 uint64_t high_addr; 284 hwaddr entry; 285 286 if (kernel_filename && !qtest_enabled()) { 287 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 288 &elf_entry, NULL, &high_addr, NULL, 1, 289 EM_OPENRISC, 1, 0); 290 entry = elf_entry; 291 if (kernel_size < 0) { 292 kernel_size = load_uimage(kernel_filename, 293 &entry, NULL, NULL, NULL, NULL); 294 high_addr = entry + kernel_size; 295 } 296 if (kernel_size < 0) { 297 kernel_size = load_image_targphys(kernel_filename, 298 KERNEL_LOAD_ADDR, 299 ram_size - KERNEL_LOAD_ADDR); 300 high_addr = KERNEL_LOAD_ADDR + kernel_size; 301 } 302 303 if (entry <= 0) { 304 entry = KERNEL_LOAD_ADDR; 305 } 306 307 if (kernel_size < 0) { 308 error_report("couldn't load the kernel '%s'", kernel_filename); 309 exit(1); 310 } 311 boot_info.bootstrap_pc = entry; 312 313 return high_addr; 314 } 315 return 0; 316 } 317 318 static hwaddr openrisc_load_initrd(Or1ksimState *state, const char *filename, 319 hwaddr load_start, uint64_t mem_size) 320 { 321 void *fdt = state->fdt; 322 int size; 323 hwaddr start; 324 325 /* We put the initrd right after the kernel; page aligned. */ 326 start = TARGET_PAGE_ALIGN(load_start); 327 328 size = load_ramdisk(filename, start, mem_size - start); 329 if (size < 0) { 330 size = load_image_targphys(filename, start, mem_size - start); 331 if (size < 0) { 332 error_report("could not load ramdisk '%s'", filename); 333 exit(1); 334 } 335 } 336 337 qemu_fdt_setprop_cell(fdt, "/chosen", 338 "linux,initrd-start", start); 339 qemu_fdt_setprop_cell(fdt, "/chosen", 340 "linux,initrd-end", start + size); 341 342 return start + size; 343 } 344 345 static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start, 346 uint64_t mem_size) 347 { 348 void *fdt = state->fdt; 349 uint32_t fdt_addr; 350 int ret; 351 int fdtsize = fdt_totalsize(fdt); 352 353 if (fdtsize <= 0) { 354 error_report("invalid device-tree"); 355 exit(1); 356 } 357 358 /* We put fdt right after the kernel and/or initrd. */ 359 fdt_addr = ROUND_UP(load_start, 4); 360 361 ret = fdt_pack(fdt); 362 /* Should only fail if we've built a corrupted tree */ 363 g_assert(ret == 0); 364 /* copy in the device tree */ 365 qemu_fdt_dumpdtb(fdt, fdtsize); 366 367 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 368 &address_space_memory); 369 370 return fdt_addr; 371 } 372 373 static void openrisc_sim_init(MachineState *machine) 374 { 375 ram_addr_t ram_size = machine->ram_size; 376 const char *kernel_filename = machine->kernel_filename; 377 OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {}; 378 Or1ksimState *state = OR1KSIM_MACHINE(machine); 379 MemoryRegion *ram; 380 hwaddr load_addr; 381 int n; 382 unsigned int smp_cpus = machine->smp.cpus; 383 384 assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX); 385 for (n = 0; n < smp_cpus; n++) { 386 cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type)); 387 if (cpus[n] == NULL) { 388 fprintf(stderr, "Unable to find CPU definition!\n"); 389 exit(1); 390 } 391 392 cpu_openrisc_clock_init(cpus[n]); 393 394 qemu_register_reset(main_cpu_reset, cpus[n]); 395 } 396 397 ram = g_malloc(sizeof(*ram)); 398 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); 399 memory_region_add_subregion(get_system_memory(), 0, ram); 400 401 openrisc_create_fdt(state, or1ksim_memmap, smp_cpus, machine->ram_size, 402 machine->kernel_cmdline); 403 404 if (nd_table[0].used) { 405 openrisc_sim_net_init(state, or1ksim_memmap[OR1KSIM_ETHOC].base, 406 or1ksim_memmap[OR1KSIM_ETHOC].size, 407 smp_cpus, cpus, 408 OR1KSIM_ETHOC_IRQ, nd_table); 409 } 410 411 if (smp_cpus > 1) { 412 openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base, 413 or1ksim_memmap[OR1KSIM_UART].size, 414 smp_cpus, cpus, OR1KSIM_OMPIC_IRQ); 415 } 416 417 openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base, 418 or1ksim_memmap[OR1KSIM_UART].size, smp_cpus, cpus, 419 OR1KSIM_UART_IRQ); 420 421 load_addr = openrisc_load_kernel(ram_size, kernel_filename); 422 if (load_addr > 0) { 423 if (machine->initrd_filename) { 424 load_addr = openrisc_load_initrd(state, machine->initrd_filename, 425 load_addr, machine->ram_size); 426 } 427 boot_info.fdt_addr = openrisc_load_fdt(state, load_addr, 428 machine->ram_size); 429 } 430 } 431 432 static void openrisc_sim_machine_init(ObjectClass *oc, void *data) 433 { 434 MachineClass *mc = MACHINE_CLASS(oc); 435 436 mc->desc = "or1k simulation"; 437 mc->init = openrisc_sim_init; 438 mc->max_cpus = OR1KSIM_CPUS_MAX; 439 mc->is_default = true; 440 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); 441 } 442 443 static const TypeInfo or1ksim_machine_typeinfo = { 444 .name = TYPE_OR1KSIM_MACHINE, 445 .parent = TYPE_MACHINE, 446 .class_init = openrisc_sim_machine_init, 447 .instance_size = sizeof(Or1ksimState), 448 }; 449 450 static void or1ksim_machine_init_register_types(void) 451 { 452 type_register_static(&or1ksim_machine_typeinfo); 453 } 454 455 type_init(or1ksim_machine_init_register_types) 456