1 /* 2 * OpenRISC simulator for use as an IIS. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Feng Gao <gf91597@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "hw/boards.h" 24 #include "elf.h" 25 #include "hw/char/serial.h" 26 #include "net/net.h" 27 #include "hw/loader.h" 28 #include "exec/address-spaces.h" 29 #include "sysemu/sysemu.h" 30 #include "hw/sysbus.h" 31 #include "sysemu/qtest.h" 32 33 #define KERNEL_LOAD_ADDR 0x100 34 35 static void main_cpu_reset(void *opaque) 36 { 37 OpenRISCCPU *cpu = opaque; 38 39 cpu_reset(CPU(cpu)); 40 } 41 42 static void openrisc_sim_net_init(MemoryRegion *address_space, 43 hwaddr base, 44 hwaddr descriptors, 45 qemu_irq irq, NICInfo *nd) 46 { 47 DeviceState *dev; 48 SysBusDevice *s; 49 50 dev = qdev_create(NULL, "open_eth"); 51 qdev_set_nic_properties(dev, nd); 52 qdev_init_nofail(dev); 53 54 s = SYS_BUS_DEVICE(dev); 55 sysbus_connect_irq(s, 0, irq); 56 memory_region_add_subregion(address_space, base, 57 sysbus_mmio_get_region(s, 0)); 58 memory_region_add_subregion(address_space, descriptors, 59 sysbus_mmio_get_region(s, 1)); 60 } 61 62 static void cpu_openrisc_load_kernel(ram_addr_t ram_size, 63 const char *kernel_filename, 64 OpenRISCCPU *cpu) 65 { 66 long kernel_size; 67 uint64_t elf_entry; 68 hwaddr entry; 69 70 if (kernel_filename && !qtest_enabled()) { 71 kernel_size = load_elf(kernel_filename, NULL, NULL, 72 &elf_entry, NULL, NULL, 1, EM_OPENRISC, 1); 73 entry = elf_entry; 74 if (kernel_size < 0) { 75 kernel_size = load_uimage(kernel_filename, 76 &entry, NULL, NULL, NULL, NULL); 77 } 78 if (kernel_size < 0) { 79 kernel_size = load_image_targphys(kernel_filename, 80 KERNEL_LOAD_ADDR, 81 ram_size - KERNEL_LOAD_ADDR); 82 entry = KERNEL_LOAD_ADDR; 83 } 84 85 if (kernel_size < 0) { 86 fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n", 87 kernel_filename); 88 exit(1); 89 } 90 cpu->env.pc = entry; 91 } 92 } 93 94 static void openrisc_sim_init(MachineState *machine) 95 { 96 ram_addr_t ram_size = machine->ram_size; 97 const char *cpu_model = machine->cpu_model; 98 const char *kernel_filename = machine->kernel_filename; 99 OpenRISCCPU *cpu = NULL; 100 MemoryRegion *ram; 101 int n; 102 103 if (!cpu_model) { 104 cpu_model = "or1200"; 105 } 106 107 for (n = 0; n < smp_cpus; n++) { 108 cpu = cpu_openrisc_init(cpu_model); 109 if (cpu == NULL) { 110 fprintf(stderr, "Unable to find CPU definition!\n"); 111 exit(1); 112 } 113 qemu_register_reset(main_cpu_reset, cpu); 114 main_cpu_reset(cpu); 115 } 116 117 ram = g_malloc(sizeof(*ram)); 118 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); 119 vmstate_register_ram_global(ram); 120 memory_region_add_subregion(get_system_memory(), 0, ram); 121 122 cpu_openrisc_pic_init(cpu); 123 cpu_openrisc_clock_init(cpu); 124 125 serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2], 126 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); 127 128 if (nd_table[0].used) { 129 openrisc_sim_net_init(get_system_memory(), 0x92000000, 130 0x92000400, cpu->env.irq[4], nd_table); 131 } 132 133 cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu); 134 } 135 136 static void openrisc_sim_machine_init(MachineClass *mc) 137 { 138 mc->desc = "or32 simulation"; 139 mc->init = openrisc_sim_init; 140 mc->max_cpus = 1; 141 mc->is_default = 1; 142 } 143 144 DEFINE_MACHINE("or32-sim", openrisc_sim_machine_init) 145