1 /* 2 * Emulated CXL Switch Upstream Port 3 * 4 * Copyright (c) 2022 Huawei Technologies. 5 * 6 * Based on xio3130_upstream.c 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/log.h" 13 #include "hw/qdev-properties.h" 14 #include "hw/pci/msi.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pcie_port.h" 17 /* 18 * Null value of all Fs suggested by IEEE RA guidelines for use of 19 * EU, OUI and CID 20 */ 21 #define UI64_NULL (~0ULL) 22 23 #define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 2 24 25 #define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70 26 #define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90 27 #define CXL_UPSTREAM_PORT_AER_OFFSET 0x100 28 #define CXL_UPSTREAM_PORT_SN_OFFSET \ 29 (CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF) 30 #define CXL_UPSTREAM_PORT_DVSEC_OFFSET \ 31 (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF) 32 33 typedef struct CXLUpstreamPort { 34 /*< private >*/ 35 PCIEPort parent_obj; 36 37 /*< public >*/ 38 CXLComponentState cxl_cstate; 39 DOECap doe_cdat; 40 uint64_t sn; 41 } CXLUpstreamPort; 42 43 CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp) 44 { 45 return &usp->cxl_cstate; 46 } 47 48 static void cxl_usp_dvsec_write_config(PCIDevice *dev, uint32_t addr, 49 uint32_t val, int len) 50 { 51 CXLUpstreamPort *usp = CXL_USP(dev); 52 53 if (range_contains(&usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { 54 uint8_t *reg = &dev->config[addr]; 55 addr -= usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob; 56 if (addr == PORT_CONTROL_OFFSET) { 57 if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) { 58 /* unmask SBR */ 59 qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n"); 60 } 61 if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) { 62 /* Alt Memory & ID Space Enable */ 63 qemu_log_mask(LOG_UNIMP, 64 "Alt Memory & ID space is not supported\n"); 65 } 66 } 67 } 68 } 69 70 static void cxl_usp_write_config(PCIDevice *d, uint32_t address, 71 uint32_t val, int len) 72 { 73 CXLUpstreamPort *usp = CXL_USP(d); 74 75 pcie_doe_write_config(&usp->doe_cdat, address, val, len); 76 pci_bridge_write_config(d, address, val, len); 77 pcie_cap_flr_write_config(d, address, val, len); 78 pcie_aer_write_config(d, address, val, len); 79 80 cxl_usp_dvsec_write_config(d, address, val, len); 81 } 82 83 static uint32_t cxl_usp_read_config(PCIDevice *d, uint32_t address, int len) 84 { 85 CXLUpstreamPort *usp = CXL_USP(d); 86 uint32_t val; 87 88 if (pcie_doe_read_config(&usp->doe_cdat, address, len, &val)) { 89 return val; 90 } 91 92 return pci_default_read_config(d, address, len); 93 } 94 95 static void latch_registers(CXLUpstreamPort *usp) 96 { 97 uint32_t *reg_state = usp->cxl_cstate.crb.cache_mem_registers; 98 uint32_t *write_msk = usp->cxl_cstate.crb.cache_mem_regs_write_mask; 99 100 cxl_component_register_init_common(reg_state, write_msk, 101 CXL2_UPSTREAM_PORT); 102 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8); 103 } 104 105 static void cxl_usp_reset(DeviceState *qdev) 106 { 107 PCIDevice *d = PCI_DEVICE(qdev); 108 CXLUpstreamPort *usp = CXL_USP(qdev); 109 110 pci_bridge_reset(qdev); 111 pcie_cap_deverr_reset(d); 112 latch_registers(usp); 113 } 114 115 static void build_dvsecs(CXLComponentState *cxl) 116 { 117 uint8_t *dvsec; 118 119 dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 120 .status = 0x1, /* Port Power Management Init Complete */ 121 }; 122 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, 123 EXTENSIONS_PORT_DVSEC_LENGTH, 124 EXTENSIONS_PORT_DVSEC, 125 EXTENSIONS_PORT_DVSEC_REVID, dvsec); 126 dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ 127 .cap = 0x27, /* Cache, IO, Mem, non-MLD */ 128 .ctrl = 0x27, /* Cache, IO, Mem */ 129 .status = 0x26, /* same */ 130 .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */ 131 }; 132 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, 133 PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0, 134 PCIE_FLEXBUS_PORT_DVSEC, 135 PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec); 136 137 dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){ 138 .rsvd = 0, 139 .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX, 140 .reg0_base_hi = 0, 141 }; 142 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, 143 REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC, 144 REG_LOC_DVSEC_REVID, dvsec); 145 } 146 147 static bool cxl_doe_cdat_rsp(DOECap *doe_cap) 148 { 149 CDATObject *cdat = &CXL_USP(doe_cap->pdev)->cxl_cstate.cdat; 150 uint16_t ent; 151 void *base; 152 uint32_t len; 153 CDATReq *req = pcie_doe_get_write_mbox_ptr(doe_cap); 154 CDATRsp rsp; 155 156 cxl_doe_cdat_update(&CXL_USP(doe_cap->pdev)->cxl_cstate, &error_fatal); 157 assert(cdat->entry_len); 158 159 /* Discard if request length mismatched */ 160 if (pcie_doe_get_obj_len(req) < 161 DIV_ROUND_UP(sizeof(CDATReq), sizeof(uint32_t))) { 162 return false; 163 } 164 165 ent = req->entry_handle; 166 base = cdat->entry[ent].base; 167 len = cdat->entry[ent].length; 168 169 rsp = (CDATRsp) { 170 .header = { 171 .vendor_id = CXL_VENDOR_ID, 172 .data_obj_type = CXL_DOE_TABLE_ACCESS, 173 .reserved = 0x0, 174 .length = DIV_ROUND_UP((sizeof(rsp) + len), sizeof(uint32_t)), 175 }, 176 .rsp_code = CXL_DOE_TAB_RSP, 177 .table_type = CXL_DOE_TAB_TYPE_CDAT, 178 .entry_handle = (ent < cdat->entry_len - 1) ? 179 ent + 1 : CXL_DOE_TAB_ENT_MAX, 180 }; 181 182 memcpy(doe_cap->read_mbox, &rsp, sizeof(rsp)); 183 memcpy(doe_cap->read_mbox + DIV_ROUND_UP(sizeof(rsp), sizeof(uint32_t)), 184 base, len); 185 186 doe_cap->read_mbox_len += rsp.header.length; 187 188 return true; 189 } 190 191 static DOEProtocol doe_cdat_prot[] = { 192 { CXL_VENDOR_ID, CXL_DOE_TABLE_ACCESS, cxl_doe_cdat_rsp }, 193 { } 194 }; 195 196 enum { 197 CXL_USP_CDAT_SSLBIS_LAT, 198 CXL_USP_CDAT_SSLBIS_BW, 199 CXL_USP_CDAT_NUM_ENTRIES 200 }; 201 202 static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv) 203 { 204 g_autofree CDATSslbis *sslbis_latency = NULL; 205 g_autofree CDATSslbis *sslbis_bandwidth = NULL; 206 CXLUpstreamPort *us = CXL_USP(priv); 207 PCIBus *bus = &PCI_BRIDGE(us)->sec_bus; 208 int devfn, sslbis_size, i; 209 int count = 0; 210 uint16_t port_ids[256]; 211 212 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 213 PCIDevice *d = bus->devices[devfn]; 214 PCIEPort *port; 215 216 if (!d || !pci_is_express(d) || !d->exp.exp_cap) { 217 continue; 218 } 219 220 /* 221 * Whilst the PCI express spec doesn't allow anything other than 222 * downstream ports on this bus, let us be a little paranoid 223 */ 224 if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { 225 continue; 226 } 227 228 port = PCIE_PORT(d); 229 port_ids[count] = port->port; 230 count++; 231 } 232 233 /* May not yet have any ports - try again later */ 234 if (count == 0) { 235 return 0; 236 } 237 238 sslbis_size = sizeof(CDATSslbis) + sizeof(*sslbis_latency->sslbe) * count; 239 sslbis_latency = g_malloc(sslbis_size); 240 if (!sslbis_latency) { 241 return -ENOMEM; 242 } 243 *sslbis_latency = (CDATSslbis) { 244 .sslbis_header = { 245 .header = { 246 .type = CDAT_TYPE_SSLBIS, 247 .length = sslbis_size, 248 }, 249 .data_type = HMATLB_DATA_TYPE_ACCESS_LATENCY, 250 .entry_base_unit = 10000, 251 }, 252 }; 253 254 for (i = 0; i < count; i++) { 255 sslbis_latency->sslbe[i] = (CDATSslbe) { 256 .port_x_id = CDAT_PORT_ID_USP, 257 .port_y_id = port_ids[i], 258 .latency_bandwidth = 15, /* 150ns */ 259 }; 260 } 261 262 sslbis_bandwidth = g_malloc(sslbis_size); 263 if (!sslbis_bandwidth) { 264 return 0; 265 } 266 *sslbis_bandwidth = (CDATSslbis) { 267 .sslbis_header = { 268 .header = { 269 .type = CDAT_TYPE_SSLBIS, 270 .length = sslbis_size, 271 }, 272 .data_type = HMATLB_DATA_TYPE_ACCESS_BANDWIDTH, 273 .entry_base_unit = 1024, 274 }, 275 }; 276 277 for (i = 0; i < count; i++) { 278 sslbis_bandwidth->sslbe[i] = (CDATSslbe) { 279 .port_x_id = CDAT_PORT_ID_USP, 280 .port_y_id = port_ids[i], 281 .latency_bandwidth = 16, /* 16 GB/s */ 282 }; 283 } 284 285 *cdat_table = g_new0(CDATSubHeader *, CXL_USP_CDAT_NUM_ENTRIES); 286 287 /* Header always at start of structure */ 288 (*cdat_table)[CXL_USP_CDAT_SSLBIS_LAT] = g_steal_pointer(&sslbis_latency); 289 (*cdat_table)[CXL_USP_CDAT_SSLBIS_BW] = g_steal_pointer(&sslbis_bandwidth); 290 291 return CXL_USP_CDAT_NUM_ENTRIES; 292 } 293 294 static void free_default_cdat_table(CDATSubHeader **cdat_table, int num, 295 void *priv) 296 { 297 int i; 298 299 for (i = 0; i < num; i++) { 300 g_free(cdat_table[i]); 301 } 302 g_free(cdat_table); 303 } 304 305 static void cxl_usp_realize(PCIDevice *d, Error **errp) 306 { 307 PCIEPort *p = PCIE_PORT(d); 308 CXLUpstreamPort *usp = CXL_USP(d); 309 CXLComponentState *cxl_cstate = &usp->cxl_cstate; 310 ComponentRegisters *cregs = &cxl_cstate->crb; 311 MemoryRegion *component_bar = &cregs->component_registers; 312 int rc; 313 314 pci_bridge_initfn(d, TYPE_PCIE_BUS); 315 pcie_port_init_reg(d); 316 317 rc = msi_init(d, CXL_UPSTREAM_PORT_MSI_OFFSET, 318 CXL_UPSTREAM_PORT_MSI_NR_VECTOR, true, true, errp); 319 if (rc) { 320 assert(rc == -ENOTSUP); 321 goto err_bridge; 322 } 323 324 rc = pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET, 325 PCI_EXP_TYPE_UPSTREAM, p->port, errp); 326 if (rc < 0) { 327 goto err_msi; 328 } 329 330 pcie_cap_flr_init(d); 331 pcie_cap_deverr_init(d); 332 rc = pcie_aer_init(d, PCI_ERR_VER, CXL_UPSTREAM_PORT_AER_OFFSET, 333 PCI_ERR_SIZEOF, errp); 334 if (rc) { 335 goto err_cap; 336 } 337 if (usp->sn != UI64_NULL) { 338 pcie_dev_ser_num_init(d, CXL_UPSTREAM_PORT_SN_OFFSET, usp->sn); 339 } 340 cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET; 341 cxl_cstate->pdev = d; 342 build_dvsecs(cxl_cstate); 343 cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_USP); 344 pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX, 345 PCI_BASE_ADDRESS_SPACE_MEMORY | 346 PCI_BASE_ADDRESS_MEM_TYPE_64, 347 component_bar); 348 349 pcie_doe_init(d, &usp->doe_cdat, cxl_cstate->dvsec_offset, doe_cdat_prot, 350 true, 1); 351 352 cxl_cstate->cdat.build_cdat_table = build_cdat_table; 353 cxl_cstate->cdat.free_cdat_table = free_default_cdat_table; 354 cxl_cstate->cdat.private = d; 355 cxl_doe_cdat_init(cxl_cstate, errp); 356 if (*errp) { 357 goto err_cap; 358 } 359 360 return; 361 362 err_cap: 363 pcie_cap_exit(d); 364 err_msi: 365 msi_uninit(d); 366 err_bridge: 367 pci_bridge_exitfn(d); 368 } 369 370 static void cxl_usp_exitfn(PCIDevice *d) 371 { 372 pcie_aer_exit(d); 373 pcie_cap_exit(d); 374 msi_uninit(d); 375 pci_bridge_exitfn(d); 376 } 377 378 static Property cxl_upstream_props[] = { 379 DEFINE_PROP_UINT64("sn", CXLUpstreamPort, sn, UI64_NULL), 380 DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename), 381 DEFINE_PROP_END_OF_LIST() 382 }; 383 384 static void cxl_upstream_class_init(ObjectClass *oc, void *data) 385 { 386 DeviceClass *dc = DEVICE_CLASS(oc); 387 PCIDeviceClass *k = PCI_DEVICE_CLASS(oc); 388 389 k->config_write = cxl_usp_write_config; 390 k->config_read = cxl_usp_read_config; 391 k->realize = cxl_usp_realize; 392 k->exit = cxl_usp_exitfn; 393 k->vendor_id = 0x19e5; /* Huawei */ 394 k->device_id = 0xa128; /* Emulated CXL Switch Upstream Port */ 395 k->revision = 0; 396 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 397 dc->desc = "CXL Switch Upstream Port"; 398 dc->reset = cxl_usp_reset; 399 device_class_set_props(dc, cxl_upstream_props); 400 } 401 402 static const TypeInfo cxl_usp_info = { 403 .name = TYPE_CXL_USP, 404 .parent = TYPE_PCIE_PORT, 405 .instance_size = sizeof(CXLUpstreamPort), 406 .class_init = cxl_upstream_class_init, 407 .interfaces = (InterfaceInfo[]) { 408 { INTERFACE_PCIE_DEVICE }, 409 { INTERFACE_CXL_DEVICE }, 410 { } 411 }, 412 }; 413 414 static void cxl_usp_register_type(void) 415 { 416 type_register_static(&cxl_usp_info); 417 } 418 419 type_init(cxl_usp_register_type); 420