1 /* 2 * ioh3420.c 3 * Intel X58 north bridge IOH 4 * PCI Express root port device id 3420 5 * 6 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/pci/pci_ids.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pcie.h" 27 #include "ioh3420.h" 28 29 #define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ 30 #define PCI_DEVICE_ID_IOH_REV 0x2 31 #define IOH_EP_SSVID_OFFSET 0x40 32 #define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL 33 #define IOH_EP_SSVID_SSID 0 34 #define IOH_EP_MSI_OFFSET 0x60 35 #define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT 36 #define IOH_EP_MSI_NR_VECTOR 2 37 #define IOH_EP_EXP_OFFSET 0x90 38 #define IOH_EP_AER_OFFSET 0x100 39 40 /* 41 * If two MSI vector are allocated, Advanced Error Interrupt Message Number 42 * is 1. otherwise 0. 43 * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. 44 */ 45 static uint8_t ioh3420_aer_vector(const PCIDevice *d) 46 { 47 switch (msi_nr_vectors_allocated(d)) { 48 case 1: 49 return 0; 50 case 2: 51 return 1; 52 case 4: 53 case 8: 54 case 16: 55 case 32: 56 default: 57 break; 58 } 59 abort(); 60 return 0; 61 } 62 63 static void ioh3420_aer_vector_update(PCIDevice *d) 64 { 65 pcie_aer_root_set_vector(d, ioh3420_aer_vector(d)); 66 } 67 68 static void ioh3420_write_config(PCIDevice *d, 69 uint32_t address, uint32_t val, int len) 70 { 71 uint32_t root_cmd = 72 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); 73 74 pci_bridge_write_config(d, address, val, len); 75 ioh3420_aer_vector_update(d); 76 pcie_cap_slot_write_config(d, address, val, len); 77 pcie_aer_write_config(d, address, val, len); 78 pcie_aer_root_write_config(d, address, val, len, root_cmd); 79 } 80 81 static void ioh3420_reset(DeviceState *qdev) 82 { 83 PCIDevice *d = PCI_DEVICE(qdev); 84 85 ioh3420_aer_vector_update(d); 86 pcie_cap_root_reset(d); 87 pcie_cap_deverr_reset(d); 88 pcie_cap_slot_reset(d); 89 pcie_cap_arifwd_reset(d); 90 pcie_aer_root_reset(d); 91 pci_bridge_reset(qdev); 92 pci_bridge_disable_base_limit(d); 93 } 94 95 static int ioh3420_initfn(PCIDevice *d) 96 { 97 PCIEPort *p = PCIE_PORT(d); 98 PCIESlot *s = PCIE_SLOT(d); 99 int rc; 100 101 pci_bridge_initfn(d, TYPE_PCIE_BUS); 102 pcie_port_init_reg(d); 103 104 rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET, 105 IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID); 106 if (rc < 0) { 107 goto err_bridge; 108 } 109 110 rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR, 111 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, 112 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); 113 if (rc < 0) { 114 goto err_bridge; 115 } 116 117 rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port); 118 if (rc < 0) { 119 goto err_msi; 120 } 121 122 pcie_cap_arifwd_init(d); 123 pcie_cap_deverr_init(d); 124 pcie_cap_slot_init(d, s->slot); 125 pcie_cap_root_init(d); 126 127 pcie_chassis_create(s->chassis); 128 rc = pcie_chassis_add_slot(s); 129 if (rc < 0) { 130 goto err_pcie_cap; 131 } 132 133 rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF); 134 if (rc < 0) { 135 goto err; 136 } 137 pcie_aer_root_init(d); 138 ioh3420_aer_vector_update(d); 139 140 return 0; 141 142 err: 143 pcie_chassis_del_slot(s); 144 err_pcie_cap: 145 pcie_cap_exit(d); 146 err_msi: 147 msi_uninit(d); 148 err_bridge: 149 pci_bridge_exitfn(d); 150 return rc; 151 } 152 153 static void ioh3420_exitfn(PCIDevice *d) 154 { 155 PCIESlot *s = PCIE_SLOT(d); 156 157 pcie_aer_exit(d); 158 pcie_chassis_del_slot(s); 159 pcie_cap_exit(d); 160 msi_uninit(d); 161 pci_bridge_exitfn(d); 162 } 163 164 static Property ioh3420_props[] = { 165 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, 166 QEMU_PCIE_SLTCAP_PCP_BITNR, true), 167 DEFINE_PROP_END_OF_LIST() 168 }; 169 170 static const VMStateDescription vmstate_ioh3420 = { 171 .name = "ioh-3240-express-root-port", 172 .version_id = 1, 173 .minimum_version_id = 1, 174 .post_load = pcie_cap_slot_post_load, 175 .fields = (VMStateField[]) { 176 VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), 177 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, 178 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), 179 VMSTATE_END_OF_LIST() 180 } 181 }; 182 183 static void ioh3420_class_init(ObjectClass *klass, void *data) 184 { 185 DeviceClass *dc = DEVICE_CLASS(klass); 186 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 187 188 k->is_express = 1; 189 k->is_bridge = 1; 190 k->config_write = ioh3420_write_config; 191 k->init = ioh3420_initfn; 192 k->exit = ioh3420_exitfn; 193 k->vendor_id = PCI_VENDOR_ID_INTEL; 194 k->device_id = PCI_DEVICE_ID_IOH_EPORT; 195 k->revision = PCI_DEVICE_ID_IOH_REV; 196 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 197 dc->desc = "Intel IOH device id 3420 PCIE Root Port"; 198 dc->reset = ioh3420_reset; 199 dc->vmsd = &vmstate_ioh3420; 200 dc->props = ioh3420_props; 201 } 202 203 static const TypeInfo ioh3420_info = { 204 .name = "ioh3420", 205 .parent = TYPE_PCIE_SLOT, 206 .class_init = ioh3420_class_init, 207 }; 208 209 static void ioh3420_register_types(void) 210 { 211 type_register_static(&ioh3420_info); 212 } 213 214 type_init(ioh3420_register_types) 215 216 /* 217 * Local variables: 218 * c-indent-level: 4 219 * c-basic-offset: 4 220 * tab-width: 8 221 * indent-tab-mode: nil 222 * End: 223 */ 224