1 /* 2 * ioh3420.c 3 * Intel X58 north bridge IOH 4 * PCI Express root port device id 3420 5 * 6 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/pci/pci_ids.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pcie.h" 27 #include "ioh3420.h" 28 #include "qapi/error.h" 29 30 #define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ 31 #define PCI_DEVICE_ID_IOH_REV 0x2 32 #define IOH_EP_SSVID_OFFSET 0x40 33 #define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL 34 #define IOH_EP_SSVID_SSID 0 35 #define IOH_EP_MSI_OFFSET 0x60 36 #define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT 37 #define IOH_EP_MSI_NR_VECTOR 2 38 #define IOH_EP_EXP_OFFSET 0x90 39 #define IOH_EP_AER_OFFSET 0x100 40 41 /* 42 * If two MSI vector are allocated, Advanced Error Interrupt Message Number 43 * is 1. otherwise 0. 44 * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. 45 */ 46 static uint8_t ioh3420_aer_vector(const PCIDevice *d) 47 { 48 switch (msi_nr_vectors_allocated(d)) { 49 case 1: 50 return 0; 51 case 2: 52 return 1; 53 case 4: 54 case 8: 55 case 16: 56 case 32: 57 default: 58 break; 59 } 60 abort(); 61 return 0; 62 } 63 64 static void ioh3420_aer_vector_update(PCIDevice *d) 65 { 66 pcie_aer_root_set_vector(d, ioh3420_aer_vector(d)); 67 } 68 69 static void ioh3420_write_config(PCIDevice *d, 70 uint32_t address, uint32_t val, int len) 71 { 72 uint32_t root_cmd = 73 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); 74 75 pci_bridge_write_config(d, address, val, len); 76 ioh3420_aer_vector_update(d); 77 pcie_cap_slot_write_config(d, address, val, len); 78 pcie_aer_write_config(d, address, val, len); 79 pcie_aer_root_write_config(d, address, val, len, root_cmd); 80 } 81 82 static void ioh3420_reset(DeviceState *qdev) 83 { 84 PCIDevice *d = PCI_DEVICE(qdev); 85 86 ioh3420_aer_vector_update(d); 87 pcie_cap_root_reset(d); 88 pcie_cap_deverr_reset(d); 89 pcie_cap_slot_reset(d); 90 pcie_cap_arifwd_reset(d); 91 pcie_aer_root_reset(d); 92 pci_bridge_reset(qdev); 93 pci_bridge_disable_base_limit(d); 94 } 95 96 static int ioh3420_initfn(PCIDevice *d) 97 { 98 PCIEPort *p = PCIE_PORT(d); 99 PCIESlot *s = PCIE_SLOT(d); 100 int rc; 101 Error *err = NULL; 102 103 pci_config_set_interrupt_pin(d->config, 1); 104 pci_bridge_initfn(d, TYPE_PCIE_BUS); 105 pcie_port_init_reg(d); 106 107 rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET, 108 IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID); 109 if (rc < 0) { 110 goto err_bridge; 111 } 112 113 rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR, 114 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, 115 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err); 116 if (rc < 0) { 117 assert(rc == -ENOTSUP); 118 error_report_err(err); 119 goto err_bridge; 120 } 121 122 rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port); 123 if (rc < 0) { 124 goto err_msi; 125 } 126 127 pcie_cap_arifwd_init(d); 128 pcie_cap_deverr_init(d); 129 pcie_cap_slot_init(d, s->slot); 130 pcie_cap_root_init(d); 131 132 pcie_chassis_create(s->chassis); 133 rc = pcie_chassis_add_slot(s); 134 if (rc < 0) { 135 goto err_pcie_cap; 136 } 137 138 rc = pcie_aer_init(d, PCI_ERR_VER, IOH_EP_AER_OFFSET, 139 PCI_ERR_SIZEOF, &err); 140 if (rc < 0) { 141 error_report_err(err); 142 goto err; 143 } 144 pcie_aer_root_init(d); 145 ioh3420_aer_vector_update(d); 146 147 return 0; 148 149 err: 150 pcie_chassis_del_slot(s); 151 err_pcie_cap: 152 pcie_cap_exit(d); 153 err_msi: 154 msi_uninit(d); 155 err_bridge: 156 pci_bridge_exitfn(d); 157 return rc; 158 } 159 160 static void ioh3420_exitfn(PCIDevice *d) 161 { 162 PCIESlot *s = PCIE_SLOT(d); 163 164 pcie_aer_exit(d); 165 pcie_chassis_del_slot(s); 166 pcie_cap_exit(d); 167 msi_uninit(d); 168 pci_bridge_exitfn(d); 169 } 170 171 static Property ioh3420_props[] = { 172 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, 173 QEMU_PCIE_SLTCAP_PCP_BITNR, true), 174 DEFINE_PROP_END_OF_LIST() 175 }; 176 177 static const VMStateDescription vmstate_ioh3420 = { 178 .name = "ioh-3240-express-root-port", 179 .version_id = 1, 180 .minimum_version_id = 1, 181 .post_load = pcie_cap_slot_post_load, 182 .fields = (VMStateField[]) { 183 VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), 184 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, 185 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), 186 VMSTATE_END_OF_LIST() 187 } 188 }; 189 190 static void ioh3420_class_init(ObjectClass *klass, void *data) 191 { 192 DeviceClass *dc = DEVICE_CLASS(klass); 193 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 194 195 k->is_express = 1; 196 k->is_bridge = 1; 197 k->config_write = ioh3420_write_config; 198 k->init = ioh3420_initfn; 199 k->exit = ioh3420_exitfn; 200 k->vendor_id = PCI_VENDOR_ID_INTEL; 201 k->device_id = PCI_DEVICE_ID_IOH_EPORT; 202 k->revision = PCI_DEVICE_ID_IOH_REV; 203 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 204 dc->desc = "Intel IOH device id 3420 PCIE Root Port"; 205 dc->reset = ioh3420_reset; 206 dc->vmsd = &vmstate_ioh3420; 207 dc->props = ioh3420_props; 208 } 209 210 static const TypeInfo ioh3420_info = { 211 .name = "ioh3420", 212 .parent = TYPE_PCIE_SLOT, 213 .class_init = ioh3420_class_init, 214 }; 215 216 static void ioh3420_register_types(void) 217 { 218 type_register_static(&ioh3420_info); 219 } 220 221 type_init(ioh3420_register_types) 222