1 /* 2 * x3130_downstream.c 3 * TI X3130 pci express downstream port switch 4 * 5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 6 * VA Linux Systems Japan K.K. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/pci/pci_ids.h" 24 #include "hw/pci/msi.h" 25 #include "hw/pci/pcie.h" 26 #include "xio3130_downstream.h" 27 28 #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */ 29 #define XIO3130_REVISION 0x1 30 #define XIO3130_MSI_OFFSET 0x70 31 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT 32 #define XIO3130_MSI_NR_VECTOR 1 33 #define XIO3130_SSVID_OFFSET 0x80 34 #define XIO3130_SSVID_SVID 0 35 #define XIO3130_SSVID_SSID 0 36 #define XIO3130_EXP_OFFSET 0x90 37 #define XIO3130_AER_OFFSET 0x100 38 39 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, 40 uint32_t val, int len) 41 { 42 pci_bridge_write_config(d, address, val, len); 43 pcie_cap_flr_write_config(d, address, val, len); 44 pcie_cap_slot_write_config(d, address, val, len); 45 pcie_aer_write_config(d, address, val, len); 46 } 47 48 static void xio3130_downstream_reset(DeviceState *qdev) 49 { 50 PCIDevice *d = PCI_DEVICE(qdev); 51 52 pcie_cap_deverr_reset(d); 53 pcie_cap_slot_reset(d); 54 pcie_cap_arifwd_reset(d); 55 pci_bridge_reset(qdev); 56 } 57 58 static int xio3130_downstream_initfn(PCIDevice *d) 59 { 60 PCIEPort *p = PCIE_PORT(d); 61 PCIESlot *s = PCIE_SLOT(d); 62 int rc; 63 64 pci_bridge_initfn(d, TYPE_PCIE_BUS); 65 pcie_port_init_reg(d); 66 67 rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, 68 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, 69 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); 70 if (rc < 0) { 71 goto err_bridge; 72 } 73 74 rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, 75 XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); 76 if (rc < 0) { 77 goto err_bridge; 78 } 79 80 rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, 81 p->port); 82 if (rc < 0) { 83 goto err_msi; 84 } 85 pcie_cap_flr_init(d); 86 pcie_cap_deverr_init(d); 87 pcie_cap_slot_init(d, s->slot); 88 pcie_cap_arifwd_init(d); 89 90 pcie_chassis_create(s->chassis); 91 rc = pcie_chassis_add_slot(s); 92 if (rc < 0) { 93 goto err_pcie_cap; 94 } 95 96 rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); 97 if (rc < 0) { 98 goto err; 99 } 100 101 return 0; 102 103 err: 104 pcie_chassis_del_slot(s); 105 err_pcie_cap: 106 pcie_cap_exit(d); 107 err_msi: 108 msi_uninit(d); 109 err_bridge: 110 pci_bridge_exitfn(d); 111 return rc; 112 } 113 114 static void xio3130_downstream_exitfn(PCIDevice *d) 115 { 116 PCIESlot *s = PCIE_SLOT(d); 117 118 pcie_aer_exit(d); 119 pcie_chassis_del_slot(s); 120 pcie_cap_exit(d); 121 msi_uninit(d); 122 pci_bridge_exitfn(d); 123 } 124 125 PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction, 126 const char *bus_name, pci_map_irq_fn map_irq, 127 uint8_t port, uint8_t chassis, 128 uint16_t slot) 129 { 130 PCIDevice *d; 131 PCIBridge *br; 132 DeviceState *qdev; 133 134 d = pci_create_multifunction(bus, devfn, multifunction, 135 "xio3130-downstream"); 136 if (!d) { 137 return NULL; 138 } 139 br = PCI_BRIDGE(d); 140 141 qdev = DEVICE(d); 142 pci_bridge_map_irq(br, bus_name, map_irq); 143 qdev_prop_set_uint8(qdev, "port", port); 144 qdev_prop_set_uint8(qdev, "chassis", chassis); 145 qdev_prop_set_uint16(qdev, "slot", slot); 146 qdev_init_nofail(qdev); 147 148 return PCIE_SLOT(d); 149 } 150 151 static Property xio3130_downstream_props[] = { 152 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, 153 QEMU_PCIE_SLTCAP_PCP_BITNR, true), 154 DEFINE_PROP_END_OF_LIST() 155 }; 156 157 static const VMStateDescription vmstate_xio3130_downstream = { 158 .name = "xio3130-express-downstream-port", 159 .version_id = 1, 160 .minimum_version_id = 1, 161 .post_load = pcie_cap_slot_post_load, 162 .fields = (VMStateField[]) { 163 VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), 164 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, 165 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), 166 VMSTATE_END_OF_LIST() 167 } 168 }; 169 170 static void xio3130_downstream_class_init(ObjectClass *klass, void *data) 171 { 172 DeviceClass *dc = DEVICE_CLASS(klass); 173 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 174 175 k->is_express = 1; 176 k->is_bridge = 1; 177 k->config_write = xio3130_downstream_write_config; 178 k->init = xio3130_downstream_initfn; 179 k->exit = xio3130_downstream_exitfn; 180 k->vendor_id = PCI_VENDOR_ID_TI; 181 k->device_id = PCI_DEVICE_ID_TI_XIO3130D; 182 k->revision = XIO3130_REVISION; 183 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 184 dc->desc = "TI X3130 Downstream Port of PCI Express Switch"; 185 dc->reset = xio3130_downstream_reset; 186 dc->vmsd = &vmstate_xio3130_downstream; 187 dc->props = xio3130_downstream_props; 188 } 189 190 static const TypeInfo xio3130_downstream_info = { 191 .name = "xio3130-downstream", 192 .parent = TYPE_PCIE_SLOT, 193 .class_init = xio3130_downstream_class_init, 194 }; 195 196 static void xio3130_downstream_register_types(void) 197 { 198 type_register_static(&xio3130_downstream_info); 199 } 200 201 type_init(xio3130_downstream_register_types) 202 203 /* 204 * Local variables: 205 * c-indent-level: 4 206 * c-basic-offset: 4 207 * tab-width: 8 208 * indent-tab-mode: nil 209 * End: 210 */ 211