1 /* 2 * x3130_downstream.c 3 * TI X3130 pci express downstream port switch 4 * 5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 6 * VA Linux Systems Japan K.K. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/pci/pci_ids.h" 24 #include "hw/pci/msi.h" 25 #include "hw/pci/pcie.h" 26 #include "xio3130_downstream.h" 27 #include "qapi/error.h" 28 29 #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */ 30 #define XIO3130_REVISION 0x1 31 #define XIO3130_MSI_OFFSET 0x70 32 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT 33 #define XIO3130_MSI_NR_VECTOR 1 34 #define XIO3130_SSVID_OFFSET 0x80 35 #define XIO3130_SSVID_SVID 0 36 #define XIO3130_SSVID_SSID 0 37 #define XIO3130_EXP_OFFSET 0x90 38 #define XIO3130_AER_OFFSET 0x100 39 40 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, 41 uint32_t val, int len) 42 { 43 pci_bridge_write_config(d, address, val, len); 44 pcie_cap_flr_write_config(d, address, val, len); 45 pcie_cap_slot_write_config(d, address, val, len); 46 pcie_aer_write_config(d, address, val, len); 47 } 48 49 static void xio3130_downstream_reset(DeviceState *qdev) 50 { 51 PCIDevice *d = PCI_DEVICE(qdev); 52 53 pcie_cap_deverr_reset(d); 54 pcie_cap_slot_reset(d); 55 pcie_cap_arifwd_reset(d); 56 pci_bridge_reset(qdev); 57 } 58 59 static int xio3130_downstream_initfn(PCIDevice *d) 60 { 61 PCIEPort *p = PCIE_PORT(d); 62 PCIESlot *s = PCIE_SLOT(d); 63 int rc; 64 Error *err = NULL; 65 66 pci_bridge_initfn(d, TYPE_PCIE_BUS); 67 pcie_port_init_reg(d); 68 69 rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, 70 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, 71 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err); 72 if (rc < 0) { 73 assert(rc == -ENOTSUP); 74 error_report_err(err); 75 goto err_bridge; 76 } 77 78 rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, 79 XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); 80 if (rc < 0) { 81 goto err_bridge; 82 } 83 84 rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, 85 p->port); 86 if (rc < 0) { 87 goto err_msi; 88 } 89 pcie_cap_flr_init(d); 90 pcie_cap_deverr_init(d); 91 pcie_cap_slot_init(d, s->slot); 92 pcie_cap_arifwd_init(d); 93 94 pcie_chassis_create(s->chassis); 95 rc = pcie_chassis_add_slot(s); 96 if (rc < 0) { 97 goto err_pcie_cap; 98 } 99 100 rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, 101 PCI_ERR_SIZEOF, &err); 102 if (rc < 0) { 103 error_report_err(err); 104 goto err; 105 } 106 107 return 0; 108 109 err: 110 pcie_chassis_del_slot(s); 111 err_pcie_cap: 112 pcie_cap_exit(d); 113 err_msi: 114 msi_uninit(d); 115 err_bridge: 116 pci_bridge_exitfn(d); 117 return rc; 118 } 119 120 static void xio3130_downstream_exitfn(PCIDevice *d) 121 { 122 PCIESlot *s = PCIE_SLOT(d); 123 124 pcie_aer_exit(d); 125 pcie_chassis_del_slot(s); 126 pcie_cap_exit(d); 127 msi_uninit(d); 128 pci_bridge_exitfn(d); 129 } 130 131 PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction, 132 const char *bus_name, pci_map_irq_fn map_irq, 133 uint8_t port, uint8_t chassis, 134 uint16_t slot) 135 { 136 PCIDevice *d; 137 PCIBridge *br; 138 DeviceState *qdev; 139 140 d = pci_create_multifunction(bus, devfn, multifunction, 141 "xio3130-downstream"); 142 if (!d) { 143 return NULL; 144 } 145 br = PCI_BRIDGE(d); 146 147 qdev = DEVICE(d); 148 pci_bridge_map_irq(br, bus_name, map_irq); 149 qdev_prop_set_uint8(qdev, "port", port); 150 qdev_prop_set_uint8(qdev, "chassis", chassis); 151 qdev_prop_set_uint16(qdev, "slot", slot); 152 qdev_init_nofail(qdev); 153 154 return PCIE_SLOT(d); 155 } 156 157 static Property xio3130_downstream_props[] = { 158 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, 159 QEMU_PCIE_SLTCAP_PCP_BITNR, true), 160 DEFINE_PROP_END_OF_LIST() 161 }; 162 163 static const VMStateDescription vmstate_xio3130_downstream = { 164 .name = "xio3130-express-downstream-port", 165 .version_id = 1, 166 .minimum_version_id = 1, 167 .post_load = pcie_cap_slot_post_load, 168 .fields = (VMStateField[]) { 169 VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), 170 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, 171 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), 172 VMSTATE_END_OF_LIST() 173 } 174 }; 175 176 static void xio3130_downstream_class_init(ObjectClass *klass, void *data) 177 { 178 DeviceClass *dc = DEVICE_CLASS(klass); 179 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 180 181 k->is_express = 1; 182 k->is_bridge = 1; 183 k->config_write = xio3130_downstream_write_config; 184 k->init = xio3130_downstream_initfn; 185 k->exit = xio3130_downstream_exitfn; 186 k->vendor_id = PCI_VENDOR_ID_TI; 187 k->device_id = PCI_DEVICE_ID_TI_XIO3130D; 188 k->revision = XIO3130_REVISION; 189 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 190 dc->desc = "TI X3130 Downstream Port of PCI Express Switch"; 191 dc->reset = xio3130_downstream_reset; 192 dc->vmsd = &vmstate_xio3130_downstream; 193 dc->props = xio3130_downstream_props; 194 } 195 196 static const TypeInfo xio3130_downstream_info = { 197 .name = "xio3130-downstream", 198 .parent = TYPE_PCIE_SLOT, 199 .class_init = xio3130_downstream_class_init, 200 }; 201 202 static void xio3130_downstream_register_types(void) 203 { 204 type_register_static(&xio3130_downstream_info); 205 } 206 207 type_init(xio3130_downstream_register_types) 208