1 /* 2 * xio3130_upstream.c 3 * TI X3130 pci express upstream port switch 4 * 5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 6 * VA Linux Systems Japan K.K. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/pci/pci_ids.h" 24 #include "hw/pci/msi.h" 25 #include "hw/pci/pcie.h" 26 #include "xio3130_upstream.h" 27 28 #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ 29 #define XIO3130_REVISION 0x2 30 #define XIO3130_MSI_OFFSET 0x70 31 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT 32 #define XIO3130_MSI_NR_VECTOR 1 33 #define XIO3130_SSVID_OFFSET 0x80 34 #define XIO3130_SSVID_SVID 0 35 #define XIO3130_SSVID_SSID 0 36 #define XIO3130_EXP_OFFSET 0x90 37 #define XIO3130_AER_OFFSET 0x100 38 39 static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, 40 uint32_t val, int len) 41 { 42 pci_bridge_write_config(d, address, val, len); 43 pcie_cap_flr_write_config(d, address, val, len); 44 pcie_aer_write_config(d, address, val, len); 45 } 46 47 static void xio3130_upstream_reset(DeviceState *qdev) 48 { 49 PCIDevice *d = PCI_DEVICE(qdev); 50 51 pci_bridge_reset(qdev); 52 pcie_cap_deverr_reset(d); 53 } 54 55 static int xio3130_upstream_initfn(PCIDevice *d) 56 { 57 PCIEPort *p = PCIE_PORT(d); 58 int rc; 59 60 rc = pci_bridge_initfn(d, TYPE_PCIE_BUS); 61 if (rc < 0) { 62 return rc; 63 } 64 65 pcie_port_init_reg(d); 66 67 rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, 68 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, 69 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); 70 if (rc < 0) { 71 goto err_bridge; 72 } 73 rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, 74 XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); 75 if (rc < 0) { 76 goto err_bridge; 77 } 78 rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, 79 p->port); 80 if (rc < 0) { 81 goto err_msi; 82 } 83 pcie_cap_flr_init(d); 84 pcie_cap_deverr_init(d); 85 rc = pcie_aer_init(d, XIO3130_AER_OFFSET); 86 if (rc < 0) { 87 goto err; 88 } 89 90 return 0; 91 92 err: 93 pcie_cap_exit(d); 94 err_msi: 95 msi_uninit(d); 96 err_bridge: 97 pci_bridge_exitfn(d); 98 return rc; 99 } 100 101 static void xio3130_upstream_exitfn(PCIDevice *d) 102 { 103 pcie_aer_exit(d); 104 pcie_cap_exit(d); 105 msi_uninit(d); 106 pci_bridge_exitfn(d); 107 } 108 109 PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction, 110 const char *bus_name, pci_map_irq_fn map_irq, 111 uint8_t port) 112 { 113 PCIDevice *d; 114 PCIBridge *br; 115 DeviceState *qdev; 116 117 d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream"); 118 if (!d) { 119 return NULL; 120 } 121 br = PCI_BRIDGE(d); 122 123 qdev = DEVICE(d); 124 pci_bridge_map_irq(br, bus_name, map_irq); 125 qdev_prop_set_uint8(qdev, "port", port); 126 qdev_init_nofail(qdev); 127 128 return PCIE_PORT(d); 129 } 130 131 static const VMStateDescription vmstate_xio3130_upstream = { 132 .name = "xio3130-express-upstream-port", 133 .version_id = 1, 134 .minimum_version_id = 1, 135 .fields = (VMStateField[]) { 136 VMSTATE_PCIE_DEVICE(parent_obj.parent_obj, PCIEPort), 137 VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0, 138 vmstate_pcie_aer_log, PCIEAERLog), 139 VMSTATE_END_OF_LIST() 140 } 141 }; 142 143 static void xio3130_upstream_class_init(ObjectClass *klass, void *data) 144 { 145 DeviceClass *dc = DEVICE_CLASS(klass); 146 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 147 148 k->is_express = 1; 149 k->is_bridge = 1; 150 k->config_write = xio3130_upstream_write_config; 151 k->init = xio3130_upstream_initfn; 152 k->exit = xio3130_upstream_exitfn; 153 k->vendor_id = PCI_VENDOR_ID_TI; 154 k->device_id = PCI_DEVICE_ID_TI_XIO3130U; 155 k->revision = XIO3130_REVISION; 156 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 157 dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; 158 dc->reset = xio3130_upstream_reset; 159 dc->vmsd = &vmstate_xio3130_upstream; 160 } 161 162 static const TypeInfo xio3130_upstream_info = { 163 .name = "x3130-upstream", 164 .parent = TYPE_PCIE_PORT, 165 .class_init = xio3130_upstream_class_init, 166 }; 167 168 static void xio3130_upstream_register_types(void) 169 { 170 type_register_static(&xio3130_upstream_info); 171 } 172 173 type_init(xio3130_upstream_register_types) 174 175 176 /* 177 * Local variables: 178 * c-indent-level: 4 179 * c-basic-offset: 4 180 * tab-width: 8 181 * indent-tab-mode: nil 182 * End: 183 */ 184